JP4978269B2 - 多層配線基板 - Google Patents
多層配線基板 Download PDFInfo
- Publication number
- JP4978269B2 JP4978269B2 JP2007083092A JP2007083092A JP4978269B2 JP 4978269 B2 JP4978269 B2 JP 4978269B2 JP 2007083092 A JP2007083092 A JP 2007083092A JP 2007083092 A JP2007083092 A JP 2007083092A JP 4978269 B2 JP4978269 B2 JP 4978269B2
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- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- electronic component
- area
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09336—Signal conductors in same plane as power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
いずれの従来例においても、図6及び図8に示すように、LSI101を実装する基板の領域にはLSI101と多層配線基板21,22とを接続するための、ハンダボール118用のLSI接続パッド113とスルーホール117が密集しているので、配線を通過させかつ配線の収容性を良くすることを目的として、LSI101の直下の基板の領域の配線の配線幅W1(細幅配線)はスペースの制約があるので細く形成される。一方、LSI101の直下の基板の領域を通過してLSI101の外側の基板の領域に形成される配線の配線幅W2(太幅配線)は、スペースに余裕があるので、信号の減衰を抑えかつ多層配線基板の製造性を良くすることを目的として、太く(W1<W2)形成される。
この例の多層配線基板25のバランス配線は、図1及び図2に示すように、層間膜を介して順次にCOVER2、GND層3、配線層4、配線層5、GND層6が形成された構成において、LSI1の一対のハンダボール18からの一対の信号経路は、LSI1の直下の基板の領域ではそれぞれLSI1の直下のスルーホール17を介して、異なる層の配線層4,5に配線7a、8aが配線幅W1で形成されるとともに、LSI1の外側の基板の領域では一方の配線7aがスルーホール19を介して配線層4aに乗り換えて、配線幅W2の配線7bへ変更されている。また、他方の配線8aはLSI1の外側の基板の領域においても配線層を変更することなく、配線幅W2の配線8bに配線幅のみ変更されている。同様に、一対のGND経路は、LSI1の直下の基板の領域ではそれぞれ異なる層のGND層3,6に形成されるとともに、LSI1の外側の基板の領域では一方のGND層3のみがスルーホールを介してGND層3aに乗り換えられている。ここで、スルーホール19は信号の反射に影響するスタブ(分岐)とならないように、半貫通に形成されていることが望ましい。
したがって、従来のタンデムバランス配線の利点を残したままで、配線の特性インピーダンスの不整合をなくすことで、高品質な信号伝送を可能にするとともに実装する電子部品の動作マージンを確保することができる。
2 COVER層
3、3a、6 GND層
4、4a、5 配線層
7a、7b、8a、8b 配線
9〜12 層間厚
13 LSI接続パッド
14 (同一層バランス配線)横方向配線
15,16 タンデムバランス配線
17,19 スルーホール
18 ハンダボール
25 多層配線基板
Claims (6)
- 実装される電子部品間を伝送する信号の伝送速度の高速化のために必須なバランス配線を備えた多層配線基板であって、
前記バランス配線は、一対の信号経路が前記電子部品の直下の基板の領域ではそれぞれ異なる層の配線層に細幅配線で形成されるとともに、前記電子部品の外側の基板の領域では、前記一対の信号経路のうち、一方の信号経路は、前記電子部品の直下の基板の領域で当該一方の信号経路が形成されている前記配線層と異なる配線層に乗り換えて形成され、かつ両方の信号経路が太幅配線で形成されていることを特徴とする多層配線基板。 - 前記電子部品の外側の基板の領域では、前記一対の信号経路のうち、他方の信号経路は、前記電子部品の直下の基板の領域で当該他方の信号経路が形成されている前記配線層と同一の配線層に形成されていることを特徴とする請求項1記載の多層配線基板。
- 前記バランス配線は、一対のグランド経路が前記電子部品の直下の基板の領域ではそれぞれ異なる層の配線層に形成されるとともに、前記電子部品の外側の基板の領域では、前記一対のグランド経路のうち、一方のグランド経路は、前記電子部品の直下の基板の領域で当該一方のグランド経路が形成されている前記配線層と異なる配線層に乗り換えて形成されていることを特徴とする請求項1又は2記載の多層配線基板。
- 前記電子部品の外側の基板の領域では、前記一対のグランド経路のうち、他方のグランド経路は、前記電子部品の直下の基板の領域で当該他方のグランド経路が形成されている前記配線層と同一の配線層に形成されていることを特徴とする請求項3記載の多層配線基板。
- 前記一方の信号経路あるいは前記一方のグランド経路が半貫通スルーホールを介して前記配線層と異なる配線層に乗り換えることを特徴とする請求項3又は4記載の多層配線基板。
- 前記電子部品が大規模集積回路であることを特徴とする請求項1乃至5のいずれか1つに記載の多層配線基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007083092A JP4978269B2 (ja) | 2007-03-27 | 2007-03-27 | 多層配線基板 |
US12/078,019 US8072774B2 (en) | 2007-03-27 | 2008-03-26 | Substrate including wiring for transmitting signal, apparatus and system including the substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007083092A JP4978269B2 (ja) | 2007-03-27 | 2007-03-27 | 多層配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008244179A JP2008244179A (ja) | 2008-10-09 |
JP4978269B2 true JP4978269B2 (ja) | 2012-07-18 |
Family
ID=39793267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007083092A Expired - Fee Related JP4978269B2 (ja) | 2007-03-27 | 2007-03-27 | 多層配線基板 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8072774B2 (ja) |
JP (1) | JP4978269B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10764991B2 (en) | 2018-08-09 | 2020-09-01 | Samsung Electronics Co., Ltd. | Printed circuit board including overvoltage controlling element and electronic device including the same |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101594729B (zh) * | 2008-05-27 | 2012-06-20 | 鸿富锦精密工业(深圳)有限公司 | 一种可补偿过孔残端电容特性的电路板 |
JP5311653B2 (ja) * | 2009-04-28 | 2013-10-09 | 京セラSlcテクノロジー株式会社 | 配線基板 |
CN102695359A (zh) * | 2011-03-21 | 2012-09-26 | 鸿富锦精密工业(深圳)有限公司 | 具有bga区域的电路板 |
JP6452270B2 (ja) * | 2012-04-19 | 2019-01-16 | キヤノン株式会社 | プリント回路板および電子機器 |
US9642259B2 (en) | 2013-10-30 | 2017-05-02 | Qualcomm Incorporated | Embedded bridge structure in a substrate |
JP6211392B2 (ja) * | 2013-10-31 | 2017-10-11 | Ngkエレクトロデバイス株式会社 | 光モジュール |
JP6102770B2 (ja) | 2014-01-28 | 2017-03-29 | 株式会社村田製作所 | 高周波モジュール |
JP6332680B2 (ja) * | 2014-06-13 | 2018-05-30 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
KR20160055460A (ko) * | 2014-11-10 | 2016-05-18 | 삼성전기주식회사 | 배선 기판 |
US9907156B1 (en) | 2015-03-06 | 2018-02-27 | Juniper Networks, Inc. | Cross-talk reduction for high speed signaling at ball grid array region and connector region |
US10455691B1 (en) * | 2017-03-28 | 2019-10-22 | Juniper Networks, Inc. | Grid array pattern for crosstalk reduction |
Family Cites Families (15)
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JPH0430452A (ja) * | 1990-05-25 | 1992-02-03 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
JP2605489B2 (ja) | 1991-02-07 | 1997-04-30 | 日本電気株式会社 | 印刷配線板 |
US5898217A (en) * | 1998-01-05 | 1999-04-27 | Motorola, Inc. | Semiconductor device including a substrate having clustered interconnects |
US6008534A (en) * | 1998-01-14 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines |
US6198635B1 (en) * | 1999-05-18 | 2001-03-06 | Vsli Technology, Inc. | Interconnect layout pattern for integrated circuit packages and the like |
JP2000349403A (ja) * | 1999-06-02 | 2000-12-15 | Matsushita Electric Ind Co Ltd | 回路基板及び配線設計支援装置 |
JP2001053507A (ja) | 1999-08-13 | 2001-02-23 | Nec Corp | 配線基板とその製造方法 |
JP2001251061A (ja) * | 2000-03-02 | 2001-09-14 | Sony Corp | 多層型プリント配線基板 |
JP2002057467A (ja) | 2000-08-11 | 2002-02-22 | Kenwood Corp | 多層配線基板 |
KR100491179B1 (ko) * | 2001-11-21 | 2005-05-24 | 마츠시타 덴끼 산교 가부시키가이샤 | 박형 회로기판 및 박형 회로기판의 제조방법 |
US6762367B2 (en) * | 2002-09-17 | 2004-07-13 | International Business Machines Corporation | Electronic package having high density signal wires with low resistance |
KR100499146B1 (ko) * | 2003-06-24 | 2005-07-04 | 삼성전자주식회사 | 곡면 미러를 구비한 광스캐너 및 그 제조방법 |
JP2006086825A (ja) * | 2004-09-16 | 2006-03-30 | Seiko Epson Corp | 多層配線基板,及び、信号安定化方法 |
TWI246384B (en) * | 2004-11-22 | 2005-12-21 | Benq Corp | Multi-layer printed circuit board layout and manufacturing method thereof |
US7404250B2 (en) * | 2005-12-02 | 2008-07-29 | Cisco Technology, Inc. | Method for fabricating a printed circuit board having a coaxial via |
-
2007
- 2007-03-27 JP JP2007083092A patent/JP4978269B2/ja not_active Expired - Fee Related
-
2008
- 2008-03-26 US US12/078,019 patent/US8072774B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10764991B2 (en) | 2018-08-09 | 2020-09-01 | Samsung Electronics Co., Ltd. | Printed circuit board including overvoltage controlling element and electronic device including the same |
US11122675B2 (en) | 2018-08-09 | 2021-09-14 | Samsung Electronics Co., Ltd. | Printed circuit board including overvoltage controlling element and electronic device including the same |
Also Published As
Publication number | Publication date |
---|---|
US20080238585A1 (en) | 2008-10-02 |
US8072774B2 (en) | 2011-12-06 |
JP2008244179A (ja) | 2008-10-09 |
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