WO2022037147A1 - 扇出型封装结构及其制造方法 - Google Patents

扇出型封装结构及其制造方法 Download PDF

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Publication number
WO2022037147A1
WO2022037147A1 PCT/CN2021/094564 CN2021094564W WO2022037147A1 WO 2022037147 A1 WO2022037147 A1 WO 2022037147A1 CN 2021094564 W CN2021094564 W CN 2021094564W WO 2022037147 A1 WO2022037147 A1 WO 2022037147A1
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WIPO (PCT)
Prior art keywords
layer
metal
fan
package structure
shielding layer
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PCT/CN2021/094564
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English (en)
French (fr)
Inventor
林耀剑
杨丹凤
刘硕
周莎莎
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江苏长电科技股份有限公司
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Priority to US18/018,266 priority Critical patent/US20230282599A1/en
Publication of WO2022037147A1 publication Critical patent/WO2022037147A1/zh

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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Definitions

  • the invention relates to the technical field of packaging, in particular to a fan-out packaging structure and a manufacturing method thereof.
  • the purpose of the present invention is to provide a fan-out package structure and a manufacturing method thereof.
  • the present invention provides a fan-out package structure, comprising a redistribution layer and at least one chip or chip package body arranged on a first surface of the redistribution layer, wherein the redistribution layer includes a grounding circuit layer;
  • the fan-out package structure further includes at least one plastic encapsulation layer, at least one first shielding layer and at least one electrical connecting piece, the electrical connecting piece is arranged on the first surface of the redistribution layer and is located on the chip or the tape. the outside of the chip package body, and is electrically connected to the grounding circuit layer;
  • the plastic encapsulation layer is at least disposed on the first surface of the redistribution layer, and encapsulates the electrical connector and the chip or package body with a chip;
  • the first shielding layer at least partially covers the side surface of the plastic sealing layer
  • the electrical connector is at least partially exposed on the side surface of the plastic encapsulation layer, and is electrically connected to the first shielding layer, and the electrical connector is electrically connected between the first shielding layer and the grounding circuit layer. on.
  • the redistribution layer includes a patterned metal circuit layer and a patterned dielectric layer, and at least part of the metal circuit layer forms a ground circuit layer.
  • the thickness of the metal circuit layer is less than 10 ⁇ m, and the minimum line spacing is less than 15 ⁇ m.
  • a second surface opposite to the first surface of the redistribution layer is provided with a first electrical contact block, and the first electrical contact block is electrically connected to the metal circuit layer.
  • the material of the dielectric layer includes one of organic polymer resin, organic polymer resin with inorganic filler, organic polymer resin with glass fiber cloth and filler sheet, and polyimide or a combination of more than one
  • the material of the metal circuit layer includes a combination of one or more of copper, titanium, and titanium-tungsten.
  • the electrical connector includes a main body, and the material of the main body is an organic polymer resin with inorganic fillers, or an organic polymer resin with glass fiber cloth and filler sheets.
  • a side of the main body facing the side wall of the first shielding layer adjacent to it is provided with a first through hole penetrating through the upper and lower surfaces thereof.
  • the first through hole is filled with conductive filler
  • the bottom of the main body is covered by the conductive filler, and is electrically connected to the grounding circuit layer, and the side of the conductive filler is exposed to the
  • the plastic sealing layer is electrically connected to the first shielding layer.
  • the conductive filler is conductive paste including silver and/or copper, or metal solder.
  • a first metal layer is provided at one or more places on the upper surface, the lower surface of the main body and the side wall surface of the first through hole.
  • the upper and lower surfaces of the main body are provided with a second metal layer, and the second metal layer is exposed on the side surface of the plastic sealing layer and is electrically connected to the first shielding layer.
  • the main body is provided with a second through hole, the second through hole communicates with the upper and lower surfaces of the main body, and the second through hole is filled with metal or the inner wall surface is covered with metal, The second metal layer on the upper and lower surfaces of the main body is electrically connected.
  • the main body is provided with a second electrical contact block on the second metal layer located on the lower surface thereof, and the second electrical contact block is electrically connected to the ground circuit layer.
  • the material of the electrical connector is a conductive material.
  • the electrical connectors are copper bumps plated on the grounding circuit layer, or metal bumps or part of tin bonded on the grounding circuit layer.
  • the electrical connector is a part of metal bonding wire, one end of which is electrically connected to the grounding circuit layer through solder balls, and the other end is exposed on the side of the plastic encapsulation layer, and is connected to the first shielding layer. connected.
  • a second shielding layer is further provided between the first shielding layer and the plastic sealing layer, and the second shielding layer is a single-layer shielding layer or a multi-layer composite shielding layer.
  • the shielding layer has a different shielding coefficient from the first shielding layer at least in a part of the frequency range.
  • the second shielding layer is provided with a plurality of shielding layer grooves or shielding layer through holes, and the first shielding layer is filled in the shielding layer grooves or the shielding layer through holes , or the first shielding layer is plated on the inner wall surface of the shielding layer groove or the shielding layer through hole.
  • the electrical connectors are located on four corners and/or four sides of the redistribution layer, and are basically symmetrically distributed around the center of the redistribution layer.
  • the present invention also provides a method for manufacturing a fan-out package structure, comprising the steps of:
  • a carrier board is provided, a patterned metal circuit layer and a dielectric layer are fabricated on the carrier board, a redistribution layer is formed by stacking, and a ground circuit is formed by at least part of the metal circuit layer close to or covering or spanning at least part of the scribe line Floor;
  • an electrical connector is arranged on the first surface of the redistribution layer, and covers or spans at least part of the scribe line, and is electrically connected to the ground circuit layer;
  • a first shielding layer is formed outside the plastic sealing layer of the single package structure, and the first shielding layer covers at least the side surface of the plastic sealing layer.
  • the thickness of the metal circuit layer is less than 10 ⁇ m, and the minimum line spacing is less than 15 ⁇ m.
  • the material of the dielectric layer includes one of organic polymer resin, organic polymer resin with inorganic filler, organic polymer resin with glass fiber cloth and filler sheet, polyimide or Various combinations, the material of the metal circuit layer includes one or more combinations of copper, titanium, and titanium-tungsten.
  • arranging the electrical connector on the first surface of the redistribution layer specifically includes:
  • First through holes penetrating the upper and lower surfaces of the main body are made, conductive fillers are filled in the first through holes, and the conductive fillers are coated on the bottom surface of the main body, and the conductive fillers are electrically connected to the main body.
  • the ground circuit layer, the first through hole covers or spans at least part of the scribe line.
  • the material of the main body is organic polymer resin with inorganic filler, or organic polymer resin with glass fiber cloth and filler
  • the conductive filler is conductive adhesive including silver and/or copper, or metal solder.
  • a metal layer is formed at one or more places on the upper surface, the lower surface of the main body and the side wall surface of the first through hole.
  • arranging the electrical connector on the first surface of the redistribution layer specifically includes:
  • a second through hole penetrating the upper and lower surfaces of the main body is fabricated, metal is plated in the second through hole, and a second metal layer is provided on the upper and lower surfaces of the main body, and the second metal layer covers or spans at least a partial cut;
  • a second electrical contact block is formed on the second metal layer on the lower surface of the main body, and the electrical contact piece is bonded to the ground circuit layer through the second electrical contact block.
  • arranging the electrical connector on the first surface of the redistribution layer specifically includes:
  • "arranging the electrical connector on the first surface of the redistribution layer” specifically includes: connecting the ground circuit layers on both sides of the scribe line through metal wire bonding.
  • the first shielding layer before making the first shielding layer, it also includes steps:
  • the second shielding layer has a different shielding coefficient from the first shielding layer at least in a part of the frequency range.
  • the beneficial effect of the present invention is that the first shielding layer is connected to the grounding line layer through the electrical connecting piece, so that the electrical connecting piece can be used to connect with the first shielding layer and the grounding line layer respectively. Realize a relatively large area of surface contact, thereby reducing the resistance between the three, to improve the shielding effect of the first shielding layer, so as to avoid connecting the first shielding layer directly with the thin metal circuit layer on the side. Higher resistance occurs.
  • the electrical connector in the present invention adopts conventional low-cost materials, and the manufacturing process is simple and easy to realize, and is suitable for large-scale industrialized manufacturing process.
  • the cooperation of the first shielding layer and the second shielding layer can effectively shield electromagnetic waves in different frequency ranges.
  • FIG. 1 is a schematic diagram of a fan-out package structure in Embodiment 1 of the present invention.
  • FIG. 5 is an enlarged schematic view of the electrical connector in FIG. 1 .
  • FIG. 6 is a top view of the main body in the first embodiment of the present invention.
  • FIG. 7 , FIG. 9 , and FIG. 11 are schematic diagrams of another implementation manner of the fan-out package structure in the first embodiment of the present invention, respectively.
  • FIG. 8 , FIG. 10 , and FIG. 12 are enlarged schematic diagrams of the electrical connectors in FIGS. 7 , 9 and 11 , respectively.
  • FIG. 13 is a schematic diagram of a fan-out package structure in Embodiment 2 of the present invention.
  • FIG. 14 is an enlarged schematic view of the electrical connector in FIG. 13 .
  • FIG. 15 , FIG. 16 , FIG. 17 , and FIG. 18 are schematic diagrams of fan-out package structures in Embodiment 3, Embodiment 4, Embodiment 5, and Embodiment 6 of the present invention, respectively.
  • FIG. 19 is a schematic flowchart of a method for manufacturing a fan-out package structure provided by the present invention.
  • 20 to 27 are schematic diagrams of each step of a method for manufacturing a fan-out package structure provided by the present invention.
  • 28 to 35 are schematic diagrams illustrating steps of variously arranging electrical connectors in a method for manufacturing a fan-out package structure provided by the present invention.
  • the term used to describe the relative position in space such as “upper”, “lower”, “rear”, “front”, etc., is used to describe one unit or feature shown in the drawings relative to another A unit or feature relationship.
  • the term spatially relative position may include different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as “below” or “above” other elements or features would then be oriented “below” or “above” the other elements or features.
  • the exemplary term “below” can encompass both a spatial orientation of below and above.
  • the present invention provides a fan-out package structure including a redistribution layer 1 , at least one chip 2 , a plastic sealing layer 4 , a first shielding layer 51 and at least one electrical connector 3.
  • the chip 2 may be a package with a chip.
  • the redistribution layer 1 includes a patterned metal circuit layer 11 and a patterned dielectric layer 12.
  • the metal circuit layer 11 and the dielectric layer 12 are alternately stacked to form the redistribution layer 1.
  • the metal circuit The layer 11 at least partially forms the ground wiring layer 111 .
  • the metal circuit layer 11 and the dielectric layer 12 may be a single layer or multiple layers.
  • the thickness of the metal circuit layer 11 is less than 10 ⁇ m, and the minimum line spacing is less than 15 ⁇ m.
  • the redistribution layer 1 under this size condition can meet the wiring requirements of high density and high integration.
  • a second surface opposite to the first surface of the redistribution layer 1 is provided with a plurality of first electrical contact blocks 13 , and the first electrical contact blocks 13 are electrically connected to the metal circuit layer 11 .
  • the first electrical contact block 13 can be a solder ball with a metal layer 33 under the ball or a composite structure with a tin cap, such as a copper-nickel-tin-silver structure, etc., as long as it is an interconnection structure that can be electrically connected to the outside world. That's it.
  • the material of the dielectric layer 12 includes one or more combinations of organic polymer resin, organic polymer resin with inorganic filler, polymer resin with glass fiber cloth and organic filler sheet, and polyimide,
  • the material of the metal circuit layer 11 includes one or a combination of copper, titanium, and titanium-tungsten.
  • the chip 2 is arranged on the first surface of the redistribution layer 1 and is electrically connected to the metal circuit layer 11 .
  • the metal circuit layer 11 provides the connection between the multiple chips 2 . electrical interconnection.
  • other passive components such as capacitors, resistors, etc., or other functional devices such as heat sinks, reinforcing ribs, etc., may also be disposed on the redistribution layer 1 .
  • underfill 21 is further provided between the chip 2 , the package with chip, passive components, functional devices and the redistribution layer.
  • the metal circuit layer 11 includes a part of the ground circuit layer 111 , and the ground circuit layer 111 is disposed outside the metal circuit layer 11 connected to the chip 2 or passive components.
  • the electrical connector 3 is disposed on the first surface of the redistribution layer 1 , outside the chip 2 , and is electrically connected to the ground circuit layer 111 .
  • the plastic encapsulation layer 4 is disposed on the first surface of the redistribution layer 1 to encapsulate the electrical connector 3 and the chip 2 .
  • the plastic sealing layer 4 is filled with plastic sealing material, and the plastic sealing material can be epoxy resin, polyimide, dry film and other polymer composite materials with fillers.
  • the plastic sealing layer 4 provides physical support for the packaging structure. And protect the chip 2, the electrical connector 3, the passive components and the like.
  • the plastic sealing layer 4 covers the side surface and the upper surface of the chip 2 and fills the area between the chip 2 and the redistribution layer 1 .
  • the plastic encapsulation layer 4 covers most of the surface of the electrical connector 3, at least a part of the electrical connector 3 is exposed on the side of the plastic encapsulation layer 4, and the exposed part has conductivity, and is A conductive path is formed in the electrical connection member 3 from the end of the electrical connection member 3 connected to the ground circuit layer 111 to the end exposed to the plastic sealing layer 4 .
  • the first shielding layer 51 at least partially covers the side surface of the plastic sealing layer 4 .
  • the first shielding layer 51 covers the measuring surface and the upper surface of the plastic encapsulation layer 4 , and substantially covers the plastic encapsulation layer 4 by forming a multi-faceted coating on the encapsulation structure. All surfaces of the chip 2 or other passive components encapsulated therein provide protection against electromagnetic interference, and the fully covered structure can further enhance the shielding effect of the first shielding layer 51 .
  • the first shielding layer 51 can be sputtered sandwich metal thin film materials such as copper, stainless steel, titanium, etc., such as stainless steel/copper/stainless steel, titanium/copper/titanium, etc., or high-density metals such as silver/copper
  • the conductive composite material such as the conductive resin of the filler can also be a combination of at least two of the above-mentioned materials, which can play the role of shielding or absorbing electromagnetic waves.
  • a second shielding layer 52 is further provided between the first shielding layer 51 and the plastic sealing layer 4 , and the second shielding layer 52 is a single-layer shielding layer or a multi-layer composite layer.
  • a shielding layer, the second shielding layer 52 has a different shielding coefficient from the first shielding layer 51 in at least a part of the frequency range, so that it can cooperate to shield electromagnetic waves in a wider frequency range.
  • the second shielding layer 52 is provided with a plurality of shielding layer grooves or shielding layer through holes 53 , and the first shielding layer 51 is filled in the shielding layer grooves or the shielding layer through holes 53 , or the first shielding layer 51 is plated on the inner wall surface of the shielding layer groove or the shielding layer through hole 53 . Therefore, the electrical contact area between the first shielding layer 51 and the second shielding layer 52 can be increased, and the electrical conductivity between the two can be improved. The shielding performance of the second shielding layer causes obvious damage.
  • the electrical connector 3 is electrically connected to the first shielding layer 51 at the exposed end of the plastic encapsulation layer 4 , and the electrical connector 3 passes between the first shielding layer 51 and the grounding circuit layer 111 . It is electrically conductive, so that the first shielding layer 51 is electrically connected to an external low-impedance grounding point through the electrical connecting member 3 and the grounding circuit layer 111 .
  • the upper end surface of the electrical connector 3 is lower than the upper end surface of the chip 2 .
  • the distance between the upper end surface of the electrical connector 3 and the upper end surface of the chip 2 is greater than or equal to 15 ⁇ m.
  • the first shielding layer 51 is connected to the grounding circuit layer 111 through the electrical connector 3 , thereby
  • the electrical connector 3 can be used to achieve relatively large-area surface contact with the first shielding layer 51 and the grounding circuit layer 111 respectively, thereby reducing the resistance between the three and improving the resistance of the first shielding layer 51 .
  • the shielding effect is to avoid the occurrence of higher resistance by connecting the first shielding layer 51 directly with the thin metal circuit layer 11 on the side.
  • the electrical connectors 3 are located at multiple locations on the four corners and/or four sides of the redistribution layer 1 , and are connected with
  • the center of the redistribution layer 1 is basically symmetrically distributed, and since the material of the electrical connector 3 has a large thermal expansion coefficient, it can restrain warpage to a certain extent.
  • the distribution positions and sizes of the electrical connectors 3 can be adjusted correspondingly according to the size, structure and distribution of the components on the heavy line layer 1 .
  • the electrical connector 3 has various embodiments, which will be described in detail below with reference to the various embodiments.
  • the electrical connection member 3 includes a main body member 31 , and the main body member 31 is provided with a side wall facing the side wall of the first shielding layer 51 adjacent thereto. Through holes 311 penetrating through its upper and lower surfaces.
  • the material of the main body 31 is organic polymer resin with inorganic filler, or organic polymer resin with glass fiber cloth and filler, synthetic resin and other polymer materials, or other low-cost, structural strength such as silicon and ceramics. base material for the structural support of the electrical connector 3 .
  • the first through holes 311 are filled with conductive fillers 32 , and the side surfaces of the conductive fillers 32 are exposed and electrically connected to the first shielding layer 51 .
  • the bottom of the main body 31 is covered by the conductive filler 32 , and is electrically connected to the grounding circuit layer 111 through the conductive filler 32 , so that the first shielding layer 51 and the The ground circuit layer 111 is electrically connected.
  • the conductive filler 32 is a conductive filler such as silver and/or copper conductive paste, or metal solder.
  • a first metal layer 33 is optionally provided on one or more of the upper surface, the lower surface of the main body 31 and the sidewall surface of the first through hole 311 , and the first metal layer 33 may be copper , silver, tin, nickel and other suitable conductive materials formed by one or more composite layers.
  • the upper surface, the lower surface of the main body 31 and the side wall surface of the through hole 311 are all provided with a metal layer 33 .
  • the conductive filler 32 fills the first through hole 311 and partially covers the first metal layer 33 covered on the upper surface of the main body 31 .
  • the electrical connection member can be strengthened. 3 electrical conductivity properties.
  • the conductive filler 32 may also be partially filled in the first through hole 311 , as long as the side surface is connected to the first shielding layer 51 . , the bottom surface can be connected to the ground circuit layer 111 .
  • the sidewalls of the first through holes 311 are plated with a first metal layer 33 , and the conductive fillers 32 are all filled in the first through holes 311 . inside the through hole 311 .
  • the inner wall surface of the first through hole 311 and the upper and lower surfaces of the electrical connector 3 and its adjacent parts are all plated with a metal layer 33
  • a green oil material layer 34 is provided on the surface of the main body member 31 that does not cover the first metal layer 33 and on a part of the surface of the first metal layer 33 , so as to protect the electrical connection member 3 .
  • the electrical connection member 3 is connected to the first shielding layer 51 through the metal layer 33 , and is connected to the grounding circuit layer 111 through conductive glue on the bottom surface of the main body member 31 .
  • the upper and lower surfaces of the main body 31 are provided with a second metal layer 35 .
  • the first shielding layer 51 is electrically connected.
  • the main body is provided with a second through hole 312, the second through hole 312 is connected to the upper and lower surfaces of the main body 31, the second through hole 312 is filled with metal or the inner wall is covered with metal, and is electrically connected The second metal layer 35 on the upper and lower surfaces of the main body 31 .
  • the main body 31 is provided with a second electrical contact block 36 on the second metal layer 35 located on the lower surface thereof, and the second electrical contact block 36 is electrically connected to the ground circuit layer 111 .
  • the upper and lower surfaces of the main body 31 are not covered with the second metal layer 35 and some surfaces of the second metal layer 35 are provided with a green oil material layer 34 to protect the electrical connector 3 .
  • the main material of the electrical connector 3 is a conductive material.
  • the electrical connector 3 is a combined structure of one or more of metal bumps, some solder balls, and some copper core balls 61 bonded on the ground circuit layer.
  • the complete solder balls or the copper core balls 61 are welded on the ground circuit layer 111 and covered with the dicing lanes. After the dicing process, they are placed on the The shape of the electrical connector 3 in a single package structure is generally half of the solder ball or half of the copper core ball 61 .
  • the cut surface of the combined structure of one or more of the metal bumps, part of the solder balls, and part of the copper core balls 61 is connected to the first shielding layer 51 , and the bottom surface is connected to the ground circuit layer 111 by welding.
  • the main material of the electrical connector 3 is a conductive material.
  • the electrical connector 3 is a copper bump 62 plated on the ground circuit layer, and the copper bump 62 can be cylindrical, square, rectangular, oval or racetrack-shaped.
  • the main material of the electrical connector 3 is a conductive material.
  • the electrical connector 3 is a part of the metal bonding wire 7 , one end of the bonding wire is electrically connected to the ground circuit layer 111 , and the other end is exposed to the side of the plastic encapsulation layer 4 , and is connected to the first shielding layer 51 . connected.
  • both ends of the metal bonding wire 7 are respectively bonded to the grounding circuit layers 111 on both sides of the dicing road, after the dicing process, the electrical connectors 3 provided in the single package structure are formed.
  • the shape is generally the structure of a half of the metal bonding wire 7 cut from the middle, and the cut surface of the metal bonding wire 7 is connected to the first shielding layer 51 .
  • the electrical connector 3 is a cured metal paste 8 .
  • the solidified metal paste 8 may be, for example, sintered silver or sintered copper or a silver-copper alloy or the like.
  • the present invention also provides a method for manufacturing a fan-out package structure, comprising the steps of:
  • a carrier board 9 As shown in FIG. 20, a carrier board 9 is provided, patterned metal circuit layer 11 and dielectric layer 12 are fabricated on the carrier board 9, and the redistribution layer 1 is formed by stacking.
  • the metal wiring layer 11 forms the ground wiring layer 111 .
  • the carrier plate 9 is a low-cost sacrificial substrate with a certain rigidity such as glass, silicon, composite polymer, etc., for structural support.
  • the thickness of the metal circuit layer 11 is less than 10 ⁇ m, and the minimum line spacing is less than 15 ⁇ m.
  • the material of the dielectric layer 12 includes photosensitive or non-photosensitive organic polymer resin, organic polymer resin with inorganic filler, organic polymer resin with glass fiber cloth and filler sheet, and one or more of polyimide.
  • the material of the metal circuit layer 11 includes a combination of one or more of copper, titanium, and titanium-tungsten.
  • the chip 2 is disposed on the first surface of the redistribution layer 1 and is electrically connected to the metal circuit layer 11 .
  • other passive components such as capacitors and resistors, or other functional devices such as heat sinks, reinforcing ribs, etc., may also be arranged on the redistribution layer 1 .
  • underfill material can also be filled between the chip 2 or other components and the redistribution layer 1 to protect and strengthen the connection.
  • the electrical connector 3 is arranged on the first surface of the redistribution layer 1 , and covers or covers or spans at least part of the scribe line, and is electrically connected to the ground circuit layer 111 .
  • the electrical connectors 3 are located at multiple locations on the four corners and/or four sides of the redistribution layer 1 , and the center of the redistribution layer 1 is located in the center of the redistribution layer 1 .
  • the distribution positions and sizes of the electrical connectors 3 can be adjusted correspondingly according to the size, structure and distribution of the components on the heavy line layer 1 .
  • organic polymer resins such as inorganic fillers, or organic polymer resins with glass fiber cloth and fillers, or epoxy resin, polyimide (PI), dry film and other filler polymer composites as molding compounds It is deposited on the first surface of the redistribution layer 1 to encapsulate the electrical connector 3 and the chip 2 .
  • step S41 is further included:
  • One or more shielding layers are formed on the plastic sealing layer 4 to form a second shielding layer 52 , and a plurality of shielding layer grooves or shielding layer through holes 53 are formed on the second shielding layer.
  • Step S41 can also be performed after step S5, as long as it is performed before the first shielding layer 51 is fabricated.
  • the carrier board 9 is peeled off by means of laser debonding separation, mechanical peeling, chemical etching, mechanical grinding, etc., to expose the active interface of the metal circuit layer 11 on the second surface of the redistribution layer 1, and the required and implanting solder balls such as under-ball metal layers 33 or photolithography to form composite metal structures with tin caps such as copper bumps as the first electrical contact pads 13 .
  • a second redistribution stack layer is formed between the first electrical contact block 13 and the previous redistribution layer 1,
  • the complete package structure is divided into individual package structures along the dicing lines by a saw blade or a laser cutting device.
  • a first shielding layer 51 is formed on the outer side of the plastic sealing layer 4 of the single package structure, and the first shielding layer 51 covers at least the side surface of the plastic sealing layer 4.
  • the first shielding layer 51 is formed on the plastic sealing layer 4 through metal deposition processes such as electroplating, sputtering, PVD, CVD, etc., ultrasonic spraying, vacuum film lamination and other deposition conductive composite layer processes.
  • the first shielding layer 51 can be sputtered sandwich metal film materials such as copper, stainless steel, titanium, etc., such as stainless steel/copper/stainless steel, titanium/copper/titanium, etc., or high-density metal fillers such as silver/copper
  • the conductive composite materials such as conductive resin can also be a combination of at least two of the above materials, which can play the role of shielding or absorbing electromagnetic waves.
  • the material of the first shielding layer 51 is filled or plated on the shielding layer groove or the shielding layer through hole 53
  • step S7 may also be performed before step S6.
  • S2a1 As shown in FIG. 28 and FIG. 29 , make through holes 311 on the main body 31 penetrating the upper and lower surfaces thereof, fill the first through holes 311 with conductive fillers 32 , and coat the bottom surface of the main body 31
  • the conductive filler 32 is electrically connected to the ground circuit layer 111 through the conductive filler 32, and the conductive filler 32 covers or spans at least part of the dicing road.
  • the material of the main body 31 is a polymer material such as synthetic resin, or other low-cost basic materials such as silicon and ceramics with a certain structural strength, so as to be used for the structural support of the electrical connector 3 .
  • the first through holes 311 are formed on the main body 31 by means of laser drilling, mechanical drilling or deep reactive ion etching.
  • one or more of the upper surface, the lower surface of the main body member 31 and the sidewall surface of the first through hole 311 are electroplating, sputtering, PVD, CVD, filling and pressing.
  • a metal layer 33 is formed by a metal deposition process such as copper, silver, tin, nickel, and other suitable conductive materials.
  • the first metal layer 33 can be a composite layer formed of one or more materials.
  • a green oil material layer 34 is provided on the surface of the main body 31 not covering the first metal layer 33 .
  • the first through hole 311 is filled with a conductive filler 32, and the conductive filler 32 is a conductive filler such as conductive glue or metal solder.
  • the conductive filler 32 can fill the first through hole 311 and partially cover the first metal layer 33 covered on the upper surface of the main body 31 .
  • the conductive filler 32 can also be partially filled in the first through hole 311 .
  • the bottom of the main body 31 is covered by the conductive filler 32 , and is electrically connected to the ground circuit layer 111 through the conductive filler 32 .
  • a second through hole 312 penetrating the upper and lower surfaces of the main body member 31 is formed.
  • the second through hole 312 is filled with metal or the inner wall is covered with metal.
  • the upper and lower surfaces of 31 are plated with a second metal layer 35;
  • a second electrical contact block 36 is provided on the second metal layer 35 on the lower surface of the main body 31;
  • the electrical connector 3 is bonded to the grounding circuit layer 111 through the second electrical contact block 36 , and the second metal layer 35 covers or spans the scribe line.
  • S2c1 As shown in FIG. 32 , electrically connect the combined structure of one or more of metal bumps, solder balls, and copper core balls 61 to the ground circuit layer 111 and cover the dicing lines.
  • the first shielding layer is connected to the grounding line layer through the electrical connecting piece, so that the electrical connecting piece can be used to connect with the first shielding layer and the grounding line layer respectively.
  • the electrical connecting piece can be used to connect with the first shielding layer and the grounding line layer respectively.

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Abstract

本发明提供一种扇出型封装结构及其制造方法，封装结构包括重布线层、至少一塑封层、至少一第一屏蔽层、至少一个芯片和至少一个电连接件，重布线层包括接地线路层，芯片和电连接件设于重布线层第一面，并与其电连接；塑封层包封电连接件和芯片；第一屏蔽层至少覆于塑封层侧面；电连接件至少有部分暴露于塑封层侧面，并电连接至第一屏蔽层。电连接件分别与第一屏蔽层和接地线路层实现大面积的面接触，降低三者间电阻，提高屏蔽效果。

Description

扇出型封装结构及其制造方法 技术领域
本发明涉及封装技术领域，具体地涉及一种扇出型封装结构及其制造方法。
背景技术
随着集成电路进一步向着高密度、高集成度发展，芯片及电子器件的封装结构也向更高密度的方向发展。扇出晶圆级封装及板级封装技术由于具有小型化、低成本和高集成度等优点，以及具有更好的性能和更高的能源效率已成为高要求的移动/无线网络等电子设备的重要的封装方法，是目前最具发展前景的封装技术之一。
同时，重数字化和高频化的电子元器件在工作时向空间辐射了大量不同频率和波长的电磁波，严重的电磁辐射会干扰电子元器件性能的实现，在通讯及消费类电子方面对电磁屏蔽器件的需求持续增长，同时也对电磁屏蔽要求越来越高。
然而，相较于传统的基板，在晶圆级或者板级的扇出型封装中，特别是高密度的重布线层较薄，在封装体侧面和背面沉积电磁屏蔽薄膜层时，导电层与线路层的接触面积小，电阻会较高，从而影响屏蔽效果。
发明内容
本发明的目的在于提供一种扇出型封装结构及其制造方法。
本发明提供一种扇出型封装结构，包括重布线层和设于其第一面上的至少一个芯片或带芯片封装体，所述重布线层包括接地线路层；
所述扇出型封装结构还包括至少一塑封层、至少一第一屏蔽层和至少一个电连接件，所述电连接件设于所述重布线层第一面上，位于所述芯片或带芯片封装体外侧，并电性连接至所述接地线路层；
所述塑封层至少设于所述重布线层第一面之上，包封所述电连接件和所述芯片或带芯片封装体；
所述第一屏蔽层至少有部分覆盖于所述塑封层的侧表面；
所述电连接件至少有部分暴露于所述塑封层侧面，并电性连接至所述第一屏蔽层，所述第一屏蔽层和所述接地线路层之间通过所述电连接件电性导通。
作为本发明的进一步改进，所述重布线层包括图形化的金属线路层和图形化的介电层， 所述金属线路层至少有部分形成接地线路层。
作为本发明的进一步改进，所述金属线路层厚度小于10μm，最小线距小于15μm。
作为本发明的进一步改进，相对于所述重布线层第一面的第二面上设有第一电接触块，所述第一电接触块电连接至所述金属线路层。
作为本发明的进一步改进，所述介电层的材料包括有机高分子树脂、带无机填料的有机高分子树脂、带玻纤布与填料片的有机高分子树脂、聚酰亚胺中的一种或多种的组合，所述金属线路层的材料包括铜、钛、钛钨中的一种或多种的组合。
作为本发明的进一步改进，所述电连接件包括主体件，所述主体件的材料为带无机填料的有机高分子树脂、或带玻纤布与填料片的有机高分子树脂。
作为本发明的进一步改进，所述主体件朝向与其相邻的所述第一屏蔽层侧壁的一侧设有贯通其上下表面的第一通孔。
作为本发明的进一步改进，所述第一通孔内填充有导电填料，所述主体件底部被所述导电填料包覆，电性连接于所述接地线路层，所述导电填料侧面露出所述塑封层与所述第一屏蔽层电性连接。
作为本发明的进一步改进，所述导电填料为包括银和/或铜的导电胶、或金属焊料。
作为本发明的进一步改进，所述主体件的上表面、下表面和所述第一通孔的侧壁面中的一处或多处设有第一金属层。
作为本发明的进一步改进，所述主体件上下表面设有第二金属层，所述第二金属层暴露于所述塑封层侧面，与所述第一屏蔽层电性连接。
作为本发明的进一步改进，所述主体件内设有第二通孔，所述第二通孔连通所述主体件上下表面，所述第二通孔内填充有金属或内壁面覆有金属，电性连通所述主体件上下表面的所述第二金属层。
作为本发明的进一步改进，所述主体件于位于其下表面的第二金属层上设有第二电接触块，所述第二电接触块与所述接地线路层电性连接。
作为本发明的进一步改进，所述电连接件的材料为导电材料。
作为本发明的进一步改进，所述电连接件为所述电连接件为电镀在所述接地线路层上的铜凸块，或为键合在所述接地线路层上的金属凸块、部分锡球、部分铜核球中的一种或多种的组合结构，或为烧结固化的金属或合金膏。
作为本发明的进一步改进，所述电连接件为部分金属焊线，其一端通过焊球与所述接地线路层电性连接，另一端暴露于所述塑封层侧面，与所述第一屏蔽层相连。
作为本发明的进一步改进，所述第一屏蔽层与所述塑封层之间还设有第二屏蔽层，所述 第二屏蔽层为单层屏蔽层或多层复合屏蔽层，所述第二屏蔽层至少在一部分频率范围内与所述第一屏蔽层具有相异的屏蔽系数。
作为本发明的进一步改进，所述第二屏蔽层内设有多个屏蔽层凹槽或屏蔽层通孔，所述第一屏蔽层填充于所述屏蔽层凹槽或所述屏蔽层通孔内，或所述第一屏蔽层镀覆于所述屏蔽层凹槽或所述屏蔽层通孔的内壁面上。
作为本发明的进一步改进，所述电连接件位于所述重布线层的四个角上和/或四条边上，且以所述重布线层的中心呈基本对称式分布。
本发明还提供一种扇出型封装结构的制造方法，包括步骤：
提供一载板，在所述载板上制作图形化的金属线路层和介电层，堆叠形成重布线层，将至少部分靠近或覆盖或跨越至少部分切割道的所述金属线路层形成接地线路层；
将芯片、和/或带芯片封装体、和/或被动器件设于所述重布线层第一面，并电性连接至所述金属线路层；
将电连接件设于所述重布线层第一面上，并覆盖或跨越至少部分所述切割道，电连接至所述接地线路层；
将所述芯片和所述电连接件塑封形成塑封层；
去除所述载板，在相对于所述重布线层第一面的第二面上形成第一电接触块；
将完整封装体沿切割道切割形成单个封装结构；
在单个封装结构的所述塑封层外侧形成第一屏蔽层，所述第一屏蔽层至少覆盖所述塑封层侧面。
作为本发明的进一步改进，所述金属线路层厚度小于10μm，最小线距小于15μm。
作为本发明的进一步改进，所述介电层的材料包括有机高分子树脂、带无机填料的有机高分子树脂，带玻纤布与填料片的有机高分子树脂、聚酰亚胺的一种或多种的组合，所述金属线路层的材料包括铜、钛、钛钨中的一种或多种的组合。
作为本发明的进一步改进，“将电连接件设于所述重布线层第一面上”具体包括：
在主体件上制作贯穿其上下表面的第一通孔，在所述第一通孔内填充导电填料，并在所述主体件底面涂覆所述导电填料，将其通过导电填料电连接至所述接地线路层，所述第一通孔覆盖或跨越至少部分切割道。
作为本发明的进一步改进，所述主体件的材料为带无机填料的有机高分子树脂，或带玻纤布与填料有机高分子树脂，所述导电填料为包括银和/或铜的导电胶、或金属焊料。
作为本发明的进一步改进，所述主体件的上表面、下表面和所述第一通孔的侧壁面中的一处或多处形成有金属层。
作为本发明的进一步改进，“将电连接件设于所述重布线层第一面上”具体包括：
在主体件上制作贯穿其上下表面的第二通孔，在所述第二通孔内镀覆金属，并在所述主体件上下表面设置第二金属层，所述第二金属层覆盖或跨越至少部分切割道；
在所述主体件下表面的所述第二金属层上制作第二电接触块，将所述电接触件通过第二电接触块键合于所述接地线路层上。
作为本发明的进一步改进，“将电连接件设于所述重布线层第一面上”具体包括：
将金属凸块、锡球、铜核球中的一种或多种的组合结构键合电连接至所述接地线路层，并覆盖或跨越至少部分切割道；或在所述接地线路层上电镀铜凸块，所述铜凸块覆盖或跨越至少部分切割道；或在所述接地线路层上设置烧结固化的金属或合金膏，并覆盖或跨越至少部分切割道。
作为本发明的进一步改进，“将电连接件设于所述重布线层第一面上”具体包括：将在切割道两侧的所述接地线路层通过金属焊线键合连接。
作为本发明的进一步改进，在制作所述第一屏蔽层之前还包括步骤：
在所述塑封层上制作一层或多层屏蔽层形成第二屏蔽层；
在所述第二屏蔽层上制作多个的屏蔽层凹槽或屏蔽层通孔；
将所述第一屏蔽层材料填充或镀覆于所述屏蔽层凹槽或所述屏蔽层通孔上。
作为本发明的进一步改进，所述第二屏蔽层至少在一部分频率范围内与所述第一屏蔽层具有相异的屏蔽系数。
本发明的有益效果是：通过所述电连接件将所述第一屏蔽层连接至所述接地线路层，从而可利用所述电连接件分别与所述第一屏蔽层和所述接地线路层实现相对大面积的面接触，从而降低三者间的电阻，来提高所述第一屏蔽层的屏蔽效果，以避免将所述第一屏蔽层直接与薄的所述金属线路层在侧面连接而出现较高的电阻。同时，本发明中的电连接件采用常规低成本材料，制程简单，易于实现，适用于大规模工业化制造流程。另外，通过第一屏蔽层和第二屏蔽层相配合可以对不同的频率范围的电磁波进行有效屏蔽。
附图说明
图1是本发明实施例一中的扇出型封装结构的示意图。
图2至图4是本发明中电连接件不同分布位置的示意图
图5是图1中的电连接件的放大示意图。
图6是本发明实施例一中的主体件的俯视图。
图7、图9、图11分别是本发明实施例一中的扇出型封装结构另一实施方式的示意图。
图8、图10、图12分别是图7、图9、图11中的电连接件的放大示意图。
图13是本发明实施例二中的扇出型封装结构的示意图。
图14是图13中的电连接件的放大示意图。
图15、图16、图17、图18分别是本发明实施例三、实施例四、实施例五、施例六中的扇出型封装结构的示意图。
图19是本发明提供的一种扇出型封装结构制造方法的流程示意图。
图20至图27是本发明提供的一种扇出型封装结构制造方法的各步骤示意图。
图28-图35是本发明提供的一种扇出型封装结构制造方法中多种设置电连接件的步骤示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施方式及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施方式仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
下面详细描述本发明的实施方式，实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
为方便说明，本文使用表示空间相对位置的术语来进行描述，例如“上”、“下”、“后”、“前”等，用来描述附图中所示的一个单元或者特征相对于另一个单元或特征的关系。空间相对位置的术语可以包括设备在使用或工作中除了图中所示方位以外的不同方位。例如，如果将图中的装置翻转，则被描述为位于其他单元或特征“下方”或“上方”的单元将位于其他单元或特征“下方”或“上方”。因此，示例性术语“下方”可以囊括下方和上方这两种空间方位。
如图1所示，本发明提供一种扇出型封装结构，所述扇出型封装结构包括重布线层1、至少一个芯片2、塑封层4、第一屏蔽层51和至少一个电连接件3。所述芯片2可以为带芯片封装体。所述重布线层1包括图形化的金属线路层11和图形化的介电层12，所述金属线路层11和所述介电层12交替堆叠形成所述重布线层1，所述金属线路层11至少有部分形成接地线路层111。所述金属线路层11和所述介电层12可以为单层或多层。
具体的，所述金属线路层11厚度小于10μm，最小线距小于15μm，该尺寸条件下的重 布线层1能满足高密度与高集成度的布线要求。
进一步的，相对于所述重布线层1第一面的第二面上设有多个第一电接触块13，所述第一电接触块13电连接至所述金属线路层11。
所述第一电接触块13可以为带球下金属层33的焊球或带锡帽的复合结构，如铜-镍-锡银结构等，只要是能够和外界形成电性连接的互连结构即可。
所述介电层12的材料包括有机高分子树脂、带无机填料的有机高分子树脂、带玻纤布与有机填料片的高分子树脂、聚酰亚胺中的一种或多种的组合，所述金属线路层11的材料包括铜、钛、钛钨中的一种或多种的组合。
所述芯片2设于所述重布线层1第一面上，与所述金属线路层11电性连接，当芯片2至少为两个时，所述金属线路层11提供多芯片2之间的电性互连。
于本发明的另一些实施方式中，所述重布线层1上还可设置其他诸如电容、电阻等其他被动元器件，或者其他诸如散热片、加强筋等功能器件。
在本发明的一些实施方中，所述芯片2、带芯片封装体、被动元器件、功能器件和所述重布线层之间还设有底填料21。
所述金属线路层11包括部分接地线路层111，所述接地线路层111设于与所述芯片2或被动元器件相接的金属线路层11的外侧。
所述电连接件3设于所述重布线层1第一面上，位于所述芯片2外侧，并电性连接至所述接地线路层111。
所述塑封层4设于所述重布线层1第一面之上，包封所述电连接件3和所述芯片2。所述塑封层4由塑封料填充而成，塑封料可以为环氧树脂、聚酰亚胺、干膜等带填料的高分子聚合物复合材料，所述塑封层4为封装结构提供物理支撑，并对所述芯片2、所述电连接件3、所述被动元器件等起到保护作用。
进一步的，于本实施方式中，所述塑封层4覆盖于所述芯片2的侧表面和上表面，并填充于所述芯片2和所述重布线层1之间的区域。
更进一步的，所述塑封层4包覆所述电连接件3大部分表面，所述电连接件3至少有部分暴露于所述塑封层4侧面，其暴露的部分具有导电性，且从所述电连接件3与所述接地线路层111相接的一端至其暴露于所述塑封层4的一端在所述电连接件3内形成导电通路。
所述第一屏蔽层51至少有部分覆盖于所述塑封层4的侧表面。
进一步的，于本实施方式中，所述第一屏蔽层51覆盖于所述塑封层4的测表面和上表面，通过对封装结构件形成多面的包覆，基本上覆盖了所述塑封层4的所有表面，为其内部所封装的芯片2或其他被动元器件提供针对电磁干扰的保护，且全覆盖的结构能进一步加强 所述第一屏蔽层51的屏蔽效果。
所述第一屏蔽层51可以是诸如铜，不锈钢，钛等溅射夹层金属薄膜材料，如不锈钢/铜/不锈钢，钛/铜/钛等，也可以是诸如含银/铜之类高密度金属填料的导电树脂等导电复合材料，也可以是上述材料中至少两种的组合，能够起到屏蔽或吸收电磁波的作用即可。
在本发明的另一些实施方式中，所述第一屏蔽层51与所述塑封层4之间还设有第二屏蔽层52，所述第二屏蔽层52为单层屏蔽层或多层复合屏蔽层，所述第二屏蔽层52至少在一部分频率范围内与所述第一屏蔽51层具有相异的屏蔽系数，从而能够配合以对更广频率范围内的电磁波起到屏蔽作用。
进一步的，所述第二屏蔽层52内设有多个屏蔽层凹槽或屏蔽层通孔53，所述第一屏蔽层51填充于所述屏蔽层凹槽或所述屏蔽层通孔53内，或所述第一屏蔽层51镀覆于所述屏蔽层凹槽或所述屏蔽层通孔53的内壁面上。从而，可增大所述第一屏蔽层51和所述第二屏蔽层52之间的电接触面积，提高两者间的导电能力，同时，凹槽或孔洞的结构也不会对所述第二屏蔽层的屏蔽性能造成明显破坏。
所述电连接件3于所述塑封层4露出的一端电性连接至所述第一屏蔽层51，所述第一屏蔽层51和所述接地线路层111之间通过所述电连接件3电性导通，从而使所述第一屏蔽层51通过所述电连接件3和所述接地线路层111电连接至外部低阻抗接地点。
进一步的，所述电连接件3的上端面低于所述芯片2的上端面。
优选的，所述电连接件3的上端面和所述芯片2的上端面之间的距离大于或等于15μm。
这里，由于所述重布线层1的厚度较薄，且所述金属线路层11厚度小于10μm，通过所述电连接件3将所述第一屏蔽层51连接至所述接地线路层111，从而可利用所述电连接件3分别与所述第一屏蔽层51和所述接地线路层111实现相对大面积的面接触，从而降低三者间的电阻，来提高所述第一屏蔽层51的屏蔽效果，以避免将所述第一屏蔽层51直接与薄的所述金属线路层11在侧面连接而出现较高的电阻。
如图2至图4所示，在本发明的一些实施方式中，所述电连接件3的位于所述重布线层1的四个角上和/或四条边上中的多处，且以所述重布线层1的中心呈基本对称式分布，由于所述电连接件3的材质具有较大热膨胀系数，从而在一定程度上可以起到抑制翘曲的作用。另外，根据所述重部线层1上部件尺寸结构以及分布情况可对应调整所述电连接件3的分布位置及尺寸大小。
在本发明中，所述电连接件3有多种实施方式，下面将结合多个实施例进行具体说明。
如图5至图6所示，在实施例一中，所述电连接件3包括主体件31，所述主体件31朝向与其相邻的所述第一屏蔽层51侧壁的一侧设有贯通其上下表面的通孔311。
所述主体件31的材料为带无机填料的有机高分子树脂，或带玻纤布与填料有机高分子树脂，合成树脂等聚合物材料，或其他诸如硅、陶瓷等低成本、具有一定结构强度的基础材料，以用于对所述电连接件3的结构支撑。
所述第一通孔311内填充有导电填料32，所述导电填料32侧面露出与所述第一屏蔽层51电性连接。
所述主体件31底部被所述导电填料32包覆，通过所述导电填料32电性连接于所述接地线路层111，从而通过所述导电填料32将所述第一屏蔽层51与所述接地线路层111电性连接。
所述导电填料32为银和/或铜的导电胶、或金属焊料等具有导电性的填充料。
所述主体件31的上表面、下表面和所述第一通孔311的侧壁面中的一处或多处可选地设有第一金属层33，所述第一金属层33可以为铜、银、锡、镍等其他合适的导电材料形成的一层或多种材料形成的复合层。
进一步的，在实施例一中，所述主体件31的上表面、下表面和通孔311的侧壁面均设有金属层33。所述导电填料32填充满所述第一通孔311，并部分覆盖于所述主体件31上表面所覆盖的所述第一金属层33，通过设置金属层33，能够加强所述电连接件3的电传导性能。
如图7和图8所示，在实施例一的另一些实施方式中，所述导电填料32也可部分填充于所述第一通孔311，只要实现侧面与所述第一屏蔽层51相连，底面与所述接地线路层111相连即可。
如图9和图10所示，在实施例一的另一些实施方式中，所述第一通孔311的侧壁镀覆第一金属层33，所述导电填料32全部填充于所述第一通孔311内。
如图11和图12所示，在实施例一的另一些实施方式中，所述第一通孔311内壁面及所述电连接件3与其相邻的部分上下表面全部镀覆金属层33，所述主体件31未覆盖所述第一金属层33的表面和部分第一金属层33的表面设有绿油材料层34，以起到对所述电连接件3保护的作用。所述电连接件3通过金属层33与所述第一屏蔽层51相连，在所述主体件31底面通过导电胶与所述接地线路层111相连。
如图13和图14所示，在实施例二式中，所述主体件31上下表面设有第二金属层35，所述第二金属层35暴露于所述塑封层4侧面，并与所述第一屏蔽层51电性连接。
所述主体件内设有第二通孔312，所述第二通孔312连通所述主体件31上下表面，所述第二通孔内312填充有金属或内壁面覆有金属，电性连通所述主体件31上下表面的所述第二金属层35。
所述主体件31于位于其下表面的第二金属层35上设有第二电接触块36，所述第二电接触块36与所述接地线路层111电性连接。
所述主体件31上下表面未覆有所述第二金属层35的表面和部分第二金属层35的表面设有绿油材料层34，以起到对所述电连接件3保护的作用。
如图15所示，在实施例三中，所述电连接件3的主体材料即为导电材料。
具体的，所述电连接件3为键合在所述接地线路层上的金属凸块、部分锡球、部分铜核球61中的一种或多种的组合结构。
可以理解的是，由于在制造过程中，完整的所述锡球或所述铜核球61等焊接在所述接地线路层111上，并覆盖于所述切割道，经过切割工序后，设于单个封装结构内的电连接件3形状大体为半个所述锡球或半个所述铜核球61。
所述金属凸块、部分锡球、部分铜核球61中的一种或多种的组合结构的切割面与所述第一屏蔽层51相连，底面与所述接地线路层111焊接相连。
如图16所示，在实施例四中，所述电连接件3的主体材料即为导电材料。
具体的，所述电连接件3为电镀在所述接地线路层上的铜凸块62，所述铜凸块62可以为圆柱形，方形，长方形，椭圆或跑道型等结构。
如图17所示，在实施例五中，所述电连接件3的主体材料即为导电材料。
具体的，所述电连接件3为部分金属焊线7，其焊线一端与所述接地线路层111电性连接，另一端暴露于所述塑封层4侧面，与所述第一屏蔽层51相连。
可以理解的是，由于在制造过程中，金属焊线7两端分别键合在切割道两侧的所述接地线路层111上，经过切割工序后，设于单个封装结构内的电连接件3形状大体为从中间切开的半个所述金属焊线7结构，金属焊线7的切割面连接于所述第一屏蔽层51。
如图18所示，在实施例六中，所述电连接件3为固化的金属膏8。所述固化的金属膏8可以为如烧结的银或烧结的铜或银铜合金等。
如图19所示，本发明还提供一种扇出型封装结构的制造方法，包括步骤：
S1：如图20所示，提供一载板9，在所述载板9上制作图形化的金属线路层11和介电层12，堆叠形成重布线层1，至少有部分靠近切割道的所述金属线路层11形成接地线路层111。
所述载板9为诸如玻璃，硅，复合聚合物等低成本，具有一定刚性的牺牲基材，以用于结构支撑。
具体的，所述金属线路层11厚度小于10μm，最小线距小于15μm。
所述介电层12的材料包括光敏或非光敏的有机高分子树脂、带无机填料的有机高分子 树脂，带玻纤布与填料片的有机高分子树脂、聚酰亚胺的一种或多种的组合，所述金属线路层11的材料包括铜、钛、钛钨中的一种或多种的组合。
S2：如图21所示，将芯片2设于所述重布线层1第一面，并电性连接至所述金属线路层11。
于本发明的另一些实施方式中，还可在所述重布线层1上设置其他诸如电容、电阻等其他被动元器件，或者其他诸如散热片、加强筋等功能器件。
于本发明的另一些实施方式中，还可在所述芯片2或其他部件与所述重布线层1之间填充底填材料，以起到保护与加强连接的作用。
S3：如图22所示，将电连接件3设于所述重布线层1第一面上，并覆盖于或覆盖或跨越至少部分切割道处，电连接至所述接地线路层111。
在本发明的一些实施方式中，所述电连接件3的位于所述重布线层1的四个角上和/或四条边上中的多处，且以所述重布线层1的中心呈基本对称式分布。另外，根据所述重部线层1上部件尺寸结构以及分布情况可对应调整所述电连接件3的分布位置及尺寸大小。
S4：如图23所示，将所述芯片2和所述电连接件3塑封形成塑封层4。
采用诸如带无机填料的有机高分子树脂，或带玻纤布与填料的有机高分子树脂，或环氧树脂、聚酰亚胺(PI)、干膜等带填料的聚合物复合材料作为塑封料沉积在所述重布线层1第一面之上，包封所述电连接件3和所述芯片2。
于本发明的一些实施方式中，如图24所示，在形成所述塑封层4之后，还包括步骤S41：
在所述塑封层4上制作一层或多层屏蔽层形成第二屏蔽层52，在所述第二屏蔽层上制作多个的屏蔽层凹槽或屏蔽层通孔53。
步骤S41也可在步骤S5之后进行，只要在制作所述第一屏蔽层51之前进行即可。
S5：如图25所示，去除所述载板9，在相对于所述重布线层1第一面的第二面上形成第一电接触块13。
通过激光解键分离，机械剥离、化学蚀刻、机械研磨等方法将所述载板9剥离，暴露所述金属线路层11位于所述重布线层1第二面上的有源界面，以及所需的清洗，并植入诸如带球下金属层33的焊球或光刻电镀形成带锡帽的复合金属结构如铜凸块等作为第一电接触块13。可选的，在分离和清洗之后，第2重布线堆叠层形成于形成第一电接触块13与之前的重布线层1之间，
S6：如图26所示，将完整封装体沿切割道切割形成单个封装结构。
通过锯片或激光切割装置沿切割道将完整的封装结构分成单独的封装结构。
S7：如图27所示，在单个封装结构的所述塑封层4外侧形成第一屏蔽层51，所述第一 屏蔽层51至少覆盖所述塑封层4侧面。
在所述塑封层4上通过电镀，溅射，PVD，CVD等金属沉积工艺，超声喷涂，真空贴膜压合等沉积导电复合层工艺形成所述第一屏蔽层51。所述第一屏蔽层51可以是铜，不锈钢，钛等溅射夹层金属薄膜材料，如不锈钢/铜/不锈钢，钛/铜/钛等，也可以是诸如含银/铜之类高密度金属填料的导电树脂等导电复合材料，也可以是上述材料中至少两种的组合，能够起到屏蔽或吸收电磁波的作用即可。
当存在所述第二屏蔽层52时，所述第一屏蔽层51材料填充或镀覆于所述屏蔽层凹槽或所述屏蔽层通孔53上
于本发明的另一些实施方式中，步骤S7也可在步骤S6之前进行。
在本发明中，“将电连接件3设于所述重布线层1第一面上”具有多种实现方式，下面将就多个制作流程进行具体说明。
流程一：
S2a1：如图28和图29所示，在主体件31上制作贯穿其上下表面的通孔311，在所述第一通孔311内填充导电填料32，并在所述主体件31底面涂覆所述导电填料32，将其通过导电填料32电连接至所述接地线路层111，所述导电填料32覆盖或跨越至少部分切割道。
所述主体件31的材料为合成树脂等聚合物材料，或其他诸如硅、陶瓷等低成本、具有一定结构强度的基础材料，以用于对所述电连接件3的结构支撑。
通过激光打孔，机械打孔或深反应离子蚀刻等方式在所述主体件31上形成所述第一通孔311。
在本发明的一些实施方式中，所述主体件31的上表面、下表面和所述第一通孔311的侧壁面中的一处或多处通过电镀，溅射，PVD，CVD,填压等金属沉积工艺形成有金属层33，所述第一金属层33可以为铜、银、锡、镍等其他合适的导电材料形成的一层或多种材料形成的复合层。
在本发明的一些实施方式中，所述主体件31未覆盖所述第一金属层33的表面设有绿油材料层34。
所述第一通孔311内填充导电填料32，所述导电填料32为导电胶或金属焊料等具有导电性的填充料。所述导电填料32可以填充满所述第一通孔311，并部分覆盖于所述主体件31上表面所覆盖的所述第一金属层33。
于本发明的另一些实施方式中，所述导电填料32也可部分填充于所述第一通孔311。
所述主体件31底部被所述导电填料32包覆，通过所述导电填料32电性连接于所述接地线路层111。
流程二：
S2b1：如图30和图31所示，在主体件31上制作贯穿其上下表面的第二通孔312，所述第二通孔内312填充金属或内壁面覆有金属，在所述主体件31上下表面镀覆第二金属层35；
在所述主体件31下表面的第二金属层35上设置第二电接触块36；
将所述电连接件3通过所述第二电接触块36键合在所述接地线路层111上，所述第二金属层35覆盖或跨越切割道。
流程三：
S2c1：如图32所示，将金属凸块、锡球、铜核球61中的一种或多种的组合结构电连接至所述接地线路层111，并覆盖切割道。
流程四：
S2d1：如图33所示，在所述接地线路层111上电镀铜凸块62，所述铜凸块62的位置覆盖或跨越至少部分切割道。
流程五：
S2e1：如图34所示，将在切割道两侧的所述接地线路层111通过常规金属焊线7键合连接。
流程六：
S2f1：如图35所示，在所述接地线路层111上涂覆金属膏8，并覆盖或跨越至少部分切割道。
综上所述，本发明通过所述电连接件将所述第一屏蔽层连接至所述接地线路层，从而可利用所述电连接件分别与所述第一屏蔽层和所述接地线路层实现相对大面积的面接触，从而降低三者间的电阻，来提高所述第一屏蔽层的屏蔽效果，以避免将所述第一屏蔽层直接与薄的所述金属线路层在侧面连接而出现较高的电阻。同时，本发明中的电连接件采用常规低成本材料，制程简单，易于实现，适用于大规模工业化制造流程。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (30)

  1. 一种扇出型封装结构，包括重布线层和设于其第一面上的至少一个芯片或带芯片封装体，其特征在于，
    所述重布线层包括接地线路层；
    所述扇出型封装结构还包括至少一塑封层、至少一第一屏蔽层和至少一个电连接件，所述电连接件设于所述重布线层第一面上，位于所述芯片或带芯片封装体外侧，并电性连接至所述接地线路层；
    所述塑封层至少设于所述重布线层第一面之上，包封所述电连接件和所述芯片或带芯片封装体；
    所述第一屏蔽层至少有部分覆盖于所述塑封层的侧表面；
    所述电连接件至少有部分暴露于所述塑封层侧面，并电性连接至所述第一屏蔽层，所述第一屏蔽层和所述接地线路层之间通过所述电连接件电性导通。
  2. 根据权利要求1所述的扇出型封装结构，其特征在于，所述重布线层包括图形化的金属线路层和图形化的介电层，所述金属线路层至少有部分形成接地线路层。
  3. 根据权利要求2所述的扇出型封装结构，其特征在于，所述金属线路层厚度小于10μm，最小线距小于15μm。
  4. 根据权利要求2所述的扇出型封装结构，其特征在于，相对于所述重布线层第一面的第二面上设有第一电接触块，所述第一电接触块电连接至所述金属线路层。
  5. 根据权利要求2所述的扇出型封装结构，其特征在于，所述介电层的材料包括有机高分子树脂、带无机填料的有机高分子树脂、带玻纤布与填料片的有机高分子树脂、聚酰亚胺中的一种或多种的组合，所述金属线路层的材料包括铜、钛、钛钨中的一种或多种的组合。
  6. 根据权利要求1所述的扇出型封装结构，其特征在于，所述电连接件包括主体件，所述主体件的材料为带无机填料的有机高分子树脂、或带玻纤布与填料片的有机高分子树脂。
  7. 根据权利要求6所述的扇出型封装结构，其特征在于，所述主体件朝向与其相邻的所述第一屏蔽层侧壁的一侧设有贯通其上下表面的第一通孔。
  8. 根据权利要求7所述的扇出型封装结构，其特征在于，所述第一通孔内填充有导电填料，所述主体件底部被所述导电填料包覆，电性连接于所述接地线路层，所述导电填料侧面露出所述塑封层与所述第一屏蔽层电性连接。
  9. 根据权利要求8所述的扇出型封装结构，其特征在于，所述导电填料为包括银和/或铜的导电胶、或金属焊料。
  10. 根据权利要求7所述的扇出型封装结构，其特征在于，所述主体件的上表面、下表面和所述第一通孔的侧壁面中的一处或多处设有第一金属层。
  11. 根据权利要求6所述的扇出型封装结构，其特征在于，所述主体件上下表面设有第二金属层，所述第二金属层暴露于所述塑封层侧面，与所述第一屏蔽层电性连接。
  12. 根据权利要求11所述的扇出型封装结构，其特征在于，所述主体件内设有第二通孔，所述第二通孔连通所述主体件上下表面，所述第二通孔内填充有金属或内壁面覆有金属，电性连通所述主体件上下表面的所述第二金属层。
  13. 根据权利要求11所述的扇出型封装结构，其特征在于，所述主体件于位于其下表面的第二金属层上设有第二电接触块，所述第二电接触块与所述接地线路层电性连接。
  14. 根据权利要求1所述的扇出型封装结构，其特征在于，所述电连接件的材料为导电材料。
  15. 根据权利要求14所述的扇出型封装结构，其特征在于，所述电连接件为所述电连接件为电镀在所述接地线路层上的铜凸块，或为键合在所述接地线路层上的金属凸块、部分锡球、部分铜核球中的一种或多种的组合结构，或为烧结固化的金属或合金膏。
  16. 根据权利要求14所述的扇出型封装结构，其特征在于，所述电连接件为部分金属焊线，其一端通过焊球与所述接地线路层电性连接，另一端暴露于所述塑封层侧面，与所述第一屏蔽层相连。
  17. 根据权利要求1所述的扇出型封装结构，其特征在于，所述第一屏蔽层与所述塑封层之间还设有第二屏蔽层，所述第二屏蔽层为单层屏蔽层或多层复合屏蔽层，所述第二屏蔽层至少在一部分频率范围内与所述第一屏蔽层具有相异的屏蔽系数。
  18. 根据权利要求17所述的扇出型封装结构，其特征在于，所述第二屏蔽层内设有多个屏蔽层凹槽或屏蔽层通孔，所述第一屏蔽层填充于所述屏蔽层凹槽或所述屏蔽层通孔内，或所述第一屏蔽层镀覆于所述屏蔽层凹槽或所述屏蔽层通孔的内壁面上。
  19. 根据权利要求1所述的扇出型封装结构，其特征在于，所述电连接件位于所述重布线层的四个角上和/或四条边上，且以所述重布线层的中心呈基本对称式分布。
  20. 一种扇出型封装结构的制造方法，其特征在于，包括步骤：
    提供一载板，在所述载板上制作图形化的金属线路层和介电层，堆叠形成重布线层，将至少部分靠近或覆盖或跨越至少部分切割道的所述金属线路层形成接地线路层；
    将芯片、和/或带芯片封装体、和/或被动器件设于所述重布线层第一面，并电性连接至所述金属线路层；
    将电连接件设于所述重布线层第一面上，并覆盖或跨越至少部分所述切割道，电连接至 所述接地线路层；
    将所述芯片和所述电连接件塑封形成塑封层；
    去除所述载板，在相对于所述重布线层第一面的第二面上形成第一电接触块；
    将完整封装体沿切割道切割形成单个封装结构；
    在单个封装结构的所述塑封层外侧形成第一屏蔽层，所述第一屏蔽层至少覆盖所述塑封层侧面。
  21. 根据权利要求20所述的扇出型封装结构的制造方法，其特征在于，所述金属线路层厚度小于10μm，最小线距小于15μm。
  22. 根据权利要求20所述的扇出型封装结构的制造方法，其特征在于，所述介电层的材料包括有机高分子树脂、带无机填料的有机高分子树脂，带玻纤布与填料片的有机高分子树脂、聚酰亚胺的一种或多种的组合，所述金属线路层的材料包括铜、钛、钛钨中的一种或多种的组合。
  23. 根据权利要求20所述的扇出型封装结构的制造方法，其特征在于，“将电连接件设于所述重布线层第一面上”具体包括：
    在主体件上制作贯穿其上下表面的第一通孔，在所述第一通孔内填充导电填料，并在所述主体件底面涂覆所述导电填料，将其通过导电填料电连接至所述接地线路层，所述第一通孔覆盖或跨越至少部分切割道。
  24. 根据权利要求23所述的扇出型封装结构的制造方法，其特征在于，所述主体件的材料为带无机填料的有机高分子树脂，或带玻纤布与填料有机高分子树脂，所述导电填料为包括银和/或铜的导电胶、或金属焊料。
  25. 根据权利要求23所述的扇出型封装结构的制造方法，其特征在于，所述主体件的上表面、下表面和所述第一通孔的侧壁面中的一处或多处形成有金属层。
  26. 根据权利要求20所述的扇出型封装结构的制造方法，其特征在于，“将电连接件设于所述重布线层第一面上”具体包括：
    在主体件上制作贯穿其上下表面的第二通孔，在所述第二通孔内镀覆金属，并在所述主体件上下表面设置第二金属层，所述第二金属层覆盖或跨越至少部分切割道；
    在所述主体件下表面的所述第二金属层上制作第二电接触块，将所述电接触件通过第二电接触块键合于所述接地线路层上。
  27. 根据权利要求20所述的扇出型封装结构的制造方法，其特征在于，“将电连接件设于所述重布线层第一面上”具体包括：
    将金属凸块、锡球、铜核球中的一种或多种的组合结构键合电连接至所述接地线路层， 并覆盖或跨越至少部分切割道；或在所述接地线路层上电镀铜凸块，所述铜凸块覆盖或跨越至少部分切割道；或在所述接地线路层上设置烧结固化的金属或合金膏，并覆盖或跨越至少部分切割道。
  28. 根据权利要求20所述的扇出型封装结构的制造方法，其特征在于，“将电连接件设于所述重布线层第一面上”具体包括：将在切割道两侧的所述接地线路层通过金属焊线键合连接。
  29. 根据权利要求20所述的扇出型封装结构的制造方法，其特征在于，在制作所述第一屏蔽层之前还包括步骤：
    在所述塑封层上制作一层或多层屏蔽层形成第二屏蔽层；
    在所述第二屏蔽层上制作多个的屏蔽层凹槽或屏蔽层通孔；
    将所述第一屏蔽层材料填充或镀覆于所述屏蔽层凹槽或所述屏蔽层通孔上。
  30. 根据权利要求29所述的扇出型封装结构的制造方法，其特征在于，所述第二屏蔽层至少在一部分频率范围内与所述第一屏蔽层具有相异的屏蔽系数。
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