WO2022105161A1 - 天线封装结构及天线封装结构制造方法 - Google Patents

天线封装结构及天线封装结构制造方法 Download PDF

Info

Publication number
WO2022105161A1
WO2022105161A1 PCT/CN2021/094566 CN2021094566W WO2022105161A1 WO 2022105161 A1 WO2022105161 A1 WO 2022105161A1 CN 2021094566 W CN2021094566 W CN 2021094566W WO 2022105161 A1 WO2022105161 A1 WO 2022105161A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
antenna
packaging
chip
packaging structure
Prior art date
Application number
PCT/CN2021/094566
Other languages
English (en)
French (fr)
Inventor
林耀剑
刘硕
徐晨
杨丹凤
Original Assignee
江苏长电科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 江苏长电科技股份有限公司 filed Critical 江苏长电科技股份有限公司
Priority to US18/035,520 priority Critical patent/US20230411826A1/en
Publication of WO2022105161A1 publication Critical patent/WO2022105161A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/52—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
    • H01Q1/526—Electromagnetic shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H01Q21/065—Patch antenna array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/0414—Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Definitions

  • the present invention relates to the technical field of packaging, in particular to an antenna packaging structure and a method for manufacturing the antenna packaging structure.
  • wireless communication equipment usually includes an antenna module and one or more integrated circuit.
  • Antenna modules and integrated circuits can be arranged in several different ways (eg, antenna-in-package (AIP), antenna-on-package (AOP), antenna-on-chip (AOC), etc.).
  • the electrical signal between the antenna module and the integrated circuit usually needs to be transmitted through one or more conductive lines and/or one or more through-holes, which are made or filled with conductive materials and which are in contact with dielectric materials.
  • Contacting and/or being at least partially surrounded by a dielectric material is prone to problems such as current leakage, stray capacitance, etc. due to the relatively high dielectric losses of conventional dielectric materials such as silicon or molding compounds.
  • the reliability of the package structure under conditions such as high temperature and high pressure is poor and is not conducive to the miniaturization of the package structure.
  • the purpose of the present invention is to provide an antenna package structure and a method for manufacturing the antenna package structure.
  • the invention provides an antenna packaging structure, the antenna packaging structure comprises: a substrate layer, an interconnection structure, an antenna support, a first antenna layer, a chip and a plastic packaging layer;
  • the substrate layer includes at least one chip circuit layer, at least one antenna control layer and at least one second antenna layer, which are stacked in sequence, and the dielectric between the first antenna layer and the second antenna layer is a dielectric layer.
  • the loss tangent value is less than 0.01;
  • the first antenna layer is electrically connected to the second antenna layer through an interconnect structure
  • the antenna support member is attached to the side of the first antenna layer facing the second antenna layer, and the dielectric loss tangent value thereof is less than 0.01;
  • the chip is arranged on the control circuit layer relative to the first antenna layer;
  • the plastic encapsulation layer covers the substrate layer, the antenna support, the first antenna layer, the interconnect structure and the chip.
  • the antenna support is one or more of a single-layer or multi-layer organic composite substrate, a plastic package, a glass piece and a low-temperature co-fired ceramic piece.
  • the antenna support member is a pure dielectric member, or a resonant cavity provided with metal on the other five sides except the surface that is in contact with the first antenna layer.
  • the interlayer dielectric material of the first antenna layer and the second antenna layer is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with filler.
  • the antenna control layer includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • the antenna packaging structure is further provided with a first moisture barrier layer outside the plastic sealing layer, and the first moisture barrier layer at least covers the first antenna layer, the antenna support and the The second antenna layer.
  • the antenna package structure further includes an interconnection structure disposed on the second antenna layer and the chip circuit layer, and the interconnection structure is electrically connected to the substrate layer line.
  • the interconnecting structural members are conductive metal pillars and/or composite structural members.
  • the composite structural member includes a main body member made of a dielectric material, and a conductive through hole located inside the main body member and communicated with the upper and lower surfaces thereof, and the conductive through hole is provided with a metal connecting member or a conductive through hole
  • the filler is electrically connected to the circuit layer, and the composite structural members disposed on one side of the second antenna layer are distributed between the voids in the antenna support member and on the peripheral side thereof.
  • the portions of the interconnection structure located on both sides of the package structure are further provided with lateral antenna layers, and the lateral antenna layers are disposed toward the side edges of the antenna package structure.
  • the sidewall of the interconnection structure is provided with a heat dissipation structure and/or a second moisture barrier layer, and the second moisture barrier layer is exposed or buried in the plastic encapsulation layer.
  • a pre-molding layer is provided on the peripheral sides of the antenna support member and the interconnection structure member.
  • the plastic encapsulation layer includes a first plastic encapsulation layer and a second plastic encapsulation layer, and the first plastic encapsulation layer at least covers the upper surface of the substrate layer, the side surface of the antenna support, and the interconnection structure.
  • the side surface of the component and the first antenna layer, the second plastic packaging layer at least covers the side surface of the chip and the side surface of the interconnect structure component, and the materials of the first plastic packaging layer and the second plastic packaging layer are different.
  • the antenna packaging structure is further provided with an electromagnetic shielding layer outside the plastic sealing layer, the electromagnetic shielding layer covers at least the lateral direction of the chip and the chip circuit layer, and the electromagnetic shielding layer includes: On the adhesive layer of the plastic encapsulation layer, the protective layer exposed to the air, and the main shielding layer arranged between the adhesive layer and the protective layer, the side walls of the interconnecting structural members are provided with metal structural members , the metal structure is exposed to the plastic encapsulation layer and is electrically grounded to the electromagnetic shielding layer.
  • the electromagnetic shielding layer is provided with a through hole exposing the metal structure, and the through hole is filled with sintered conductive paste or solder.
  • the antenna package structure further includes a microwave integrated circuit and/or a power management chip and/or a passive device disposed on the chip circuit layer.
  • the present invention also provides a packaging method for the antenna packaging structure, which is characterized by comprising the steps of:
  • At least one second antenna layer, at least one antenna control layer and at least one chip circuit layer are formed into prefabricated substrate layer single particles or strips, and the interconnection structure on the first antenna layer is electrically bonded , the second antenna layer uses a dielectric material whose dielectric loss tangent value is less than 0.01 as an interlayer medium;
  • the temporary carrier is removed, an interconnect structure and at least one chip are arranged on the chip circuit layer, a second plastic packaging layer is performed, and a single-piece antenna packaging structure is formed by cutting.
  • the antenna support is one or more of organic single-layer or multi-layer composite substrates, plastic encapsulation layers, glass parts and low-temperature co-fired ceramic parts, and the antenna support can be a pure dielectric part , or a resonant cavity with metal on the other 5 sides except the first antenna layer.
  • the interlayer dielectric material of the second antenna layer is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with filler.
  • the chip circuit layer includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • the interconnect structure on the second antenna layer is a conductive metal column.
  • the interconnecting structural member includes a main body member formed of a dielectric material, and a metal connecting member located inside the main body member and communicating with the upper and lower surfaces thereof, the metal connecting member is connected to the substrate layer on the substrate layer.
  • the circuit layer is electrically connected.
  • the interconnecting structural members disposed on one side of the second antenna layer are distributed between the voids in the antenna support member and its peripheral side, and the upper surface of the interconnecting structural member is low on the upper surface of the first antenna layer.
  • the portions of the interconnection structure located on both sides of the package structure are further provided with lateral antenna layers, and the lateral antenna layers are disposed toward the side edges of the antenna package structure.
  • the sidewall of the interconnect structure is provided with a heat dissipation structure and/or a second moisture barrier layer, and the second moisture barrier layer is exposed to the plastic sealing layer.
  • An adhesive layer, a main shielding layer and a protective layer are sequentially deposited on the outside of the antenna packaging structure to form an electromagnetic shielding layer, and the electromagnetic shielding layer at least covers the chip and the chip circuit layer.
  • a through hole exposing the interconnection structure is formed on the electromagnetic shielding layer, and a sintered conductive paste or solder is filled in the through hole.
  • a first moisture-blocking layer is formed outside the antenna package structure, and the first moisture-blocking layer covers at least the first antenna layer, the antenna support and the second antenna layer.
  • the antenna package structure further includes a microwave integrated circuit, a power management chip and a passive device disposed on the chip circuit layer.
  • the present invention separates the antenna and the chip on both sides of the substrate layer, and the antenna layer is composed of the antenna support, the first antenna layer above the antenna support, and the second antenna layer below the antenna support , the antenna support and the interlayer medium of the antenna are made of low dielectric loss materials, so as to form a heterogeneous antenna structure, so as to reduce the current leakage and stray capacitance in the package structure caused by dielectric loss, and reduce The size of the small antenna package structure.
  • FIG. 1 is a schematic diagram of an antenna package structure in an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an antenna package structure in another embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a substrate layer and an antenna layer in an antenna package structure according to another embodiment of the present invention, and a lateral antenna layer is provided on the part of the interconnect structure on both sides of the package structure.
  • FIG. 4 is a schematic diagram of a substrate layer and an antenna layer in an antenna package structure in another embodiment of the present invention, in which the antenna support member is omitted.
  • FIG. 5 is a manufacturing flow chart of an antenna package structure in an embodiment of the present invention.
  • 6 to 11 are schematic diagrams of steps of a manufacturing process of an antenna package structure in an embodiment of the present invention.
  • the term used to describe the relative position in space such as “upper”, “lower”, “rear”, “front”, etc., is used to describe one unit or feature shown in the drawings relative to another A unit or feature relationship.
  • the term spatially relative position may include different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as “below” or “above” other elements or features would then be oriented “below” or “above” the other elements or features.
  • the exemplary term “below” can encompass both a spatial orientation of below and above.
  • the present invention provides an antenna package structure including: a substrate layer 1 , an antenna support member 2 , a first antenna layer 3 , an interconnection structure member 6 , a plastic packaging layer 4 and at least one chip 5 .
  • the substrate layer includes a chip circuit layer 11 , an antenna control layer 12 and at least one second antenna layer 13 that are stacked in sequence.
  • the dielectric loss of the interlayer medium between the first antenna layer 11 and the second antenna layer 13 The tangent value is less than 0.01, and the substrate layer 1 is additionally prefabricated.
  • the antenna control layer 12 includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • the interlayer dielectric material of the second antenna layer 13 is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with fillers.
  • a low dielectric constant and low dielectric loss The material is used as the interlayer dielectric material of the second antenna layer 13, which can reduce the dielectric loss and capacitive reactance in the antenna circuit, thereby reducing the problems of current leakage and stray capacitance caused by the dielectric loss.
  • the first antenna layer 3 is electrically connected to the second antenna layer 13 through the interconnect structure 6 .
  • the antenna support 2 is attached to the side of the first antenna layer 3 facing the second antenna layer 13 , and the dielectric loss tangent value thereof is less than 0.01.
  • the interconnect structure 6 disposed on one side of the second antenna layer 13 is a conductive metal column 6a, such as a copper column, which is electrically connected to the substrate layer through a copper core or a plastic core solder ball. 1.
  • the interconnection structure 6 disposed on one side of the chip circuit layer 11 is a composite structure 6b.
  • the composite structure 6b includes a main body 61 formed of a dielectric material, and conductive through holes 62 or For stacking holes, the conductive through holes 62 are provided with metal connectors or conductive fillers to be electrically connected to the grounding circuit layer.
  • the upper and lower surfaces of the main body member 61 are plated with metal layers, and the composite structural member 6b is electrically connected to the circuit layer by soldering or conductive glue/paste.
  • the main body 61 is also an organic composite substrate with low dielectric loss, a glass part and a low-temperature co-fired ceramic part, so as to further reduce the dielectric loss in the package structure, or the main body 61 can also be made of organic composite substrates with inorganic fillers.
  • the side wall of the composite structure 6b is provided with a heat dissipation structure 63 and/or a second moisture barrier layer 64.
  • the second moisture barrier layer 64 is exposed or buried in the plastic sealing layer 4.
  • High thermal conductivity materials are made into columnar or thin-layered structures. Thus, the reliability of the package structure under high temperature and high humidity conditions is further improved.
  • the second antenna layer 13 and the chip circuit layer 11 are provided with a composite structure 6b, and the composite structure 6b is provided on one side of the second antenna layer 13 They are distributed between the gaps in the antenna support member 2 and the surrounding sides thereof, so as to maximize and effectively utilize the space in the package structure.
  • interconnecting structural members 6 are not limited to this, as long as they can play an electrical connection role.
  • the antenna support member 2 and the interconnection structure member 6 are provided with a pre-molding layer 43 on the peripheries.
  • the portions of the interconnection structure 6 located on both sides of the package structure are further provided with lateral antenna layers 65 , and the lateral antenna layers 65 are disposed toward the side edges of the antenna package structure,
  • the interconnecting structural member 6 is provided with a circuit or a conductive connecting member that electrically connects the lateral antenna layer 65 and the antenna control layer 12 .
  • the antenna support 2 is made of materials with low dielectric loss, so that the antenna circuit forms a heterogeneous split structure, and the antenna support 2 serves as the main body 61 of the antenna circuit to reduce the dielectric loss in the circuit.
  • the shape of the antenna support 2 can be specifically set according to the shape of the plane arrangement of the first antenna layer 3 and the number of antenna modules in the first antenna layer 3, and the outline shape of the horizontal plane of the antenna support 2 is roughly similar to that of the first antenna.
  • the planar arrangement shape of the antenna circuit of layer 3 can make the antenna support 2 with low dielectric loss play a good supporting role for the first antenna, and at the same time reduce the space occupied in the package structure.
  • the antenna support member 2 is one or more of an organic composite substrate, a glass member and a low-temperature co-fired ceramic member, and the organic composite plate and the glass member have low dielectric constant while having low dielectric loss, Low temperature co-fired ceramics have a high dielectric constant with low dielectric loss.
  • the antenna support member 2 is a pure dielectric member, or a resonant cavity provided with metal on the other five sides except the surface that is in contact with the first antenna layer 3 . Under the condition of ensuring low dielectric loss, by using antenna supports 2 with different dielectric constants, the package structure can be adapted to chips 5 with different usage conditions, and the requirements for high-density integration of the package structure are met.
  • the antenna support 2 is attached to the first antenna layer 3 through a chip film or adhesive paste, which can cover the entire surface of the first antenna layer 3 or partially extend to the interconnect structure 6 .
  • the chip 5 is disposed on the chip circuit layer 11 , that is, the chip 5 and the antenna layer are disposed on two opposite surfaces of the substrate layer 1 .
  • the antenna layer and the chip 5 are arranged on both sides of the substrate layer 1, on the one hand, the circuit layers on the substrate layer 1 can be arranged in layers, the chip 5 and the chip circuit layer 11 are arranged on one side, and the antenna control circuit layer and The antenna layer is arranged on one side, which facilitates the wiring design on the substrate layer 1 in sequence; on the other hand, the signal interference of the antenna layer to the chip 5 can be reduced.
  • the antenna supporting member 2 provided on the antenna side may also be omitted, and the first antenna layer 3 and the second antenna layer 13 are only connected by the interconnecting structural member 6 .
  • the plastic sealing layer 4 covers the substrate layer 1 , the antenna support 2 , the first antenna layer 3 and the chip 5 .
  • the plastic sealing layer 4 is filled with a plastic sealing compound, and the plastic sealing material can be epoxy resin, polyimide, dry film and other polymer composite materials with fillers.
  • the inner element plays a protective role.
  • the plastic encapsulation layer 4 includes a first plastic encapsulation layer 41 and/or a second plastic encapsulation layer 42 , and the first plastic encapsulation layer 41 covers the substrate layer 1 , the antenna support 2 and the first antenna layer 3 .
  • the second plastic sealing layer 42 covers the chip 5 .
  • the first plastic sealing layer 41 and the second plastic sealing layer 42 use different plastic sealing compounds, so that the difference in thermal expansion coefficient of the different plastic sealing materials can be used to adjust the warpage problem of the packaging structure.
  • the first or second plastic package may also cover the substrate layer 1 , the antenna support member 2 and the first antenna layer 3 , the chip 5 and the interconnection structure member 6 at the same time.
  • first plastic sealing layer 41 covers the antenna support 2 and the first antenna layer.
  • second plastic sealing layer 42 covers the substrate layer 1 and the chip 5 .
  • the antenna packaging structure is further provided with a first moisture barrier layer 7 outside the plastic sealing layer 4 , and the first moisture barrier layer 7 at least covers the first antenna layer 3 , the The antenna support 6 and the second antenna layer 13 further improve the reliability of the package structure under high humidity conditions.
  • an underfill 51 is further provided between the chip 5 and the chip circuit layer 11 .
  • the antenna package structure further includes a microwave integrated circuit and/or a power management chip and/or a passive device disposed on the chip circuit layer 11 .
  • Passive devices include capacitors, resistors, etc., or other functional devices such as heat sinks and stiffeners.
  • the antenna packaging structure is further provided with an electromagnetic shielding layer 8 outside the packaging layer.
  • the electromagnetic shielding layer 8 covers at least the chip 5 and the chip circuit layer 11 to reduce electromagnetic wave interference received by the chip 5 .
  • the electromagnetic shielding layer 8 includes: an adhesive layer attached to the plastic sealing layer 4 , a protective layer exposed to the air, and a main shielding layer disposed between the adhesive layer and the protective layer.
  • the adhesive layer is a metal material with high adhesion such as copper, or an organic material with high adhesion, so as to strengthen the bonding strength between the electromagnetic shielding layer 8 and the package structure.
  • the main shielding layer is a sputtered sandwich metal film material such as copper, stainless steel, titanium, etc., or a conductive composite material such as a conductive resin containing high-density metal fillers such as silver/copper, or a combination of at least two of the above materials, capable of Play the role of shielding or absorbing electromagnetic waves.
  • the protective layer is a stainless steel (7% NiV) or CrCu alloy layer, or an organic moisture barrier layer, etc., to further enhance the reliability of the package structure under high humidity conditions.
  • the side wall of the interconnection structure 6 is provided with a metal structure, and the metal structure is exposed to the plastic encapsulation layer 4 and is electrically connected to the electromagnetic shielding layer 8 .
  • the electromagnetic shielding layer 8 is provided with a through hole 81 exposing the metal structure, and the through hole 81 is filled with sintered conductive paste or solder to strengthen the ground connection of the electromagnetic shielding layer.
  • the position of the part of the horizontal cutting surface covered by the electromagnetic shielding layer 8 is different.
  • the present invention also provides a packaging method for an antenna packaging structure, comprising the steps of:
  • a temporary carrier board 9 with an optional temporary bonding layer is provided, the first antenna layer 3 and the interconnection structure 6 are arranged on the temporary carrier board 9, and the first antenna layer 3 is made of dielectric Dielectric materials with loss tangent less than 0.01 are used as interlayer dielectrics.
  • Temporary carrier plate 9 is a low cost, somewhat rigid sacrificial substrate such as glass, silicon, composite polymer, etc., for structural support.
  • the interlayer dielectric material of the first antenna layer 3 is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with a filler.
  • the interconnecting structural member 6 is a conductive metal column, such as a cylindrical copper column and a rectangular parallelepiped.
  • the interconnection structure member 6 includes a main body member 61 made of a dielectric material, and a metal connection member located inside the main body member 61 and communicated with the upper and lower surfaces thereof, and the metal connection member is connected to the ground on the substrate layer 1 .
  • the circuit layer is electrically connected.
  • the upper surface and the lower surface of the main body member 61 are plated with metal layers, and the interconnection structure member 6 is electrically connected to the grounding circuit layer through solder, or conductive glue/paste.
  • the main body 61 is an organic composite substrate with low dielectric loss, a glass part and a low-temperature co-fired ceramic part, so as to further reduce the dielectric loss in the package structure, or the main body 61 can also be made of an organic composite substrate with inorganic fillers. Molecular resin, or organic polymer resin with glass fiber cloth and filler, synthetic resin and other polymer materials with certain structural strength.
  • the portions of the interconnection structure 6 located on both sides of the package structure are further provided with lateral antenna layers 65, and the lateral antenna layers 65 are disposed toward the side edges of the antenna package structure.
  • the sidewall of the interconnection structure 6 is provided with a heat dissipation structure 63 and/or a second moisture barrier layer 64 , and the second moisture barrier layer 64 is exposed or buried in the plastic sealing layer 4 .
  • the antenna support 2 is one or more of an organic single-layer or multi-layer composite substrate, a plastic package, a glass piece and a low-temperature co-fired ceramic piece.
  • the antenna support member 2 is a pure dielectric member, or a resonant cavity provided with metal on the other five sides except the surface that is in contact with the first antenna layer 3 .
  • the antenna support 2 is attached to the first antenna layer 3 by a material such as film or adhesive paste.
  • the interconnecting structural members 6 are distributed between the voids in the antenna support member 2 and the peripheral sides thereof.
  • the prefabricated substrate layer 1 formed by at least one second antenna layer 13 , the antenna control layer 12 and the chip circuit layer 11 is provided on the interconnect structure 6 , and the first The two antenna layers 13 use a dielectric material whose dielectric loss tangent value is less than 0.01 as an interlayer medium.
  • the prefabricated substrate layer 1 can be pre-bonded with the chip and the interconnection structure 6, and then placed on the interconnection structure 6 together for solder reflow bonding, and the substrate layer 1 can be Pre-bonded copper core/plastic core solder balls and/or regular SnAgCu balls.
  • the antenna control layer 12 includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • the interlayer dielectric material of the second antenna layer 13 is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with filler.
  • the plastic encapsulation compound filling the first plastic encapsulation layer 41 covers the substrate layer 1 , the interconnection structure 6 , the antenna support 2 and the first antenna layer 3 .
  • the first plastic packaging layer 41 may not cover the chip surface of the substrate layer 1 during plastic sealing, or may cover the chip surface of the substrate layer 1 first, and then the first plastic packaging layer 41 may be thinned to expose the pads on the chip surface of the substrate layer 1 .
  • a first plastic sealing layer 41 is formed by encapsulating the interconnecting structural member, the antenna support member 2 and the first antenna layer 3 .
  • the steps before refilling the plastic sealing compound, the steps further include:
  • the temporary carrier plate 9 is peeled off by methods such as laser debonding separation, mechanical peeling, chemical etching, and mechanical grinding.
  • the complete package structure is divided into individual package structures along the dicing lines by a saw blade or a laser cutting device.
  • plastic packaging of the chip 5 further includes the steps:
  • An underfill 51 is coated between the chip 5 and the chip circuit layer 11 .
  • setting the chip 5 also includes the steps of:
  • Microwave integrated circuits and/or power management chips and/or passive devices are arranged on the chip circuit layer 11 .
  • Passive devices include capacitors, resistors, etc., or other functional devices such as heat sinks and stiffeners.
  • An adhesive layer, a main shielding layer and a protective layer are sequentially deposited on the outside of the antenna packaging structure to form an electromagnetic shielding layer 8, and the electromagnetic shielding layer 8 at least covers the chip 5 and the chip circuit layer 11;
  • a through hole 81 exposing the metal structure is formed on the electromagnetic shielding layer 8 , and a sintered conductive paste or solder is filled in the through hole 81 .
  • the electromagnetic shielding layer 8 includes: an adhesive layer attached to the plastic sealing layer 4 , a protective layer exposed to the air, and a main shielding layer disposed between the adhesive layer and the protective layer.
  • the adhesive layer is a metal material with high adhesion such as copper, or an organic material with high adhesion.
  • the primary shielding layer is a sputtered sandwich metal film material such as copper, stainless steel, titanium, etc., or a conductive composite material such as a conductive resin containing high-density metal fillers such as silver/copper, or a combination of at least two of the above materials.
  • the protective layer is stainless steel, NiV (7%) or CrCu alloy layer, or organic moisture barrier layer.
  • the electromagnetic shielding layer 8 may also be formed after complete cutting.
  • the steps before or after cutting to form a single antenna package, the steps further include:
  • a first moisture-blocking layer 7 is formed outside the antenna package structure, and the first moisture-blocking layer 7 covers at least the first antenna layer 3 , the antenna support member 2 and the second antenna layer 13 .
  • the order of some steps in the present invention can be exchanged and adjusted.
  • the chip 5 and the substrate layer 2 can be placed on the temporary carrier 9 first, and then the temporary carrier 9 can be removed to form the antenna support 2 and the substrate layer 2.
  • the antenna layer, etc. only needs to be able to form a relatively distributed chip and antenna layer package structure.
  • the present invention separates the antenna and the chip on both sides of the substrate layer.
  • the antenna layer is composed of the antenna support, the first antenna layer located above the antenna support, and the second antenna layer located below the antenna support.
  • the low dielectric loss material is used for the interlayer medium between the support member and the antenna layer to form a heterogeneous antenna structure, so as to reduce the current leakage and stray capacitance in the package structure caused by the dielectric loss, and reduce the size of the antenna. Dimensions of the package structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Details Of Aerials (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

本发明提供一种天线封装结构及天线封装结构制造方法，将天线和芯片分设于基板层两侧，天线层由天线支撑件、位于天线支撑件上方的第一天线层和位于天线支撑件下方的第二天线层共同构成，天线支撑件和天线层层间介质采用低介电损耗材料，从而形成异质异构的天线结构，以减少因介电损耗带来的封装结构内电流泄漏、杂散电容等问题，并减小天线封装结构的尺寸。

Description

天线封装结构及天线封装结构制造方法 技术领域
本发明涉及封装技术领域，具体地涉及一种天线封装结构及天线封装结构制造方法。
背景技术
随着高科技电子产品的普及以及人们需求的增加，特别是为了配合移动的需求，大多高科技电子产品都增加了无线通讯的功能，目前无线通信设备通常会包括天线模块和一个或多个集成电路。天线模块和集成电路可以按数种不同方式(例如，封装内天线(AIP)、封装上天线(AOP)、片上天线(AOC)等)来布置。
天线模块与集成电路之间电信号通常需要通过一条或多条导电线路和/或一个或多个贯通孔来实现传输，这些线路和通孔由导电材料制成或填充，并且其与介电材料接触和/或被介电材料至少部分地包围，由于常规的介电材料(诸如硅或模塑化合物)具有较高的介电损耗，从而易产生诸如电流漏泄、杂散电容等问题。并且，由于常规介电材料性能所限，封装结构的在诸如高温高压条件下的可靠性较差且不利于封装结构的小型化。
发明内容
本发明的目的在于提供一种天线封装结构及天线封装结构制造方法。
本发明提供一种天线封装结构，所述天线封装结构包括：基板层、互连结构件、天线支撑件、第一天线层、芯片和塑封层；
所述基板层包括依次堆叠设置的至少一层芯片线路层、至少一层天线控制层和至少一层第二天线层，所述第一天线层和所述第二天线层层间介质的介电损耗正切值小于0.01；
所述第一天线层通过互连结构件电性连接于所述第二天线层；
所述天线支撑件贴合于所述第一天线层朝向所述第二天线层的一侧，其介电损耗正切值小于0.01；
所述芯片相对于所述第一天线层，设于所述控制线路层上；
所述塑封层包覆所述基板层、所述天线支撑件、所述第一天线层、所述互连结 构件和所述芯片。
作为本发明的进一步改进，所述天线支撑件为单层或多层有机复合基板，塑封件，玻璃件和低温共烧陶瓷件中的一种或多种。
作为本发明的进一步改进，所述天线支撑件为纯介电件，或为除与所述第一天线层相接面外其余五个侧面设有金属的共振腔。
作为本发明的进一步改进，所述第一天线层和第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
作为本发明的进一步改进，所述天线控制层包括天线信号控制线路和天线信号发送接收线路。
作为本发明的进一步改进，所述天线封装结构于塑封层外侧还设有第一阻湿层，所述第一阻湿层至少包覆所述第一天线层、所述天线支撑件和所述第二天线层。
作为本发明的进一步改进，所述天线封装结构还包括设于所述第二天线层和设于所述芯片线路层上的互连结构件，所述互连结构件电性连接于所述基板层线路。
作为本发明的进一步改进，所述互连结构件为导电金属柱和/或复合结构件。
作为本发明的进一步改进，所述复合结构件包括由介电材料构成主体件，以及位于所述主体件内部连通其上下表面的导电通孔，所述导电通孔内设有金属连接件或导电填料以与线路层电性连接，设于所述第二天线层一侧的所述复合结构件分布于所述天线支撑件内空隙之间及其周侧。
作为本发明的进一步改进，所述互连结构件位于所述封装结构两侧的部分还设有侧向天线层，所述侧向天线层朝向所述天线封装结构侧边缘设置。
作为本发明的进一步改进，所述互连结构件的侧壁设有散热结构件和/或第二阻湿层，所述第二阻湿层暴露于或埋入于所述塑封层。
作为本发明的进一步改进，其特征在于，所述天线支撑件和所述互连结构件周侧设有预塑封层。
作为本发明的进一步改进，所述塑封层包括第一塑封层和第二塑封层，所述第一塑封层至少包覆所述基板层上表面、所述天线支撑件侧面，所述互连结构件侧面和所述第一天线层，所述第二塑封层至少包覆所述芯片侧面和互连结构件侧面，所述第一塑封层和所述第二塑封层材料相异。
作为本发明的进一步改进，所述天线封装结构于塑封层外侧还设有电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层的侧向，所述电磁屏蔽层包括：贴合于所述塑封层的粘结层，暴露于空气的保护层，以及设于所述粘结层和所述保护 层之间的主屏蔽层，所述互连结构件侧壁设有金属结构件，所述金属结构件暴露于所述塑封层与所述电磁屏蔽层电性接地连接。
作为本发明的进一步改进，所述电磁屏蔽层上设有暴露所述金属结构件的通孔，所述通孔内填充有烧结导电膏或锡焊。
作为本发明的进一步改进，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路和/或电源管理芯片和/或被动器件。
本发明还提供一种天线封装结构的封装方法，其特征在于，包括步骤：
提供一临时载板，在所述临时载板上设置第一天线层和互连结构件，所述第一天线层以介电损耗正切值小于0.01的介电材料的作为层间介质；
于所述第一天线层上贴附介电损耗正切值小于0.01的天线支撑件；
将至少一层第二天线层，至少一层天线控制层和至少一层芯片线路层形成预制基板层单粒或板条，并电学键合所述第一天线层上的所述互连结构件，所述第二天线层以介电损耗正切值小于0.01的介电材料的作为层间介质；
填充第一塑封层包覆所述基板层、所述互连结构件、所述天线支撑件和所述第一天线层；
去除所述临时载板，于所述芯片线路层上设置互连结构件和至少一个芯片，并进行第二塑封层，切割形成单块天线封装结构。
作为本发明的进一步改进，所述天线支撑件为有机单层或多层复合基板，塑封层，玻璃件和低温共烧陶瓷件中的一种或多种，天线支撑件可以是纯介电件，或除第一天线层外其余5侧面带金属的共振腔。
作为本发明的进一步改进，所述第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
作为本发明的进一步改进，所述芯片线路层包括天线信号控制线路和天线信号发送接收线路。
作为本发明的进一步改进，于所述第二天线层上的互连结构件为导电金属柱。
作为本发明的进一步改进，所述互连结构件包括由介电材料构成主体件，以及位于所述主体件内部连通其上下表面的金属连接件，所述金属连接件与所述基板层上的线路层电性连接。
作为本发明的进一步改进，设于所述第二天线层一侧的所述互连结构件分布于所述天线支撑件内空隙之间及其周侧，且所述互连结构件上表面低于所述第一天线层上表面。
作为本发明的进一步改进，所述互连结构件位于所述封装结构两侧的部分还设有侧向天线层，所述侧向天线层朝向所述天线封装结构侧边缘设置。
作为本发明的进一步改进，所述互连结构件的侧壁设有散热结构件和/或第二阻湿层，所述第二阻湿层暴露于所述塑封层。
作为本发明的进一步改进，还包括步骤：
于所述天线封装结构外侧依次沉积粘结层，主屏蔽层和保护层来形成电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层。
作为本发明的进一步改进，于所述电磁屏蔽层上形成暴露所述互连结构件的通孔，于所述通孔内填充烧结导电膏或锡焊。
作为本发明的进一步改进，还包括步骤：
于所述天线封装结构外侧形成第一阻湿层，所述第一阻湿层至少包覆所述第一天线层、所述天线支撑件和所述第二天线层。
作为本发明的进一步改进，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路、电源管理芯片和被动器件。
本发明的有益效果是：本发明将天线和芯片分设于基板层两侧，天线层由天线支撑件、位于天线支撑件上方的第一天线层和位于天线支撑件下方的第二天线层共同构成，天线支撑件和天线层层间介质采用低介电损耗材料，从而形成异质异构的天线结构，以减少因介电损耗带来的封装结构内电流泄漏、杂散电容等问题，并减小天线封装结构的尺寸。
附图说明
图1是本发明一实施方式中的天线封装结构示意图。
图2是本发明另一实施方式中的天线封装结构示意图。
图3是本发明另一实施方式中的天线封装结构中基板层和天线层的示意图，其互连结构件位于封装结构两侧的部分设有侧向天线层。
图4是本发明另一实施方式中的天线封装结构中基板层和天线层的示意图，其省略天线支撑件。
图5是是本发明一实施方式中的天线封装结构制造流程图。
图6至图11是本发明一实施方式中的天线封装结构制造流程各步骤示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施方式及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施方式仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
下面详细描述本发明的实施方式，实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
为方便说明，本文使用表示空间相对位置的术语来进行描述，例如“上”、“下”、“后”、“前”等，用来描述附图中所示的一个单元或者特征相对于另一个单元或特征的关系。空间相对位置的术语可以包括设备在使用或工作中除了图中所示方位以外的不同方位。例如，如果将图中的装置翻转，则被描述为位于其他单元或特征“下方”或“上方”的单元将位于其他单元或特征“下方”或“上方”。因此，示例性术语“下方”可以囊括下方和上方这两种空间方位。
如图1所示，本发明提供一种天线封装结构，天线封装结构包括：基板层1、天线支撑件2、第一天线层3、互连结构件6、塑封层4和至少一个芯片5。
所述基板层包括依次堆叠设置的芯片线路层11、天线控制层12和至少一层第二天线层13，所述第一天线层11和所述第二天线层13层间介质的介电损耗正切值小于0.01，基板层1为另外预制。
天线控制层12包括天线信号控制线路和天线信号发送接收线路。
具体的，在本实施方式中，第二天线层13层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料，通过选用具有低介电常数和低介电损耗的材料作为第二天线层13的层间介质材料，可以减少天线电路内的介电损耗和容抗，从而减少因介电损耗带来的电流泄漏、杂散电容等问题。
第一天线层3通过互连结构件6电性连接于第二天线层13。
天线支撑件2贴合于第一天线层3朝向第二天线层13的一侧，其介电损耗正切值小于0.01。
进一步的，在本实施方式中，设于第二天线层13一侧的互连结构件6为导电金属柱6a，如铜柱等，通过铜核或塑核焊球等电性连接于基板层1。
设于芯片线路层11一侧的互连结构件6为复合结构件6b，复合结构件6b包括 由介电材料构成主体件61，以及位于主体件61内部连通其上下表面的导电通孔62或叠孔，导电通孔62内设有金属连接件或导电填料以与接地线路层电性连接。
主体件61的上表面和下表面镀覆有金属层，复合结构件6b通过焊锡，或导电胶/膏电性连接于线路层。
更进一步的，主体件61也为具有低介电损耗的有机复合基板，玻璃件和低温共烧陶瓷件，以进一步降低封装结构内的介电损耗，或者主体件61也可采用带无机填料的有机高分子树脂，或带玻纤布与填料有机高分子树脂，合成树脂等具有一定结构强度的聚合物材料。
复合结构件6b的侧壁设有散热结构件63和/或第二阻湿层64，第二阻湿层64暴露于或埋入于塑封层4，散热机构件63为诸如铜柱等由具有高热导材料制成柱状或薄层状结构件。从而进一步提高封装结构在高温和高湿条件下的可靠性。
如图2所示，在本发明的另一些实施方式中，于第二天线层13和芯片线路层11上均设有复合结构件6b，设于第二天线层13一侧的复合结构件6b分布于天线支撑件2内空隙之间及其周侧，以使封装结构内的空间得到最大化有效利用。
当然，互连结构件6的结构及分布位置并不限于此，只要能够起到电性连接作用即可。
进一步的，在本发明一些实施方式中，天线支撑件2和互连结构件6周侧设有预塑封层43。
如图3所示，在本发明的一些其他实施方式中，互连结构件6位于封装结构两侧的部分还设有侧向天线层65，侧向天线层65朝向天线封装结构侧边缘设置，互连结构件6内设有电性连通侧向天线层65与天线控制层12的线路或导电连接件。
天线支撑件2采用低介电损耗的材料，使得天线线路形成异质异构的分体式结构，天线支撑件2作为天线线路的主体件61可以减小电路内的介电损耗。
具体的，天线支撑件2的形状可以根据第一天线层3的平面排布形状以及第一天线层3中天线模块的数量而具体设置，天线支撑件2的水平面轮廓形状大致类似于第一天线层3天线线路的平面排布形状，从而可以使具有低介电损耗的天线支撑件2对第一天线起到良好支撑作用的同时，减少其在封装结构内所占用的空间。
更进一步的，天线支撑件2为有机复合基板，玻璃件和低温共烧陶瓷件中的一种或多种，有机复合板和玻璃件在具有低介电损耗的同时具有低的介电常数，低温共烧陶瓷在具有低介电损耗的同时具有高的介电常数。天线支撑件2为纯介电件，或为除与第一天线层3相接面外其余五个侧面设有金属的共振腔。在保证介电损耗 较低的情况下，通过使用具有不同介电常数的天线支撑件2，使得封装结构能够适用于具有不同使用条件的芯片5，满足封装结构高密度集成化的需求。
天线支撑件2通过芯片膜或粘结膏等材料贴合于第一天线层3，芯片膜或粘结膏可以覆盖第一天线层3的全表面，或部分延伸至互连结构件6上。
芯片5设于芯片线路层11上，即芯片5与天线层分设于基板层1的相对两个表面上。将天线层与芯片5分设于基板层1两侧，一方面，使得基板层1上的线路层可以实现分层布置，将芯片5和芯片线路层11设在一侧，将天线控制线路层和天线层设在一侧，便于在基板层1上依次分别进行布线设计；另一方面，可以减少天线层对芯片5的信号干扰。
如图4所示，在本发明的一些实施方式中，也可省略设于天线侧的天线支撑件2，只通过互联结构件6将第一天线层3和第二天线层13连接。
塑封层4包覆基板层1、天线支撑件2、第一天线层3和芯片5。塑封层4由塑封料填充而成，塑封料可以为环氧树脂、聚酰亚胺、干膜等带填料的高分子聚合物复合材料，塑封层4为封装结构提供物理支撑，并对封装结构内元件起到保护作用。
进一步的，在本实施方式中，塑封层4包括第一塑封层41和/或第二塑封层42，第一塑封层41包覆基板层1、天线支撑件2和第一天线层3，第二塑封层42包覆芯片5。第一塑封层41和第二塑封层42采用不同的塑封料，从而可以利用不同塑封料的热膨胀系数差异来调整封装结构的翘曲问题。在另外的实施方法中，第一或第二塑封也可以同时包覆基板层1、天线支撑件2和第一天线层3，芯片5和互连结构件6。
需要说明的是，根据制造工艺流程步骤顺序的差异，第一塑封层41和第二塑封层42分别包覆的器件存在差别，如第一塑封层41包覆天线支撑件2和第一天线层3，第二塑封层42包覆基板层1和芯片5。
在本发明的一些实施方式中，所述天线封装结构于塑封层4外侧还设有第一阻湿层7，所述第一阻湿层7至少包覆所述第一天线层3、所述天线支撑件6和所述第二天线层13，从而进一步提高封装结构在高湿条件下的可靠性。
在本发明的一些实施方式中，芯片5和芯片线路层11之间还设有底填料51。
在本发明的一些实施方式中，天线封装结构还包括设于芯片线路层11上的微波集成电路和/或电源管理芯片和/或被动器件。被动器件包括诸如电容、电阻等，或者其他诸如散热片、加强筋等功能器件。
在本发明的一些实施方式中，天线封装结构于封装层外侧还设有电磁屏蔽层8， 电磁屏蔽层8至少覆盖芯片5和芯片线路层11，以减少芯片5所受到的电磁波干扰。
具体的，电磁屏蔽层8包括：贴合于塑封层4的粘结层，暴露于空气的保护层，以及设于粘结层和保护层之间的主屏蔽层。粘结层为铜等具有较高粘附性的金属材料，或为具有高粘附性的有机材料，以加强电磁屏蔽层8和封装结构之间的结合强度。主屏蔽层是诸如铜，不锈钢，钛等溅射夹层金属薄膜材料，或诸如含银/铜之类高密度金属填料的导电树脂等导电复合材料，或是上述材料中至少两种的组合，能够起到屏蔽或吸收电磁波的作用即可。防护层为不锈钢(7％NiV)或CrCu合金层，或有机阻湿层等，以进一步加强封装结构在高湿条件下的可靠性。
进一步的，互连结构件6侧壁设有金属结构件，金属结构件暴露于塑封层4与电磁屏蔽层8电性连接。
更进一步的，电磁屏蔽层8上设有暴露所述金属结构件的通孔81，通孔81内填充有烧结导电膏或锡焊，以加强电磁屏蔽层的接地连接。
根据制造流程中工艺步骤顺序的差异，电磁屏蔽层8所覆盖的部分水平切割面位置存在差异。
如图5所示，本发明还提供一种天线封装结构的封装方法，包括步骤：
S1：如图6所示，提供一带可选的临时键合层的临时载板9，在临时载板9上设置第一天线层3和互连结构件6，第一天线层3以介电损耗正切值小于0.01的介电材料的作为层间介质。
临时载板9为诸如玻璃，硅，复合聚合物等低成本，具有一定刚性的牺牲基材，以用于结构支撑。
具体的，在本实施方式中，第一天线层3层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
进一步的，在本实施方式中，互连结构件6为导电金属柱，如圆柱形和长方体形铜柱等。
在本发明的另一些实施方式中，互连结构件6包括由介电材料构成主体件61，以及位于主体件61内部连通其上下表面的金属连接件，金属连接件与基板层1上的接地线路层电性连接。
主体件61的上表面和下表面镀覆有金属层，互连结构件6通过焊锡，或导电胶/膏电性连接于接地线路层。
进一步的，主体件61为具有低介电损耗的有机复合基板，玻璃件和低温共烧陶瓷件，以进一步降低封装结构内的介电损耗，或者主体件61也可采用带无机填料的 有机高分子树脂，或带玻纤布与填料有机高分子树脂，合成树脂等具有一定结构强度的聚合物材料。
在本发明的一些其他实施方式中，互连结构件6位于封装结构两侧的部分还设有侧向天线层65，侧向天线层65朝向天线封装结构侧边缘设置。
在本发明的一些其他实施方式中，互连结构件6的侧壁设有散热结构件63和/或第二阻湿层64，第二阻湿层64暴露于或埋入于塑封层4。
S2：如图7所示，于第一天线层3上贴附介电损耗正切值小于0.01的天线支撑件2。
具体的，在本实施方式中，天线支撑件2为有机单层或多层复合基板，塑封件，玻璃件和低温共烧陶瓷件中的一种或多种。天线支撑件2为纯介电件，或为除与第一天线层3相接面外其余五个侧面设有金属的共振腔。
天线支撑件2通过膜或粘结膏等材料贴合于第一天线层3。
互连结构件6分布于天线支撑件2内空隙之间及其周侧。
S3：如图8所示，将至少一层的第二天线层13，天线控制层12和芯片线路层11所形成的预制基板层1设于所述互连结构件6之上，所述第二天线层13以介电损耗正切值小于0.01的介电材料的作为层间介质。在另外一种实施方式中，预制基板层1可以预先键合好芯片和互连结构件6，然后再一起设于所述互连结构件6之上锡焊回流键合，基板层1上可预键合带铜核/塑核的锡球和/或常规的SnAgCu球。
进一步的，天线控制层12包括天线信号控制线路和天线信号发送接收线路。
具体的，在本实施方式中，第二天线层13层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
S4：如图9所示，填充第一塑封层41的塑封料包覆基板层1、互连结构件6、天线支撑件2和第一天线层3。第一塑封层41可以在塑封时不覆盖基板层1的芯片面，也可以先覆盖基板层1的芯片面，再随之减薄第一塑封层41以露出基板层1芯片面的焊盘。
采用诸如带无机填料的有机高分子树脂，或带玻纤布与填料的有机高分子树脂，或环氧树脂、聚酰亚胺、干膜等带填料的聚合物复合材料作为塑封料沉积在基板层1之上，包封互联结构件、天线支撑件2和第一天线层3形成第一塑封层41。
在本发明一些其他实施方式中，再填充塑封料之前，还包括步骤：
S5：如图10和图11所示，去除临时载板9，于芯片线路层11上设置互连结构件6和至少一个芯片5，并进行第二塑封层42，切割形成单块天线封装结构。临时 载板9也可以在第二塑封层42之后去除。
通过激光解键分离，机械剥离、化学蚀刻、机械研磨等方法将临时载板9剥离。
通过锯片或激光切割装置沿切割道将完整的封装结构分成单独的封装结构。
进一步的，在本发明的一些实施方式中，对芯片5进行塑封之前还包括步骤：
于芯片5和芯片线路层11之间涂设底填料51。
进一步的，在本发明的一些实施方式中，设置芯片5同时还包括步骤：
于芯片线路层11上设置微波集成电路和/或电源管理芯片和/或被动器件。被动器件包括诸如电容、电阻等，或者其他诸如散热片、加强筋等功能器件。
在本发明的一些实施方式中，切割形成单颗天线封装体之前，还包括步骤：
部分切割塑封层；
于天线封装结构外侧依次沉积粘结层，主屏蔽层和保护层来形成电磁屏蔽层8，电磁屏蔽层8至少覆盖芯片5和芯片线路层11；
于电磁屏蔽层8上形成暴露所述金属结构件的通孔81，并于通孔81内填充烧结导电膏或锡焊。
具体的，电磁屏蔽层8包括：贴合于塑封层4的粘结层，暴露于空气的保护层，以及设于粘结层和保护层之间的主屏蔽层。粘结层为铜等具有较高粘附性的金属材料，或为具有高粘附性的有机材料度。主屏蔽层是诸如铜，不锈钢，钛等溅射夹层金属薄膜材料，或诸如含银/铜之类高密度金属填料的导电树脂等导电复合材料，或是上述材料中至少两种的组合。防护层为不锈钢，NiV(7％)或CrCu合金层，或有机阻湿层等。电磁屏蔽层8也可以在完全切割之后形成。
在本发明的一些实施方式中，切割形成单颗天线封装体之前或之后，还包括步骤：
于所述天线封装结构外侧形成第一阻湿层7，第一阻湿7层至少包覆第一天线层3、天线支撑件2和第二天线层13。
需要说明的是，本发明中的部分步骤顺序可以进行交换调整，如也可先于临时载板9上先设置芯片5和基板层2，之后再去除临时载板9，形成天线支撑件2和天线层等，只要能够形成相对分布的芯片和天线层封装结构结构即可。
综上所述，本发明将天线和芯片分设于基板层两侧，天线层由天线支撑件、位于天线支撑件上方的第一天线层和位于天线支撑件下方的第二天线层共同构成，天线支撑件和天线层层间介质采用低介电损耗材料，从而形成异质异构的天线结构，以减少因介电损耗带来的封装结构内电流泄漏、杂散电容等问题，并减小天线封装 结构的尺寸。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (29)

  1. 一种天线封装结构，其特征在于，
    所述天线封装结构包括：基板层、互连结构件、天线支撑件、第一天线层、芯片和塑封层；
    所述基板层包括依次堆叠设置的至少一层芯片线路层、至少一层天线控制层和至少一层第二天线层，所述第一天线层和所述第二天线层层间介质的介电损耗正切值小于0.01；
    所述第一天线层通过互连结构件电性连接于所述第二天线层；
    所述天线支撑件贴合于所述第一天线层朝向所述第二天线层的一侧，其介电损耗正切值小于0.01；
    所述芯片相对于所述第一天线层，设于所述控制线路层上；
    所述塑封层包覆所述基板层、所述天线支撑件、所述第一天线层、所述互连结构件和所述芯片。
  2. 根据权利要求1所述的天线封装结构，其特征在于，所述天线支撑件为单层或多层有机复合基板，塑封件，玻璃件和低温共烧陶瓷件中的一种或多种。
  3. 根据权利要求2所述的天线封装结构，其特征在于，所述天线支撑件为纯介电件，或为除与所述第一天线层相接面外其余五个侧面设有金属的共振腔。
  4. 根据权利要求3所述的天线封装结构，其特征在于，所述第一天线层和第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
  5. 根据权利要求4所述的天线封装结构，其特征在于，所述天线控制层包括天线信号控制线路和天线信号发送接收线路。
  6. 根据权利要求3所述的天线封装结构，其特征在于，所述天线封装结构于塑封层外侧还设有第一阻湿层，所述第一阻湿层至少包覆所述第一天线层、所述天线支撑件和所述第二天线层。
  7. 根据权利要求1所述的天线封装结构，其特征在于，所述天线封装结构还包括设于所述第二天线层和设于所述芯片线路层上的互连结构件，所述互连结构件电性连接于所述基板层线路。
  8. 根据权利要求7所述的天线封装结构，其特征在于，所述互连结构件为导电金属柱和/或复合结构件。
  9. 根据权利要求8所述的天线封装结构，其特征在于，所述复合结构件包括由介 电材料构成主体件，以及位于所述主体件内部连通其上下表面的导电通孔，所述导电通孔内设有金属连接件或导电填料以与线路层电性连接，设于所述第二天线层一侧的所述复合结构件分布于所述天线支撑件内空隙之间及其周侧。
  10. 根据权利要求9所述的天线封装结构，其特征在于，所述互连结构件位于所述封装结构两侧的部分还设有侧向天线层，所述侧向天线层朝向所述天线封装结构侧边缘设置。
  11. 根据权利要求9所述的天线封装结构，其特征在于，所述互连结构件的侧壁设有散热结构件和/或第二阻湿层，所述第二阻湿层暴露于或埋入于所述塑封层。
  12. 根据权利要求7、8或9所述的天线封装结构，其特征在于，所述天线支撑件和所述互连结构件周侧设有预塑封层。
  13. 根据权利要求12所述的天线封装结构，其特征在于，所述塑封层包括第一塑封层和第二塑封层，所述第一塑封层至少包覆所述基板层上表面、所述天线支撑件侧面，所述互连结构件侧面和所述第一天线层，所述第二塑封层至少包覆所述芯片侧面和互连结构件侧面，所述第一塑封层和所述第二塑封层材料相异。
  14. 根据权利要求2所述的天线封装结构，其特征在于，所述天线封装结构于塑封层外侧还设有电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层的侧向，所述电磁屏蔽层包括：贴合于所述塑封层的粘结层，暴露于空气的保护层，以及设于所述粘结层和所述保护层之间的主屏蔽层，所述互连结构件侧壁设有金属结构件，所述金属结构件暴露于所述塑封层与所述电磁屏蔽层电性接地连接。
  15. 根据权利要求14所述的天线封装结构，其特征在于，所述电磁屏蔽层上设有暴露所述金属结构件的通孔，所述通孔内填充有烧结导电膏或锡焊。
  16. 根据权利要求1所述的天线封装结构，其特征在于，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路和/或电源管理芯片和/或被动器件。
  17. 一种天线封装结构的封装方法，其特征在于，包括步骤：
    提供一临时载板，在所述临时载板上设置第一天线层和互连结构件，所述第一天线层以介电损耗正切值小于0.01的介电材料的作为层间介质；
    于所述第一天线层上贴附介电损耗正切值小于0.01的天线支撑件；
    将至少一层第二天线层，至少一层天线控制层和至少一层芯片线路层形成预制基板层单粒或板条，并电学键合所述第一天线层上的所述互连结构件，所述第二天线层以介电损耗正切值小于0.01的介电材料的作为层间介质；
    填充第一塑封层包覆所述基板层、所述互连结构件、所述天线支撑件和所述第 一天线层；
    去除所述临时载板，于所述芯片线路层上设置互连结构件和至少一个芯片，并进行第二塑封层，切割形成单块天线封装结构。
  18. 根据权利要求17所述的封装方法，其特征在于，所述天线支撑件为有机单层或多层复合基板，塑封层，玻璃件和低温共烧陶瓷件中的一种或多种，天线支撑件2可以是纯介电件，或除第一天线层3外其余5侧面带金属的共振腔。
  19. 根据权利要求18所述的封装方法，其特征在于，所述第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
  20. 根据权利要求17所述的封装方法，其特征在于，所述芯片线路层包括天线信号控制线路和天线信号发送接收线路。
  21. 根据权利要求17所述的封装方法，其特征在于，于所述第二天线层上的互连结构件为导电金属柱。
  22. 根据权利要求17所述的封装方法，其特征在于，所述互连结构件包括由介电材料构成主体件，以及位于所述主体件内部连通其上下表面的金属连接件，所述金属连接件与所述基板层上的线路层电性连接。
  23. 根据权利要求22所述的封装方法，其特征在于，设于所述第二天线层一侧的所述互连结构件分布于所述天线支撑件内空隙之间及其周侧，且所述互连结构件上表面低于所述第一天线层上表面。
  24. 根据权利要求23所述的封装方法，其特征在于，所述互连结构件位于所述封装结构两侧的部分还设有侧向天线层，所述侧向天线层朝向所述天线封装结构侧边缘设置。
  25. 根据权利要求22所述的封装方法，其特征在于，所述互连结构件的侧壁设有散热结构件和/或第二阻湿层，所述第二阻湿层暴露于所述塑封层。
  26. 根据权利要求17所述的封装方法，其特征在于，还包括步骤：
    于所述天线封装结构外侧依次沉积粘结层，主屏蔽层和保护层来形成电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层。
  27. 根据权利要求26所述的封装方法，其特征在于，于所述电磁屏蔽层上形成暴露所述互连结构件的通孔，于所述通孔内填充烧结导电膏或锡焊。
  28. 根据权利要求17所述的封装方法，其特征在于，还包括步骤：
    于所述天线封装结构外侧形成第一阻湿层，所述第一阻湿层至少包覆所述第一天线层、所述天线支撑件和所述第二天线层。
  29. 根据权利要求17所述的封装方法，其特征在于，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路、电源管理芯片和被动器件。
PCT/CN2021/094566 2020-11-17 2021-05-19 天线封装结构及天线封装结构制造方法 WO2022105161A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/035,520 US20230411826A1 (en) 2020-11-17 2021-05-19 Antenna packaging structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011284065.5A CN114512789A (zh) 2020-11-17 2020-11-17 天线封装结构及天线封装结构制造方法
CN202011284065.5 2020-11-17

Publications (1)

Publication Number Publication Date
WO2022105161A1 true WO2022105161A1 (zh) 2022-05-27

Family

ID=81546611

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/094566 WO2022105161A1 (zh) 2020-11-17 2021-05-19 天线封装结构及天线封装结构制造方法

Country Status (3)

Country Link
US (1) US20230411826A1 (zh)
CN (1) CN114512789A (zh)
WO (1) WO2022105161A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116995068A (zh) * 2023-09-25 2023-11-03 之江实验室 芯片集成天线封装结构及封装方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113125859B (zh) * 2021-03-10 2023-02-03 青岛歌尔智能传感器有限公司 一种用于测试屏蔽效能的封装结构和屏蔽效能的测试方法
CN117497532B (zh) * 2024-01-02 2024-04-09 成都雷电微力科技股份有限公司 一种aip三维堆叠tr气密封装组件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107342233A (zh) * 2017-06-29 2017-11-10 江苏长电科技股份有限公司 低损耗部件埋入式天线封装结构及其制造方法
CN108538794A (zh) * 2018-03-26 2018-09-14 江苏长电科技股份有限公司 表面贴装型封装结构及其制作方法
CN209515978U (zh) * 2019-04-02 2019-10-18 中芯长电半导体（江阴）有限公司 天线封装结构
CN210182380U (zh) * 2019-06-04 2020-03-24 中芯长电半导体（江阴）有限公司 半导体封装结构
US20200328518A1 (en) * 2019-04-11 2020-10-15 Samsung Electro-Mechanics Co., Ltd. Chip antenna module and electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107342233A (zh) * 2017-06-29 2017-11-10 江苏长电科技股份有限公司 低损耗部件埋入式天线封装结构及其制造方法
CN108538794A (zh) * 2018-03-26 2018-09-14 江苏长电科技股份有限公司 表面贴装型封装结构及其制作方法
CN209515978U (zh) * 2019-04-02 2019-10-18 中芯长电半导体（江阴）有限公司 天线封装结构
US20200328518A1 (en) * 2019-04-11 2020-10-15 Samsung Electro-Mechanics Co., Ltd. Chip antenna module and electronic device
CN210182380U (zh) * 2019-06-04 2020-03-24 中芯长电半导体（江阴）有限公司 半导体封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116995068A (zh) * 2023-09-25 2023-11-03 之江实验室 芯片集成天线封装结构及封装方法
CN116995068B (zh) * 2023-09-25 2024-01-09 之江实验室 芯片集成天线封装结构及封装方法

Also Published As

Publication number Publication date
CN114512789A (zh) 2022-05-17
US20230411826A1 (en) 2023-12-21

Similar Documents

Publication Publication Date Title
WO2022105161A1 (zh) 天线封装结构及天线封装结构制造方法
WO2022105160A1 (zh) 天线封装结构及天线封装结构制造方法
US9548279B2 (en) Connection member, semiconductor device, and stacked structure
JP5773082B2 (ja) モジュール
TWI559443B (zh) 具有柱型互連接件之積體電路封裝系統及其製造方法
US20070053167A1 (en) Electronic circuit module and manufacturing method thereof
KR20140057979A (ko) 반도체 패키지 및 반도체 패키지의 제조 방법
US20220254695A1 (en) Embedded package structure and preparation method therefor, and terminal
US20230163114A1 (en) Three-dimensional fan-out integrated package structure, packaging method thereof, and wireless headset
CN107424987B (zh) 堆叠式半导体结构及其制造方法
US20190198972A1 (en) Semiconductor package structure having antenna module
US20230011464A1 (en) Wiring structure and method for manufacturing the same
CN100472780C (zh) 电子零部件及其制造方法
CN109904128B (zh) 基于硅基载板的三维集成t/r组件封装结构及封装方法
CN112349691A (zh) 一种气密高导热lcp封装基板、制造方法及多芯片系统级封装结构
CN112349700A (zh) 一种气密高导热lcp封装基板及多芯片系统级封装结构
CN112349698B (zh) 一种lcp封装基板、制造方法及多芯片系统级封装结构
KR101741648B1 (ko) 전자파 차폐 수단을 갖는 반도체 패키지 및 그 제조 방법
US11784625B2 (en) Packaging method and package structure for filter chip
WO2018098648A1 (zh) 集成电路封装方法以及集成封装电路
WO2021008228A1 (zh) Sip封装结构
TW201832298A (zh) 電子封裝構件及其製作方法
CN112349696A (zh) 一种lcp封装基板、制造方法及多芯片系统级封装结构
WO2022037147A1 (zh) 扇出型封装结构及其制造方法
CN215266271U (zh) 基于铜箔载板的正反面芯片集成封装结构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21893317

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 18035520

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21893317

Country of ref document: EP

Kind code of ref document: A1