WO2022105160A1 - 天线封装结构及天线封装结构制造方法 - Google Patents

天线封装结构及天线封装结构制造方法 Download PDF

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Publication number
WO2022105160A1
WO2022105160A1 PCT/CN2021/094565 CN2021094565W WO2022105160A1 WO 2022105160 A1 WO2022105160 A1 WO 2022105160A1 CN 2021094565 W CN2021094565 W CN 2021094565W WO 2022105160 A1 WO2022105160 A1 WO 2022105160A1
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WO
WIPO (PCT)
Prior art keywords
layer
antenna
chip
packaging
plastic
Prior art date
Application number
PCT/CN2021/094565
Other languages
English (en)
French (fr)
Inventor
林耀剑
徐晨
刘硕
何晨烨
Original Assignee
江苏长电科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 江苏长电科技股份有限公司 filed Critical 江苏长电科技股份有限公司
Priority to US18/035,514 priority Critical patent/US20230335882A1/en
Publication of WO2022105160A1 publication Critical patent/WO2022105160A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/40—Radiating elements coated with or embedded in protective material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/52—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
    • H01Q1/526—Electromagnetic shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0006—Particular feeding systems
    • H01Q21/0075—Stripline fed arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/0414—Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration

Definitions

  • the present invention relates to the technical field of packaging, in particular to an antenna packaging structure and a method for manufacturing the antenna packaging structure.
  • wireless communication equipment usually includes an antenna module and one or more integrated circuit.
  • Antenna modules and integrated circuits can be arranged in several different ways (eg, antenna-in-package (AIP), antenna-on-package (AOP), antenna-on-chip (AOC), etc.).
  • the electrical signal between the antenna module and the integrated circuit usually needs to be transmitted through one or more conductive lines and/or one or more through-holes, which are made or filled with conductive materials and which are in contact with dielectric materials.
  • Contacting and/or being at least partially surrounded by a dielectric material is prone to problems such as current leakage, stray capacitance, etc. due to the relatively high dielectric losses of conventional dielectric materials such as silicon or molding compounds.
  • the reliability of the package structure under conditions such as high temperature and high pressure is poor and is not conducive to the miniaturization of the package structure.
  • the purpose of the present invention is to provide an antenna package structure and a method for manufacturing the antenna package structure.
  • the present invention provides an antenna packaging structure, which comprises: a substrate layer, at least one antenna support, a first antenna layer, a plastic packaging layer and at least one chip;
  • the substrate layer includes at least one layer of chip circuit layers, at least one layer of antenna control layer and at least one layer of second antenna layer which are stacked in sequence, and the dielectric loss tangent value of the interlayer medium of the second antenna layers is less than 0.01;
  • the antenna support is arranged on the second antenna layer, and its dielectric loss tangent is less than 0.01;
  • the first antenna layer is disposed on the antenna support, and is electrically connected with the second antenna layer through electromagnetic radiation or physical contact;
  • the chip is arranged on the chip circuit layer relative to the antenna support;
  • the plastic packaging layer covers the substrate layer, the antenna support, the first antenna layer and the chip.
  • the antenna support member is one or more of an organic composite substrate, a glass member and a low-temperature co-fired ceramic member.
  • At least the interlayer dielectric material of the second antenna layer is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with filler.
  • the antenna control layer includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • the upper surface of the antenna support is further provided with a first moisture-blocking layer, the first moisture-blocking layer covers the first antenna layer, and is exposed or buried in the plastic encapsulation layer .
  • the antenna package structure further includes an interconnection structure member disposed on the second antenna layer and/or the chip circuit layer, and the interconnection structure member on the second antenna layer at least The interconnection structure on the chip circuit layer is electrically connected to the substrate layer.
  • the interconnecting structural member includes a main body member made of a dielectric material, and a conductive hole at least located inside the main body member and communicated with the upper and lower surfaces thereof, and the conductive hole is provided with a metal connection member or a conductive hole
  • the filler is electrically connected to at least the grounding circuit layer, and the interconnecting structural members disposed on one side of the second antenna layer are distributed between the voids in the antenna support member and on the peripheral side thereof.
  • the parts of the interconnection structure located on both sides of the package structure may further be provided with lateral antenna layers, and the lateral antenna layers are disposed toward the side edges of the antenna package structure.
  • the sidewall of the interconnect structure is provided with a heat dissipation structure and/or a second moisture barrier layer, and the second moisture barrier layer is exposed or buried outside the plastic encapsulation layer.
  • the plastic encapsulation layer includes a first plastic encapsulation layer and a second plastic encapsulation layer, and the first plastic encapsulation layer at least covers the upper surface of the substrate layer, the side surface of the antenna support, and the interconnection structure.
  • the side surface of the component and the first antenna layer, the second plastic packaging layer at least covers the side surface of the chip and the side surface of the interconnect structure component, and the materials of the first plastic packaging layer and the second plastic packaging layer are different.
  • the antenna encapsulation structure is further provided with an electromagnetic shielding layer outside the plastic encapsulation layer, the electromagnetic shielding layer at least covers the chip and the lateral direction of the chip circuit layer, and the electromagnetic shielding layer includes: On the adhesive layer of the plastic encapsulation layer, the protective layer exposed to the air, and the main shielding layer arranged between the adhesive layer and the protective layer, the side walls of the interconnecting structural members are provided with metal structural members , the metal structure is exposed to the plastic encapsulation layer and is electrically connected to the electromagnetic shielding layer, and a part of the electromagnetic shielding layer forms a pad on the back of the chip or the plastic encapsulation layer through the opening is connected to the electromagnetic shielding layer. The backside of the chip is bonded to form a pad.
  • the antenna package structure further includes a microwave integrated circuit and/or a power management chip and/or a passive device disposed on the chip circuit layer.
  • the present invention also provides a packaging method for the antenna packaging structure, comprising the steps of:
  • a temporary carrier board is provided, on which a chip circuit layer, an antenna control layer, and at least one second antenna layer located on the antenna control layer are arranged to form a substrate layer, and the second antenna layer is formed by intervening Dielectric materials with electrical loss tangent less than 0.01 are used as interlayer dielectrics;
  • an interconnection structure is arranged on the substrate layer, and the interconnection structure is electrically connected to the ground circuit layer on the substrate layer;
  • At least one antenna support member with a dielectric loss tangent value less than 0.01 is arranged on the second antenna layer, and a first antenna layer is arranged on the antenna support member;
  • the temporary carrier is removed, an interconnection structure and at least one chip are arranged on the chip circuit layer, a second plastic packaging layer is formed by filling, and a single-piece antenna packaging structure is formed by cutting.
  • the antenna support member is one or more of an organic composite substrate, a glass member and a low-temperature co-fired ceramic member.
  • the first plastic encapsulation layer at least covers the upper surface of the substrate layer, the side surface of the antenna support, the side surface of the interconnection structure and the first antenna layer, and the second plastic encapsulation The layer covers at least the side surface of the chip and the side surface of the interconnect structure, and the materials of the first plastic packaging layer and the second plastic packaging layer are different.
  • At least the interlayer dielectric material of the second antenna layer is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with filler.
  • the chip circuit layer includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • a first moisture-blocking layer is formed on the upper surface of the antenna support member, and the first moisture-blocking layer covers the first antenna layer.
  • the interconnecting structural member includes a main body member made of a dielectric material, and a metal connection member at least located inside the main body member and communicated with the upper and lower surfaces thereof, the metal connection member is at least connected to the substrate layer
  • the ground circuit layer is electrically connected.
  • the interconnecting structural members disposed on one side of the second antenna layer are distributed between the voids in the antenna support member and on the peripheral side thereof.
  • the parts of the interconnection structure located on both sides of the package structure may further be provided with lateral antenna layers, and the lateral antenna layers are disposed toward the side edges of the antenna package structure.
  • the sidewall of the interconnect structure is provided with a heat dissipation structure and/or a second moisture barrier layer, and the second moisture barrier layer is exposed or buried in the plastic encapsulation layer.
  • An adhesive layer, a main shielding layer and a protective layer are sequentially deposited on the outside of the antenna packaging structure to form an electromagnetic shielding layer, and the electromagnetic shielding layer at least covers the chip and the chip circuit layer.
  • the antenna package structure further includes a microwave integrated circuit, a power management chip and a passive device disposed on the chip circuit layer.
  • the present invention separates the antenna and the chip on both sides of the substrate layer, and the antenna layer is composed of the antenna support, the first antenna layer above the antenna support, and the second antenna layer below the antenna support , the antenna support and the interlayer medium of the antenna are made of low dielectric loss materials, so as to form a heterogeneous antenna structure, so as to reduce the current leakage and stray capacitance in the package structure caused by dielectric loss, and reduce The size of the small antenna package structure.
  • FIG. 1 is a schematic diagram of an antenna package structure in an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a substrate layer and an antenna layer in an antenna package structure according to another embodiment of the present invention, wherein the upper surface of the interconnection structure is higher than the upper surface of the first antenna layer.
  • FIG 3 is a schematic diagram of a substrate layer and an antenna layer in an antenna packaging structure according to another embodiment of the present invention, and a first moisture-blocking layer is further provided on the upper surface of the antenna support member.
  • FIG. 4 is a schematic diagram of an antenna package structure in another embodiment of the present invention, and a lateral antenna layer is provided on the part of the interconnect structure on both sides of the package structure.
  • FIG. 5 is a schematic diagram of a substrate layer and an antenna layer in an antenna packaging structure according to another embodiment of the present invention, and the interconnection structure is a complete block structure.
  • FIG. 6 is a schematic diagram of a substrate layer and an antenna layer in an antenna package structure according to another embodiment of the present invention, and the interconnection structure is integrated in the antenna support.
  • FIG. 7 is a schematic diagram of the structure of an antenna package in another embodiment of the present invention, which is provided with an inter-board connector.
  • FIGS 8 and 9 are schematic diagrams of an antenna packaging structure in another embodiment of the invention, and an electromagnetic shielding layer is further provided outside the packaging layer.
  • FIG. 10 is a manufacturing flow chart of an antenna package structure in an embodiment of the present invention.
  • 11 to 15 are schematic diagrams of each step of a manufacturing process of an antenna package structure in an embodiment of the present invention.
  • the term used to describe the relative position in space such as “upper”, “lower”, “rear”, “front”, etc., is used to describe one unit or feature shown in the drawings relative to another A unit or feature relationship.
  • the term spatially relative position may include different orientations of the device in use or operation other than the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as “below” or “above” other elements or features would then be oriented “below” or “above” the other elements or features.
  • the exemplary term “below” can encompass both a spatial orientation of below and above.
  • the present invention provides an antenna package structure
  • the antenna package structure includes: a substrate layer 1, at least one antenna support member 2, a first antenna layer 3, a plastic packaging layer 4 and at least one chip 5, and an interconnection structure Piece 6.
  • the substrate layer 1 includes a chip circuit layer 11 , an antenna control layer 12 and at least one second antenna layer 13 stacked in sequence.
  • the dielectric loss tangent of the interlayer medium of the second antenna layer 13 is less than 0.01.
  • the antenna control layer 12 includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • the interlayer dielectric material of the second antenna layer 13 is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with fillers.
  • a low dielectric constant and low dielectric loss The material is used as the interlayer dielectric material of the second antenna layer 13, which can reduce the dielectric loss and capacitive reactance in the antenna circuit, thereby reducing the problems of current leakage and stray capacitance caused by the dielectric loss.
  • the antenna support member 2 is disposed on the second antenna layer 13, and its dielectric loss tangent value is less than 0.01.
  • the first antenna layer 3 is disposed on the antenna support member 2, and is electrically connected to the substrate layer 1 through the conductive through holes 62 or connecting lines in the antenna support member 2.
  • the first antenna layer 3 may also be connected to the substrate layer. 1 has no physical contact and electrical connection, but forms an electromagnetic radiation non-contact electrical connection with the second antenna layer 13 .
  • the antenna support 2 is made of materials with low dielectric loss, so that the antenna circuit forms a heterogeneous and heterogeneous split structure. As the main component of the antenna circuit and structure, the antenna support 2 can reduce the dielectric loss in the circuit.
  • the shape of the antenna support 2 can be specifically set according to the shape of the plane arrangement of the first antenna layer 3 and the number of antenna modules in the first antenna layer 3, and the outline shape of the horizontal plane of the antenna support 2 is roughly similar to that of the first antenna.
  • the plane arrangement shape of the layer 3, and the projection of the first antenna layer 3 on the horizontal plane is completely within the outline of the antenna support 2, so that the antenna support 2 with low dielectric loss can support the first antenna well At the same time, the space occupied by the package structure is reduced.
  • the antenna support 2 is an organic composite single-layer or multi-layer substrate, one or more of a glass part and a low-temperature co-fired ceramic part, and the organic composite plate and the glass part have low dielectric loss and low dielectric loss.
  • the dielectric constant of low temperature co-fired ceramics has a high dielectric constant with low dielectric loss. Under the condition of ensuring low dielectric loss, the use of antenna supports 2 with different dielectric constants enables the package structure to be suitable for chips 5 with different usage conditions, and meets the requirements for high-density integration of the package structure.
  • the antenna support 2 is attached to the substrate layer 1 through a material such as a chip film or an adhesive paste.
  • the chip film or the adhesive paste also generally has a low dielectric loss constant and a thickness of less than 50um.
  • the chip 5 is disposed on the chip circuit layer 11 relative to the antenna support 2 , that is, the chip 5 and the antenna layer are disposed on two opposite surfaces of the substrate layer 1 .
  • the antenna layer and the chip 5 are arranged on both sides of the substrate layer 1, on the one hand, the circuit layers on the substrate layer 1 can be arranged in layers, the chip 5 and the chip circuit layer 11 are arranged on one side, and the antenna control circuit layer and The antenna layer is arranged on one side, which facilitates the wiring design on the substrate layer 1 in sequence; on the other hand, the signal interference of the antenna layer to the chip 5 can be reduced.
  • an underfill 51 may also be provided between the chip 5 and the chip circuit layer 11 .
  • Chip 5 can be with or without backside metal.
  • the antenna package structure further includes a microwave integrated circuit and/or a power management chip and/or a passive device disposed on the chip circuit layer 11 .
  • Passive devices include capacitors, resistors, etc., or other functional devices such as heat sinks and stiffeners.
  • the antenna package structure further includes an interconnect structure 6 disposed on the second antenna layer 13 and/or the chip circuit layer 11, which includes an antenna side interconnect structure 6a and a chip side interconnect structure 6b.
  • the antenna-side interconnection structure 6 a is electrically connected to at least the ground line on the substrate layer 1 .
  • the chip-side interconnect structure 6b is at least electrically connected to the signal and ground lines on the substrate layer 1 .
  • the interconnection structure member 6 includes a main body member 61 made of a dielectric material, and a conductive hole 62 located at least inside the main body member 61 and communicating with the upper and lower surfaces thereof.
  • the conductive hole 62 may be a through hole or a stacked hole. Or interlayer electrical connection holes, the conductive holes 62 are provided with metal connectors or conductive fillers to be electrically connected to at least the ground circuit layer.
  • the interconnection structure 6 is provided on both the second antenna layer 13 and the chip circuit layer 11, and the antenna side interconnection structure 6a is distributed between the gaps in the antenna support 2 and its peripheral side, so that the space in the package structure can be reduced. maximized and effective use.
  • the upper and lower surfaces of the main body member 61 are plated with designed metal layers, and the metal layers may be higher than, equal to or lower than the upper and lower surfaces of the main body member.
  • the interconnection structure 6 is electrically connected to at least the ground circuit layer through solder, or conductive glue/paste.
  • the main body 61 can also be an organic composite single-layer or multi-layer substrate with low dielectric loss, a glass part and a low-temperature co-fired ceramic part, so as to further reduce the dielectric loss in the package structure, or the main body 61 can also be used.
  • Organic polymer resins with inorganic fillers, or organic polymer resins with glass fiber cloth and fillers, synthetic resins and other polymer materials with certain structural strength can be used.
  • the sidewall of the interconnection structure 6 is provided with a heat dissipation structure 63 and/or a second moisture barrier layer 64 .
  • the chip-side interconnect structure 6b is provided with a second moisture barrier layer 64 exposed to the plastic encapsulation layer 4 , and the heat dissipation structure is made of a material with high thermal conductivity, such as a copper pillar or an electroplated copper layer. Columnar or lamellar structures. Thus, the reliability of the package structure under high temperature and high humidity conditions is further improved.
  • the upper metal surface of the antenna-side interconnection structure 6 a may be higher than, equal to or lower than the upper surface of the first antenna layer 3 .
  • the upper metal surface of the antenna-side interconnection structure 6 a is flush with the upper surface of the first antenna layer 3 .
  • the upper surface of the interconnection structure 6 is higher than the upper surface of the first antenna layer 3 , and the upper surface of the interconnection structure 6 is exposed to the plastic encapsulation layer 4 , thereby facilitating the improvement of the The heat dissipation capability of the package structure and the convenience of stacking additional components on top of the interconnect structure to expand the package structure.
  • the upper surface of the antenna support 2 is further provided with a first moisture barrier layer 7 , the first moisture barrier layer 7 covers the first antenna layer 3 , and the first moisture barrier layer 7 is The upper surfaces of the wet layer 7 and the interconnect structure 6 are exposed to the plastic encapsulation layer 4, and the first moisture barrier layer 7 realizes moisture barrier and moisture proof protection for the first antenna layer 3, improving the reliability of the package structure under high humidity conditions, and the exposed The interconnection structure 6 and the first moisture barrier layer 7 are beneficial to improve the heat dissipation capability of the package structure.
  • the portions of the interconnect structure 6 on both sides of the package structure are further provided with lateral antenna layers 65 , and the lateral antenna layers 65 are disposed toward the side edges of the antenna package structure.
  • the interconnecting structural member 6 is provided with a circuit or a conductive connecting member that electrically connects the lateral antenna layer 65 and the antenna control layer 12 .
  • the antenna-side interconnection structure 6a is a complete block structure, which is provided with solder bumps 66 at at least four corners and at the center. The point 66 is connected to the substrate layer 1 .
  • the antenna-side interconnect structure 6 a is integrated in the antenna support 2 , so as to further improve the integration degree of the package structure.
  • the chip-side interconnection structure 6b is omitted from the package structure, and an inter-board connector 7 is provided there, and the inter-board connector 7 structure and the chip-side interconnect structure Similar to component 6b, a conductive circuit or conductive hole 62 is provided in the dielectric material, which is electrically connected to the circuit of the substrate layer 1, and it is more convenient to connect other electronic components or other electronic structures through the inter-board connector 7, so as to facilitate the packaging structure. expand.
  • the plastic sealing layer 4 covers the substrate layer 1 , the antenna support 2 , the first antenna layer 3 and the chip 5 .
  • the plastic sealing layer 4 is filled with a plastic sealing compound, and the plastic sealing material can be epoxy resin, polyimide, dry film and other polymer composite materials with fillers.
  • the inner element plays a protective role.
  • the plastic encapsulation layer 4 includes a first plastic encapsulation layer 41 and a second plastic encapsulation layer 42 , and the first plastic encapsulation layer 41 at least covers the upper surface of the substrate layer 1 , the side surface of the antenna support 2 , and the antenna side interconnect structure.
  • the side of the component 6a and the first antenna layer 3, and the second plastic encapsulation layer 42 at least covers the side of the chip 5 and the side of the chip-side interconnect structure 6b.
  • the first plastic encapsulation layer 41 and the second plastic encapsulation layer 42 are made of different or the same plastic encapsulation material. By using different materials, the warpage problem of the encapsulation structure can be adjusted by using the difference in thermal expansion coefficient of the different plastic encapsulation materials.
  • the antenna packaging structure is further provided with an electromagnetic shielding layer 8 outside the packaging layer, and the electromagnetic shielding layer 8 covers at least the lateral direction of the chip 5 and the chip circuit layer 11 . Side or side to reduce the electromagnetic wave interference received by the chip 5 .
  • the pads designed by a part of the electromagnetic shielding layer 8 can also be combined with the back of the chip 5 through the second plastic encapsulation layer 42 with holes on the back of the chip 5 and form tin caps or tin balls on the pads to improve heat dissipation or mechanical reliability. .
  • the electromagnetic shielding layer 8 includes: an adhesive layer attached to the plastic sealing layer 4 , a protective layer exposed to the air, and a main shielding layer disposed between the adhesive layer and the protective layer.
  • the adhesive layer is a metal material with high adhesion such as copper, or an organic material with high adhesion, so as to strengthen the bonding strength between the electromagnetic shielding layer 8 and the package structure.
  • the main shielding layer is a sputtered sandwich metal film material such as copper, stainless steel, titanium, etc., or a conductive composite material such as a conductive resin containing high-density metal fillers such as silver/copper, or a combination of at least two of the above materials, capable of Play the role of shielding or absorbing electromagnetic waves.
  • the protective layer is a stainless steel (7% NiV) or CrCu alloy layer, or an organic moisture barrier layer, etc., to further enhance the reliability of the package structure under high humidity conditions.
  • the sidewall of the chip-side interconnection structure 6b is provided with a metal structure, and the metal structure is exposed to the plastic encapsulation layer 4 and electrically connected to the electromagnetic shielding layer 8 to ground.
  • the electromagnetic shielding layer 8 can also be electrically grounded to the metal of the bottom surface of the interconnect structure 6.2.
  • the position of the part of the horizontal cutting surface covered by the electromagnetic shielding layer 8 is different.
  • the present invention also provides a packaging method for an antenna packaging structure, comprising the steps of:
  • a temporary carrier 9 As shown in FIG. 11 , a temporary carrier 9 is provided, and at least one chip circuit layer 11 , at least one antenna control layer 12 , and at least one first layer on the antenna control layer 12 are arranged on the temporary carrier 9
  • the two antenna layers 13 form the substrate layer 1
  • the second antenna layer 13 uses a dielectric material with a dielectric loss tangent less than 0.01 as an interlayer medium.
  • the substrate layer 1 may be a prefabricated substrate strip or substrate pellet, or a redistribution stack layer formed by multiple layers of fine metal wiring and dielectric layer openings on a temporary carrier.
  • Temporary carrier 9 is a low cost, somewhat rigid, sacrificial substrate with a temporary debonding layer or etch barrier, such as glass, silicon, composite polymer, etc., for structural support.
  • the temporary carrier plate 9 may also be a high temperature film with a reinforced frame with a single-sided temporal adhesive layer.
  • the temporary carrier plate 9 may be rectangular, square or circular.
  • the antenna control layer 12 includes an antenna signal control circuit and an antenna signal transmission and reception circuit.
  • At least the interlayer dielectric material of the second antenna layer 13 is a resin with a dielectric constant not greater than 3.9 or a polymer dielectric material with fillers
  • an interconnection structure is provided on the substrate layer 1 , and the interconnection structure is electrically connected to the ground circuit layer on the substrate layer 1 .
  • the interconnection structural member 6 includes a main body member 61 made of a dielectric material, and a metal connecting member located inside the main body member 61 and communicating with the upper and lower surfaces thereof.
  • the metal connecting member is connected to the grounding circuit on the substrate layer 1 .
  • Layer electrical connection
  • the upper surface and the lower surface of the main body 61 are plated with designed metal layers, and the antenna side interconnect structure 6a is electrically connected to the ground circuit layer through solder, or conductive glue/paste.
  • the main body 61 can be a single-layer or multi-layer organic composite substrate with low dielectric loss, a glass part and a low-temperature co-fired ceramic part to further reduce the dielectric loss in the package structure, or the main body 61 can also use Organic polymer resin with inorganic filler, or organic polymer resin with glass fiber cloth and filler, synthetic resin and other polymer materials with certain structural strength.
  • the portions of the interconnect structure located on both sides of the package structure are further provided with lateral antenna layers 65, and the lateral antenna layers 65 are disposed toward the side edges of the antenna package structure.
  • the sidewall of the interconnection structure 6 is provided with a heat dissipation structure 63 and/or a second moisture barrier layer 64 , and the second moisture barrier layer 64 is exposed to the plastic sealing layer 4 .
  • the interconnection structure 6 is a complete block structure, which is provided with solder bumps at at least four corners and at the center, and is connected to the overtime layer through the solder bumps.
  • an antenna support 2 with a dielectric loss tangent less than 0.01 is provided on the second antenna layer 13 , and the first antenna layer 3 is provided on the antenna support 2 .
  • the antenna support member 2 is one or more of a single-layer or multi-layer organic composite substrate, a glass member and a low-temperature co-fired ceramic member.
  • the antenna support member 2 is attached to the substrate layer 1 by a material such as a chip back film or an adhesive paste.
  • the interconnection structures 6 disposed on one side of the second antenna layer 13 are distributed between the gaps in the antenna support 2 and its periphery, and the upper surface of the interconnection structures 6 is not lower than the upper surface of the first antenna layer 3 .
  • the first plastic encapsulation layer 41 is filled to cover the substrate layer 1 , the interconnection structural member 6 , the antenna support member 2 and the first antenna layer 3 .
  • a first plastic encapsulation layer 41 is formed by encapsulating the interconnecting structural member, the antenna support member 2 and the first antenna layer 3 .
  • the plastic encapsulation layer 4 may be polished to expose the upper surface of the interconnection structure 6 .
  • the steps before refilling the plastic sealing compound, the steps further include:
  • a first moisture barrier layer 7 is formed on the upper surface of the antenna support member 2 before the antenna support member 2 is cut or after the antenna support member 2 is attached to the substrate layer 1 , and the first moisture barrier layer 7 covers the first antenna layer 3 .
  • the molding layer 4 may be polished to expose the upper surface of the interconnection structure 6 and the upper surface of the first moisture barrier layer 7 .
  • the upper surface of the interconnect structure 6 and/or the upper surface of the first moisture barrier layer 7 may be directly protected during the molding process, so that no molding layer covers the upper surface of the interconnect structure 6 and/or the first moisture barrier layer 7 .
  • the upper surface of a moisture barrier layer 7 may be polished to expose the upper surface of the interconnection structure 6 and the upper surface of the first moisture barrier layer 7 .
  • the temporary carrier 9 is removed, and the interconnect structure 6 and at least one chip 5 are arranged on the chip circuit layer 11, and the chip 5 may be with or without back metal.
  • the second plastic encapsulation layer 42 is performed to form a single-piece antenna encapsulation structure by cutting.
  • the second plastic encapsulation layer 42 may be thinned and/or laser drilled/grooved to expose the interface pads of the chip-side interconnect structure 6b and/or the interface pads of the chip 5 . At least a part of the backside, and then the solder caps or solder balls are covered on the interface pads and/or the backside metal of the chip side interconnection structure 6b.
  • the temporary carrier plate 9 is peeled off by methods such as laser debonding separation, mechanical peeling, chemical etching, and mechanical grinding.
  • the complete package structure is divided into individual package structures along the dicing lines by a saw blade or a laser cutting device.
  • plastic packaging of the chip 5 further includes the steps:
  • An underfill 51 is coated between the chip 5 and the chip circuit layer 11 .
  • setting the chip 5 also includes the steps of:
  • Microwave integrated circuits and/or power management chips and/or passive devices are arranged on the chip circuit layer 11 .
  • Passive devices include capacitors, resistors, etc., or other functional devices such as heat sinks and stiffeners.
  • An adhesive layer, a main shielding layer and a protective layer are sequentially deposited on the outside of the antenna packaging structure to form an electromagnetic shielding layer 8 .
  • the electromagnetic shielding layer 8 includes: an adhesive layer attached to the plastic sealing layer 4 , a protective layer exposed to the air, and a main shielding layer disposed between the adhesive layer and the protective layer.
  • the adhesive layer is a metal material with high adhesion such as copper, or an organic material with high adhesion.
  • the primary shielding layer is a sputtered sandwich metal film material such as copper, stainless steel, titanium, etc., or a conductive composite material such as a conductive resin containing high-density metal fillers such as silver/copper, or a combination of at least two of the above materials.
  • the protective layer is stainless steel, NiV (7%) or CrCu alloy layer, or organic moisture barrier layer.
  • step S2 and step S3 can be exchanged, or performed simultaneously; After that, the temporary carrier board 9 is removed to form the antenna support member 2 and the antenna layer, etc., as long as the relatively distributed chip and antenna layer packaging structure can be formed.
  • the antenna support and the interlayer medium of the antenna are made of low dielectric loss materials, thereby forming a heterogeneous antenna structure, so as to reduce the problems of current leakage and stray capacitance in the package structure caused by dielectric loss, and it is beneficial to Reduce the size of the antenna package structure.

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Abstract

本发明提供一种天线封装结构及天线封装结构制造方法，将天线和芯片分设于基板层两侧，天线层由天线支撑件、位于天线支撑件上方的第一天线层和位于天线支撑件下方的第二天线层共同构成，天线支撑件和天线层层间介质采用低介电损耗材料，从而形成异质异构的天线结构，以减少因介电损耗带来的封装结构内电流泄漏、杂散电容等问题，并减小天线封装结构的尺寸。

Description

天线封装结构及天线封装结构制造方法 技术领域
本发明涉及封装技术领域，具体地涉及一种天线封装结构及天线封装结构制造方法。
背景技术
随着高科技电子产品的普及以及人们需求的增加，特别是为了配合移动的需求，大多高科技电子产品都增加了无线通讯的功能，目前无线通信设备通常会包括天线模块和一个或多个集成电路。天线模块和集成电路可以按数种不同方式(例如，封装内天线(AIP)、封装上天线(AOP)、片上天线(AOC)等)来布置。
天线模块与集成电路之间电信号通常需要通过一条或多条导电线路和/或一个或多个贯通孔来实现传输，这些线路和通孔由导电材料制成或填充，并且其与介电材料接触和/或被介电材料至少部分地包围，由于常规的介电材料(诸如硅或模塑化合物)具有较高的介电损耗，从而易产生诸如电流漏泄、杂散电容等问题。并且，由于常规介电材料性能所限，封装结构的在诸如高温高压条件下的可靠性较差且不利于封装结构的小型化。
发明内容
本发明的目的在于提供一种天线封装结构及天线封装结构制造方法。
本发明提供一种天线封装结构，所述天线封装结构包括：基板层、至少一个天线支撑件、第一天线层、塑封层和至少一个芯片；
所述基板层包括依次堆叠设置的至少一层芯片线路层、至少一层天线控制层和至少一层第二天线层，所述第二天线层层间介质的介电损耗正切值小于0.01；
所述天线支撑件设于所述第二天线层上，其介电损耗正切值小于0.01；
所述第一天线层设于所述天线支撑件上，其与所述第二天线层通过电磁辐射或物理接触电性连接；
所述芯片相对于所述天线支撑件，设于所述芯片线路层上；
所述塑封层包覆所述基板层、所述天线支撑件、所述第一天线层和所述芯片。
作为本发明的进一步改进，所述天线支撑件为有机复合基板，玻璃件和低温共 烧陶瓷件中的一种或多种。
作为本发明的进一步改进，至少所述第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
作为本发明的进一步改进，所述天线控制层包括天线信号控制线路和天线信号发送接收线路。
作为本发明的进一步改进，所述天线支撑件的上表面还设有第一阻湿层，所述第一阻湿层包覆所述第一天线层，并暴露于或埋入所述塑封层。
作为本发明的进一步改进，所述天线封装结构还包括设于所述第二天线层和/或所述芯片线路层上的互连结构件，所述第二天线层上的互连结构件至少电性连接于所述基板层接地线路，所述芯片线路层上的所述互连结构件电性连接于所述基板层。
作为本发明的进一步改进，所述互连结构件包括由介电材料构成主体件，以及至少位于所述主体件内部连通其上下表面的导电孔，所述导电孔内设有金属连接件或导电填料以至少与接地线路层电性连接，设于所述第二天线层一侧的所述互连结构件分布于所述天线支撑件内空隙之间及其周侧。
作为本发明的进一步改进，所述互连结构件位于所述封装结构两侧的部分还可以设有侧向天线层，所述侧向天线层朝向所述天线封装结构侧边缘设置。
作为本发明的进一步改进，所述互连结构件的侧壁设有散热结构件和/或第二阻湿层，所述第二阻湿层暴露于或埋入于所述塑封层外侧。
作为本发明的进一步改进，所述塑封层包括第一塑封层和第二塑封层，所述第一塑封层至少包覆所述基板层上表面、所述天线支撑件侧面，所述互连结构件侧面和所述第一天线层，所述第二塑封层至少包覆所述芯片侧面和互连结构件侧面，所述第一塑封层和所述第二塑封层材料相异。
作为本发明的进一步改进，所述天线封装结构于塑封层外侧还设有可以电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层侧向，所述电磁屏蔽层包括：贴合于所述塑封层的粘结层，暴露于空气的保护层，以及设于所述粘结层和所述保护层之间的主屏蔽层，所述互连结构件侧壁设有金属结构件，所述金属结构件暴露于所述塑封层与所述电磁屏蔽层接地电性连接，所述电磁屏蔽层的一部分在所述芯片背面形成焊盘或通过开孔的所述塑封层与所述芯片背面结合形成焊盘。
作为本发明的进一步改进，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路和/或电源管理芯片和/或被动器件。
本发明还提供一种天线封装结构的封装方法，包括步骤：
提供一临时载板，在所述临时载板上设置芯片线路层，天线控制层，以及至少一层位于所述天线控制层上的第二天线层形成基板层，所述第二天线层以介电损耗正切值小于0.01的介电材料的作为层间介质；
于所述基板层上设置互联结构件，所述互联结构件电性连接于所述基板层上的接地线路层；
于所述第二天线层上设置介电损耗正切值小于0.01的至少一个天线支撑件，于所述天线支撑件上设置第一天线层；
填充第一塑封层包覆所述基板层、所述互联结构件、所述天线支撑件和所述第一天线层；
去除所述临时载板，于所述芯片线路层上设置互连结构件和至少一个芯片，并填充形成第二塑封层，切割形成单块天线封装结构。
作为本发明的进一步改进，所述天线支撑件为有机复合基板，玻璃件和低温共烧陶瓷件中的一种或多种。
作为本发明的进一步改进，所述第一塑封层至少包覆所述基板层上表面、所述天线支撑件侧面，所述互连结构件侧面和所述第一天线层，所述第二塑封层至少包覆所述芯片侧面和互连结构件侧面，所述第一塑封层和所述第二塑封层材料相异。
作为本发明的进一步改进，至少所述第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
作为本发明的进一步改进，所述芯片线路层包括天线信号控制线路和天线信号发送接收线路。
作为本发明的进一步改进，还包括步骤：
于所述天线支撑件的上表面形成第一阻湿层，所述第一阻湿层包覆所述第一天线层。
作为本发明的进一步改进，所述互连结构件包括由介电材料构成主体件，以及至少位于所述主体件内部连通其上下表面的金属连接件，所述金属连接件至少与所述基板层上的接地线路层电性连接。
作为本发明的进一步改进，设于所述第二天线层一侧的所述互连结构件分布于所述天线支撑件内空隙之间及其周侧。
作为本发明的进一步改进，所述互连结构件位于所述封装结构两侧的部分还可以设有侧向天线层，所述侧向天线层朝向所述天线封装结构侧边缘设置。
作为本发明的进一步改进，所述互连结构件的侧壁设有散热结构件和/或第二阻 湿层，所述第二阻湿层暴露于或埋入于所述塑封层。
作为本发明的进一步改进，在切割形成单颗天线封装体之前，还可以包括步骤：
部分切割所述第一塑封层或第二塑封层；
于所述天线封装结构外侧依次沉积粘结层，主屏蔽层和保护层来形成电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层。
作为本发明的进一步改进，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路、电源管理芯片和被动器件。
本发明的有益效果是：本发明将天线和芯片分设于基板层两侧，天线层由天线支撑件、位于天线支撑件上方的第一天线层和位于天线支撑件下方的第二天线层共同构成，天线支撑件和天线层层间介质采用低介电损耗材料，从而形成异质异构的天线结构，以减少因介电损耗带来的封装结构内电流泄漏、杂散电容等问题，并减小天线封装结构的尺寸。
附图说明
图1是本发明一实施方式中的天线封装结构示意图。
图2是本发明另一实施方式中的天线封装结构中基板层和天线层的示意图，其互连结构件上表面高于第一天线层上表面。
图3是本发明另一实施方式中的天线封装结构中基板层和天线层的示意图，其天线支撑件的上表面还设有第一阻湿层。
图4是本发明另一实施方式中的天线封装结构示意图，其互连结构件位于封装结构两侧的部分设有侧向天线层。
图5是本发明另一实施方式中的天线封装结构中基板层和天线层的示意图，其互连结构件为一完整块状结构件。
图6是本发明另一实施方式中的天线封装结构中基板层和天线层的示意图，互连结构件集成在天线支撑件内。
图7是本发明另一实施方式中的天线封装结构示意图，其设有板间连接器。
图8和图9是发明另一实施方式中的天线封装结构示意图，其于封装层外侧还设有电磁屏蔽层。
图10是本发明一实施方式中的天线封装结构制造流程图。
图11至图15是本发明一实施方式中的天线封装结构制造流程各步骤示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施方式及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施方式仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
下面详细描述本发明的实施方式，实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
为方便说明，本文使用表示空间相对位置的术语来进行描述，例如“上”、“下”、“后”、“前”等，用来描述附图中所示的一个单元或者特征相对于另一个单元或特征的关系。空间相对位置的术语可以包括设备在使用或工作中除了图中所示方位以外的不同方位。例如，如果将图中的装置翻转，则被描述为位于其他单元或特征“下方”或“上方”的单元将位于其他单元或特征“下方”或“上方”。因此，示例性术语“下方”可以囊括下方和上方这两种空间方位。
如图1所示，本发明提供一种天线封装结构，天线封装结构包括：基板层1、至少一个天线支撑件2、第一天线层3、塑封层4和至少一个芯片5，和互连结构件6。
基板层1包括依次堆叠设置的芯片线路层11、天线控制层12和至少一层第二天线层13，第二天线层13层间介质的介电损耗正切值小于0.01。
天线控制层12包括天线信号控制线路和天线信号发送接收线路。
具体的，在本实施方式中，第二天线层13层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料，通过选用具有低介电常数和低介电损耗的材料作为第二天线层13的层间介质材料，可以减少天线电路内的介电损耗和容抗，从而减少因介电损耗带来的电流泄漏、杂散电容等问题。
天线支撑件2设于第二天线层13上，其介电损耗正切值小于0.01。
进一步的，第一天线层3设于天线支撑件2上，其通过位于天线支撑件2内的导电通孔62或连接线路电性连接于基板层1，第一天线层3也可以与基板层1没有物理接触电性连接，而与第2天线层13形成电磁辐射非接触电连接。天线支撑件2 采用低介电损耗的材料，使得天线线路形成异质异构的分体式结构，天线支撑件2作为天线线路和结构的主要组成部分可以减小电路内的介电损耗。
具体的，天线支撑件2的形状可以根据第一天线层3的平面排布形状以及第一天线层3中天线模块的数量而具体设置，天线支撑件2的水平面轮廓形状大致类似于第一天线层3的平面排布形状，且第一天线层3在水平面上的投影完全位于天线支撑件2轮廓之内，从而可以使具有低介电损耗的天线支撑件2对第一天线起到良好支撑作用的同时，减少其在封装结构内所占用的空间。
更进一步的，天线支撑件2为有机复合单层或多层基板，玻璃件和低温共烧陶瓷件中的一种或多种，有机复合板和玻璃件在具有低介电损耗的同时具有低的介电常数，低温共烧陶瓷在具有低介电损耗的同时具有高的介电常数。在保证介电损耗较低的情况下，通过使用具有不同介电常数的天线支撑件2，使得封装结构能够适用于具有不同使用条件的芯片5，满足封装结构高密度集成化的需求。
天线支撑件2通过芯片膜或粘结膏等材料贴合于基板层1，芯片膜或粘结膏也一般具有较低的介电损耗常数并且厚度小于50um。
芯片5相对于天线支撑件2，设于芯片线路层11上，即芯片5与天线层分设于基板层1的相对两个表面上。将天线层与芯片5分设于基板层1两侧，一方面，使得基板层1上的线路层可以实现分层布置，将芯片5和芯片线路层11设在一侧，将天线控制线路层和天线层设在一侧，便于在基板层1上依次分别进行布线设计；另一方面，可以减少天线层对芯片5的信号干扰。
在本发明的一些实施方式中，芯片5和芯片线路层11之间还可以设有底填料51。芯片5可以带或不带背面金属。
在本发明的一些实施方式中，天线封装结构还包括设于芯片线路层11上的微波集成电路和/或电源管理芯片和/或被动器件。被动器件包括诸如电容、电阻等，或者其他诸如散热片、加强筋等功能器件。
天线封装结构还包括设于第二天线层13和/或芯片线路层11上的互连结构件6,其包括天线侧互连结构件6a和芯片侧互连结构件6b。天线侧互连结构件6a至少电性连接于基板层1上的接地线路。而芯片侧互连结构件6b至少电性连接于基板层1上的信号和接地线路。
进一步的，在本实施方式中，互连结构件6包括由介电材料构成主体件61，以及至少位于主体件61内部连通其上下表面的导电孔62，导电孔62可以是通孔或叠孔或层间电性连孔，导电孔62内设有金属连接件或导电填料以至少与接地线路层电 性连接。于第二天线层13和芯片线路层11上均设有互连结构件6，天线侧互连结构件6a分布于天线支撑件2内空隙之间及其周侧，以使封装结构内的空间得到最大化有效利用。
主体件61的上表面和下表面镀覆有设计的金属层，金属层可以高于，等于或低于主体件的上下表面。互连结构件6通过焊锡，或导电胶/膏电性至少连接于接地线路层。
更进一步的，主体件61也可以为具有低介电损耗的有机复合单层或多层基板，玻璃件和低温共烧陶瓷件，以进一步降低封装结构内的介电损耗，或者主体件61也可采用带无机填料的有机高分子树脂，或带玻纤布与填料有机高分子树脂，合成树脂等具有一定结构强度的聚合物材料。
互连结构件6的侧壁设有散热结构件63和/或第二阻湿层64。
具体的，在本实施方式中，芯片侧互连结构件6b设有暴露于塑封层4的第二阻湿层64，散热结构件为诸如铜柱或电镀铜层等由具有高热导材料制成柱状或薄层状结构件。从而进一步提高封装结构在高温和高湿条件下的可靠性。
天线侧互连结构件6a上金属表面可以高于，等于或低于第一天线层3上表面。
具体的，在本实施方式中，天线侧互连结构件6a上金属表面与第一天线层3上表面平齐。
如图2所示，在本发明的一些其他实施方式中，互连结构件6上表面高于第一天线层3上表面，且互连结构件6上表面暴露于塑封层4，从而利于提高封装结构的散热能力，以及方便在互联结构件上方另外堆叠其他部件来对封装结构进行拓展。
如图3所示，在本发明的一些其他实施方式中，天线支撑件2的上表面还设有第一阻湿层7，第一阻湿层7包覆第一天线层3，第一阻湿层7和互连结构件6上表面暴露于塑封层4，第一阻湿层7对第一天线层3实现阻湿防潮保护，提高封装结构在高湿条件下的可靠性，且暴露的互连结构件6和第一阻湿层7有利于提高封装结构的散热能力。
如图4所示，在本发明的一些其他实施方式中，互连结构件6位于封装结构两侧的部分还设有侧向天线层65，侧向天线层65朝向天线封装结构侧边缘设置。互连结构件6内设有电性连通侧向天线层65与天线控制层12的线路或导电连接件。
如图5所示，在本发明的一些其他实施方式中，天线侧互连结构件6a为一完整块状结构件，其至少于四个角落和中心处设置有焊料凸点66，通过焊料凸点66与基板层1进行连接。
如图6所示，在本发明的一些其他实施方式中，天线侧互连结构件6a集成在天线支撑件2内，从而进一步提高封装结构的集成度。
如图7所示，在本发明的一些其他实施方式中，封装结构省略芯片侧互连结构件6b，并于该处设置板间连接器7，板间连接器7结构与芯片侧互连结构件6b类似，于介电材料中设置导电线路或导电孔62，与基板层1线路电性连接，通过板间连接器7更加便于连接其他电子元器件或者其他电子结构，以利于对封装结构进行拓展。
塑封层4包覆基板层1、天线支撑件2、第一天线层3和芯片5。塑封层4由塑封料填充而成，塑封料可以为环氧树脂、聚酰亚胺、干膜等带填料的高分子聚合物复合材料，塑封层4为封装结构提供物理支撑，并对封装结构内元件起到保护作用。
进一步的，在本实施方式中，塑封层4包括第一塑封层41和第二塑封层42，第一塑封层41至少包覆基板层1上表面、天线支撑件2侧面、天线侧互连结构件6a侧面和第一天线层3，第二塑封层42至少包覆芯片5侧面和芯片侧互连结构件6b侧面。第一塑封层41和第二塑封层42采用不同或相同的塑封料，通过采用不同的材料可以利用不同塑封料的热膨胀系数等差异来调整封装结构的翘曲问题。
如图8和图9所示，在本发明的一些其他实施方式中，天线封装结构于封装层外侧还设有电磁屏蔽层8，电磁屏蔽层8至少覆盖芯片5侧向和芯片线路层11的侧向或侧面，以减少芯片5所受到的电磁波干扰。由电磁屏蔽层8的一部分而设计的焊盘也可以通过在芯片5背面开孔的第二塑封层42与芯片5背面结合并在焊盘上形成锡帽或锡球从而提高散热或机械可靠性。
具体的，电磁屏蔽层8包括：贴合于塑封层4的粘结层，暴露于空气的保护层，以及设于粘结层和保护层之间的主屏蔽层。粘结层为铜等具有较高粘附性的金属材料，或为具有高粘附性的有机材料，以加强电磁屏蔽层8和封装结构之间的结合强度。主屏蔽层是诸如铜，不锈钢，钛等溅射夹层金属薄膜材料，或诸如含银/铜之类高密度金属填料的导电树脂等导电复合材料，或是上述材料中至少两种的组合，能够起到屏蔽或吸收电磁波的作用即可。防护层为不锈钢(7％NiV)或CrCu合金层，或有机阻湿层等，以进一步加强封装结构在高湿条件下的可靠性。
进一步的，芯片侧互连结构件6b侧壁设有金属结构件，金属结构件暴露于塑封层4与电磁屏蔽层8接地电性连接。电磁屏蔽层8也可以与互连结构件6.2底部表面金属进行接地电性连接。
根据制造流程中工艺步骤顺序的差异，电磁屏蔽层8所覆盖的部分水平切割面位置存在差异。
如图10所示，本发明还提供一种天线封装结构的封装方法，包括步骤：
S1：如图11所示，提供一临时载板9，在临时载板9上设置至少一层芯片线路层11，至少一层天线控制层12，以及至少一层位于天线控制层12上的第二天线层13形成基板层1，第二天线层13以介电损耗正切值小于0.01的介电材料的作为层间介质。基板层1可以是预制基板条或基板单粒，或是在临时载板上由多层微细金属布线和介电层开孔形成的重布线堆叠层。
临时载板9为诸如玻璃，硅，复合聚合物等低成本，具有一定刚性和带临时解键合层或蚀刻阻挡层的牺牲基材，以用于结构支撑。临时载板9也可以是带加强框架的有单面临时粘合层的高温膜。临时载板9可以是长方形，方形或圆形。
进一步的，天线控制层12包括天线信号控制线路和天线信号发送接收线路。
具体的，在本实施方式中，至少第二天线层13层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料
S2：如图11所示，于基板层1上设置互联结构件，互联结构件电性连接于基板层1上的接地线路层。
具体的，在本实施方式中，互连结构件6包括由介电材料构成主体件61，以及位于主体件61内部连通其上下表面的金属连接件，金属连接件与基板层1上的接地线路层电性连接。
主体件61的上表面和下表面镀覆有设计的金属层，天线侧互连结构件6a通过焊锡，或导电胶/膏电性连接于接地线路层。
进一步的，主体件61可以为具有低介电损耗的单层或多层有机复合基板，玻璃件和低温共烧陶瓷件，以进一步降低封装结构内的介电损耗，或者主体件61也可采用带无机填料的有机高分子树脂，或带玻纤布与填料有机高分子树脂，合成树脂等具有一定结构强度的聚合物材料。
在本发明的一些其他实施方式中，互连结构位于封装结构两侧的部分还设有侧向天线层65，侧向天线层65朝向天线封装结构侧边缘设置。
在本发明的一些其他实施方式中，互连结构件6的侧壁设有散热结构件63和/或第二阻湿层64，第二阻湿层64暴露于塑封层4。
在本发明的一些其他实施方式中，互连结构件6为一完整块状结构件，其至少于四个角落和中心处设置有焊料凸点，通过焊料凸点与加班层进行连接。
S3：如图11所示，于第二天线层13上设置介电损耗正切值小于0.01的天线支撑件2，于天线支撑件2上设置第一天线层3。
具体的，在本实施方式中，天线支撑件2为单层或多层有机复合基板，玻璃件和低温共烧陶瓷件中的一种或多种。
天线支撑件2通过芯片背膜或粘结膏等材料贴合于基板层1。
设于第二天线层13一侧的互连结构件6分布于天线支撑件2内空隙之间及其周侧，且互连结构件6上表面不低于第一天线层3上表面。
S4：如图12所示，填充第一塑封层41包覆基板层1、互连结构件6、天线支撑件2和第一天线层3。
采用诸如带无机填料的有机高分子树脂，或带玻纤布与填料的有机高分子树脂，或环氧树脂、聚酰亚胺、干膜等带填料的聚合物复合材料作为塑封料沉积在基板层1之上，包封互联结构件、天线支撑件2和第一天线层3形成第一塑封层41。
当互连结构件6上表面高于第一天线层3上表面较多时，可以对塑封层4进行打磨，暴露出互连结构件6上表面。
在本发明一些其他实施方式中，再填充塑封料之前，还包括步骤：
于天线支撑件2切割之前或贴合于基板层1之后在天线支撑件2的上表面形成第一阻湿层7，第一阻湿层7包覆第一天线层3。
填充塑封料之后，依设计和性能需要，可以对塑封层4进行打磨，暴露出互连结构件6上表面和第一阻湿层7的上表面。在一种实施方法中，塑封过程中可以直接保护互连结构件6上表面和/或第一阻湿层7的上表面，从而没有塑封层覆盖与互连结构件6上表面和/或第一阻湿层7的上表面。
S5：如图13和图14所示，去除临时载板9，于芯片线路层11上设置互连结构件6和至少一个芯片5，芯片5可以带或不带背面金属。并进行第二塑封层42，切割形成单块天线封装结构。在其中一种实施方法中，在最终切割之前，第二塑封层42可以进行减薄和/或激光开孔/开槽以露出芯片侧互连结构件6b的接口焊盘和/或芯片5的至少部分背面，并随之覆盖锡帽或锡球于芯片侧互连结构件6b的接口焊盘和/或芯片背面金属上。
通过激光解键分离，机械剥离、化学蚀刻、机械研磨等方法将临时载板9剥离。
通过锯片或激光切割装置沿切割道将完整的封装结构分成单独的封装结构。
进一步的，在本发明的一些实施方式中，对芯片5进行塑封之前还包括步骤：
于芯片5和芯片线路层11之间涂设底填料51。
进一步的，在本发明的一些实施方式中，设置芯片5同时还包括步骤：
于芯片线路层11上设置微波集成电路和/或电源管理芯片和/或被动器件。被动 器件包括诸如电容、电阻等，或者其他诸如散热片、加强筋等功能器件。
在本发明的一些实施方式中，切割形成单颗天线封装体之前，还包括步骤：
部分切割塑封层；
于天线封装结构外侧依次沉积粘结层，主屏蔽层和保护层来形成电磁屏蔽层8，电磁屏蔽层8至少覆盖芯片5侧向和芯片线路层11的侧向或侧面。
具体的，电磁屏蔽层8包括：贴合于塑封层4的粘结层，暴露于空气的保护层，以及设于粘结层和保护层之间的主屏蔽层。粘结层为铜等具有较高粘附性的金属材料，或为具有高粘附性的有机材料度。主屏蔽层是诸如铜，不锈钢，钛等溅射夹层金属薄膜材料，或诸如含银/铜之类高密度金属填料的导电树脂等导电复合材料，或是上述材料中至少两种的组合。防护层为不锈钢，NiV(7％)或CrCu合金层，或有机阻湿层等。
需要说明的是，本发明中的部分步骤顺序可以进行交换调整，如步骤S2和步骤S3可以交换顺序，或同时进行；如也可先于临时载板9上先设置芯片5和基板层2，之后再去除临时载板9，形成天线支撑件2和天线层等，只要能够形成相对分布的芯片和天线层封装结构结构即可。
综上所述，本发明通过将天线和芯片分设于基板层两侧，由天线支撑件、位于天线支撑件上方的第一天线层和位于天线支撑件下方的第二天线层共同构成天线层，天线支撑件和天线层层间介质采用低介电损耗材料，从而形成异质异构的天线结构，以减少因介电损耗带来的封装结构内电流泄漏、杂散电容等问题，并有利于减小天线封装结构的尺寸。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (24)

  1. 一种天线封装结构，其特征在于，
    所述天线封装结构包括：基板层、至少一个天线支撑件、第一天线层、塑封层和至少一个芯片；
    所述基板层包括依次堆叠设置的至少一层芯片线路层、至少一层天线控制层和至少一层第二天线层，所述第二天线层层间介质的介电损耗正切值小于0.01；
    所述天线支撑件设于所述第二天线层上，其介电损耗正切值小于0.01；
    所述第一天线层设于所述天线支撑件上，其与所述第二天线层通过电磁辐射或物理接触电性连接；
    所述芯片相对于所述天线支撑件，设于所述芯片线路层上；
    所述塑封层包覆所述基板层、所述天线支撑件、所述第一天线层和所述芯片。
  2. 根据权利要求1所述的天线封装结构，其特征在于，所述天线支撑件为有机复合基板，玻璃件和低温共烧陶瓷件中的一种或多种。
  3. 根据权利要求2所述的天线封装结构，其特征在于，至少所述第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
  4. 根据权利要求3所述的天线封装结构，其特征在于，所述天线控制层包括天线信号控制线路和天线信号发送接收线路。
  5. 根据权利要求2所述的天线封装结构，其特征在于，所述天线支撑件的上表面还设有第一阻湿层，所述第一阻湿层包覆所述第一天线层，并暴露于或埋入所述塑封层。
  6. 根据权利要求2所述的天线封装结构，其特征在于，所述天线封装结构还包括设于所述第二天线层和/或所述芯片线路层上的互连结构件，所述第二天线层上的互连结构件至少电性连接于所述基板层接地线路，所述芯片线路层上的所述互连结构件电性连接于所述基板层。
  7. 根据权利要求6所述的天线封装结构，其特征在于，所述互连结构件包括由介电材料构成主体件，以及至少位于所述主体件内部连通其上下表面的导电孔，所述导电孔内设有金属连接件或导电填料以至少与接地线路层电性连接，设于所述第二天线层一侧的所述互连结构件分布于所述天线支撑件内空隙之间及其周侧。
  8. 根据权利要求6所述的天线封装结构，其特征在于，所述互连结构件位于所述封装结构两侧的部分还可以设有侧向天线层，所述侧向天线层朝向所述天线封装结 构侧边缘设置。
  9. 根据权利要求6所述的天线封装结构，其特征在于，所述互连结构件的侧壁设有散热结构件和/或第二阻湿层，所述第二阻湿层暴露于或埋入于所述塑封层外侧。
  10. 根据权利要求6所述的天线封装结构，其特征在于，所述塑封层包括第一塑封层和第二塑封层，所述第一塑封层至少包覆所述基板层上表面、所述天线支撑件侧面，所述互连结构件侧面和所述第一天线层，所述第二塑封层至少包覆所述芯片侧面和互连结构件侧面，所述第一塑封层和所述第二塑封层材料相同或相异。
  11. 根据权利要求6所述的天线封装结构，其特征在于，所述天线封装结构于塑封层外侧还设有电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层侧向，所述电磁屏蔽层包括：贴合于所述塑封层的粘结层，暴露于空气的保护层，以及设于所述粘结层和所述保护层之间的主屏蔽层，所述互连结构件侧壁设有金属结构件，所述金属结构件暴露于所述塑封层与所述电磁屏蔽层接地电性连接，所述电磁屏蔽层的一部分在所述芯片背面形成焊盘或通过开孔的所述塑封层与所述芯片背面结合形成焊盘。
  12. 根据权利要求1所述的天线封装结构，其特征在于，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路和/或电源管理芯片和/或被动器件。
  13. 一种天线封装结构的封装方法，其特征在于，包括步骤：
    提供一临时载板，在所述临时载板上设置芯片线路层，天线控制层，以及至少一层位于所述天线控制层上的第二天线层形成基板层，所述第二天线层以介电损耗正切值小于0.01的介电材料的作为层间介质；
    于所述基板层上设置互联结构件，所述互联结构件电性连接于所述基板层上的接地线路层；
    于所述第二天线层上设置介电损耗正切值小于0.01的至少一个天线支撑件，于所述天线支撑件上设置第一天线层；
    填充第一塑封层包覆所述基板层、所述互联结构件、所述天线支撑件和所述第一天线层；
    去除所述临时载板，于所述芯片线路层上设置互连结构件和至少一个芯片，并填充形成第二塑封层，切割形成单块天线封装结构。
  14. 根据权利要求13所述的封装方法，其特征在于，所述天线支撑件为有机复合基板，玻璃件和低温共烧陶瓷件中的一种或多种。
  15. 根据权利要求13所述的封装方法，其特征在于，所述第一塑封层至少包覆所 述基板层上表面、所述天线支撑件侧面，所述互连结构件侧面和所述第一天线层，所述第二塑封层至少包覆所述芯片侧面和互连结构件侧面，所述第一塑封层和所述第二塑封层材料相异。
  16. 根据权利要求13所述的封装方法，其特征在于，至少所述第二天线层层间介电材料为介电常数不大于3.9的树脂或带填料的高分子介电材料。
  17. 根据权利要求13所述的封装方法，其特征在于，所述芯片线路层包括天线信号控制线路和天线信号发送接收线路。
  18. 根据权利要求13所述的封装方法，其特征在于，还包括步骤：
    于所述天线支撑件的上表面形成第一阻湿层，所述第一阻湿层包覆所述第一天线层。
  19. 根据权利要求13所述的封装方法，其特征在于，所述互连结构件包括由介电材料构成主体件，以及至少位于所述主体件内部连通其上下表面的金属连接件，所述金属连接件至少与所述基板层上的接地线路层电性连接。
  20. 根据权利要求19所述的封装方法，其特征在于，设于所述第二天线层一侧的所述互连结构件分布于所述天线支撑件内空隙之间及其周侧。
  21. 根据权利要求20所述的封装方法，其特征在于，所述互连结构件位于所述封装结构两侧的部分还可以设有侧向天线层，所述侧向天线层朝向所述天线封装结构侧边缘设置。
  22. 根据权利要求19所述的封装方法，其特征在于，所述互连结构件的侧壁设有散热结构件和/或第二阻湿层，所述第二阻湿层暴露于或埋入于所述塑封层。
  23. 根据权利要求13所述的封装方法，其特征在于，在切割形成单颗天线封装体之前，还可以包括步骤：
    部分切割所述第一塑封层或第二塑封层；
    于所述天线封装结构外侧依次沉积粘结层，主屏蔽层和保护层来形成电磁屏蔽层，所述电磁屏蔽层至少覆盖所述芯片和芯片线路层。
  24. 根据权利要求13所述的封装方法，其特征在于，所述天线封装结构还包括设于所述芯片线路层上的微波集成电路、电源管理芯片和被动器件。
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