TWI508260B - 具有金屬導線之微電子晶粒封裝、含有金屬導線之堆疊晶粒封裝及相關方法及系統 - Google Patents

具有金屬導線之微電子晶粒封裝、含有金屬導線之堆疊晶粒封裝及相關方法及系統 Download PDF

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TWI508260B
TWI508260B TW097128170A TW97128170A TWI508260B TW I508260 B TWI508260 B TW I508260B TW 097128170 A TW097128170 A TW 097128170A TW 97128170 A TW97128170 A TW 97128170A TW I508260 B TWI508260 B TW I508260B
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Taiwan
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individual
package
metal
die
dielectric
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TW097128170A
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TW200926392A (en
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Meow Koon Eng
Yong Poo Chia
Suan Jeung Boon
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Micron Technology Inc
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Description

具有金屬導線之微電子晶粒封裝、含有金屬導線之堆疊晶粒封裝及相關方法及系統
本揭示案大體係關於具有金屬導線之微電子晶粒封裝，且更明確地說，係關於經組態用於堆疊晶粒封裝之金屬導線。
經封裝之微電子組合(諸如，記憶體晶片及微處理器晶片)通常含有一安裝至一基板且裝入於一塑料保護罩中之微電子晶粒。該晶粒含有功能特徵，諸如，記憶體單元、處理器電路及互連電路。該晶粒亦通常含有電耦接至功能特徵之結合襯墊。結合襯墊電連接至延伸到保護罩外部的針腳或其他類型之端子，用於將晶粒連接至匯流排、電路或其他微電子組合。
在一習知配置中，將晶粒安裝至支撐基板(例如，印刷電路板)，且用線結合將晶粒結合襯墊電耦接至基板之對應的結合襯墊。在密封後，可用焊球或其他合適連接來將基板電連接至外部裝置。因此，基板支撐晶粒，且提供晶粒與外部裝置之間的電鏈接。
在其他習知配置中，可將晶粒安裝至具有連接至抽取式框架之傳導性導線指狀物之導線架。在製造期間，該框架臨時地將導線指狀物支撐在相對於晶粒之適當位置中。每一導線指狀物耦接至晶粒之對應的結合襯墊(例如，經由線結合或金屬重分布層)，且以框架及導線指狀物中之每一者的一部分延伸出密封材料之方式來密封該組合。接著 修剪該框架，且每一導線指狀物之暴露部分將晶粒連接至外部組件。一般而言，個別導線指狀物可經彎曲且接著耦接至一對應的外部結合襯墊。
晶粒製造商們已受到減小由晶粒佔據之體積且仍增加所得經密封之組合的容量之不斷增加的壓力。為了滿足此等需求，晶粒製造商們常將多個晶粒相互疊置以增加在電路板或晶粒所安裝至的其他元件上之有限表面積內的裝置之容量或效能。
以下參照半導體裝置及製造半導體裝置之方法來描述本揭示案之若干實施例的具體細節。在可含有基板之半導體晶圓上製造半導體組件，將微電子裝置、微機械裝置、資料儲存元件、光學器件、讀取/寫入組件及其他特徵製造於半導體晶圓上或中。舉例而言，可將SRAM、DRAM(例如，DDR/SDRAM)、快閃記憶體(例如，NAND快閃記憶體)、處理器、成像器及其他類型之裝置建構於半導體晶圓上。雖然以下描述關於具有積體電路之半導體裝置的許多實施例，但製造於其他類型之基板上的其他類型之裝置可處於本發明之範疇內。此外，本發明之若干其他實施例可具有與此章節中所描述之組態、組件或程序不同的組態、組件或程序。因此，一般熟習此項技術者將因此理解本發明可具有帶有額外元件之其他實施例，或者本發明可具有無以下關於圖1至圖12展示及描述的特徵中之若干者之其他實施例。
圖1為具有複數個晶粒封裝10(個別地由參考數字10a至10d識別)之堆疊系統100之一實施例之橫截面側視圖。個別晶粒封裝10可含有一微電子晶粒12、一模製介電殼14及與殼14側向間隔開之金屬導線16(或金屬接觸)。殼14具有側向殼側21、頂部殼側22及底部殼側23，且殼14密封晶粒12及導線16之至少一部分。在圖1所展示之實例中，個別導線16耦接至底部殼側23且至少部分朝向位於上部之晶粒封裝或堆疊系統100之頂部突出。個別導線16可進一步含有一外部導線表面25及一內部導線表面26，內部導線表面26具有一大體面向個別側向殼側21之區域27。所說明之實例的內部表面區域27位於個別導線16之有角度的導線部分28上，有角度的導線部分28與側向殼側21側向間隔該導線之側向導線部分29。晶粒封裝10可進一步含有將導線16電耦接至晶粒12之金屬跡線32及包住跡線32及晶粒12之有效側之一部分的介電間隔層34。晶粒封裝10亦可含有耦接至跡線32之封裝結合襯墊36。舉例而言，堆疊系統100具有一插入式基板102，該插入式基板102具有一金屬凸塊襯墊104，該金屬凸塊襯墊104由結合襯墊連接106電連接至在第一晶粒封裝10a處之封裝結合襯墊36。
圖1中所示之堆疊系統100之實施例含有由黏接層112a－c在對應之頂側及底側處實體地耦接在一起之四個堆疊晶粒封裝10a－d，且該等晶粒封裝10a－d之導線16由外部封裝間連接器114電耦接在一起。舉例而言，連接器114可為沿著外部導線表面25之對應於垂直對準之導線16之集合之部分 及視情況沿著內部導線表面26之部分而形成的金屬焊料線。因此，金屬襯墊104經由含有導線16及連接器114之傳導路徑電耦接至晶粒封裝10a－d內之微電子晶粒。在許多實施例中，且如圖1中所示，對應於晶粒封裝10a－c之導線16延伸超出頂部殼側22，接觸位於上部之晶粒封裝10上之外部導線表面25之一部分，且由個別連接器114固持至外部導線表面25之該部分。另外，圖1中所展示之個別連接器114之實施例沿著有角度的導線部分28及側向導線部分29附著至外部導線表面25及內部導線表面26的部分。在替代實施例中，連接器114可僅沿著有角度之導線部分28附著至外部導線表面25之一部分，且視情況，沿著側向導線部分29附著至內部導線表面26之一部分。因此，連接器114之若干實施例至少自有角度的導線部分28側向向外突出，且視情況，可朝向側向殼側21在個別晶粒封裝10之間延伸。
堆疊系統100可由一方法形成，該方法含有堆疊晶粒封裝10a－d且在晶粒封裝10a－d之個別導線16處形成連接器114。堆疊且對準導線16可含有依次堆疊晶粒封裝10a－d，使得一封裝之導線16被置放於鄰近的晶粒封裝上之對應導線上方或下方，且使得下部封裝之導線16朝向上部封裝之導線16向上突出。可使用波焊或回焊製程來形成連接器114。在波焊製程中，可將泵汲的波狀或級聯的液相金屬焊料施加於有角度的導線部分28。在回焊製程中，具有金屬粉末粒子之焊錫膏可經施加於有角度的導線部分28上且 接著經加熱以熔化金屬粒子。在此等或其他焊接製程中，金屬焊料選擇性地潤濕(例如，當經加熱時)至外部導線表面25之至少一部分，且視情況，內部導線表面26之一部分，但焊料並不潤濕至殼14之介電材料。當金屬焊料冷卻時，連接器114形成，且個別晶粒封裝10之個別導線16與上部或下部晶粒封裝上之對應的導線耦接。在其他實施例中，個別導線16中之一些可不實體接觸在緊鄰的晶粒封裝上之對應的導線，使得僅某些導線與鄰近的晶粒封裝互連。在任何此等實施例中，連接器114可橋接鄰近的晶粒之垂直對準的導線16之間的垂直間隙(例如，見圖9，參考68)。舉例而言，60微米或更小之垂直導線間隔距離可創造出足夠的表面張力以用於形成個別導線16之間的焊料橋。
一般而言，且與堆疊系統100相對比，堆疊封裝或晶粒之習知方法已具有挑戰性且花費高。舉例而言，因為習知導線未經配置以面向介電殼或朝向位於上部的晶粒封裝突出，所以其可能難以定位，且若未準確地對準，可能在封裝下方崩潰。此外，將一封裝上之習知導線附著至一對應的封裝上之對應的導線耗時甚巨，且需要仔細地手動操縱及檢查每一習知的導線間互連。舉例而言，在位於上部的晶粒封裝上之習知的導線通常向下彎曲，使得其朝向位於下部的晶粒封裝上之導線突出。當習知導線經歷附著製程時，需要檢查導線間連接以驗證彎曲的導線相對於下部之封裝正確地定位。同樣，堆疊習知封裝之製程難以標準 化，因為晶粒係按各種各樣的大小製造，且封裝同樣地在大小上變化。因此，需要特製堆疊且互連習知封裝之製程以適合於特定封裝類型之配置。
微電子晶粒封裝10之若干實施例可易於堆疊且為穩固的。舉例而言，在堆疊且對準了晶粒封裝10a－d後，對應的晶粒封裝之導線16經自動地充分對準以供連接器114相互耦接導線，且並不需要手動操縱來將個別導線相互對準。另外，因為導線16自殼14之側面向外延伸，所以其提供一位於個別導線之側向部分與有角度部分兩者上之接觸表面；此致能使用簡單的焊接製程來相互耦接晶粒封裝10a－d，且創造出不需要嚴格的對準容差之可靠的導線間互連。同樣，藉由為個別導線16提供一表面以在其上壓縮或回彈，晶粒封裝10之側向殼側21可防止導線16在晶粒封裝堆疊期間崩潰。此外，導線16可進一步確定外部封裝尺寸，使得可使用標準化的封裝大小來收容各種各樣的不同大小之晶粒，如以下參看圖10進一步詳細地解釋。
圖2A至圖8B說明根據本揭示案之若干實施例形成微電子晶粒封裝之階段。圖2A為含有一坐落於釋放層45之頂部上的金屬框架41之微電子組合40之俯視圖。框架41包含導線部分42、開口43及切割道44。開口43暴露釋放層45之一部分，用於鄰近導線部分42附著且定位晶粒12(圖1)，且切割道44提供一切削或分裂路徑以用於自框架41切割個別晶粒封裝(參看圖8A及圖8B進一步地描述)。在一實施例中，框架41可由銅製造，且可含有沿著導線部分42之選擇性的 銅鍍層。在其他實施例中，框架41可包含各種各樣的其他金屬材料，諸如，鋁或鋁銅合金。舉例而言，釋放層45可為熱或UV釋放膜。
圖2B及圖2C為展示框架41、導線部分42、釋放層45及支撐基板47(例如，矽晶圓或具有平坦表面之其他類型的結構)的組合40之部分分解橫截面側視圖。圖2B進一步展示一個別切割道44，及圖2C進一步展示個別導線部分42之間的間隙48。間隙48與開口43及支撐基板47一起界定一空穴之底部及側面，該空穴隨後將被填充有介電材料(參看圖4A至圖4C進一步加以描述)。個別導線部分42相互間隔開一間隔距離s1 ，其應足夠大以防止連接器114在個別導線上側向橋接。
圖3A為在將微電子晶粒附著至釋放層45後的組合40之俯視圖。更具體言之，圖3A展示框架41、導線部分42及開口43，其中個別晶粒12經置放於開口43內且鄰近導線部分42。圖3B及圖3C為進一步展示開口43及導線部分42之橫截面側視圖，導線部分42位於晶粒12之頂側表面下，且具有厚度t1 。在若干實施例中，導線部分42可具有在約50微米至250微米之範圍內之厚度t1 。
圖4A為在介電材料50已形成於金屬框架41之頂側及晶粒12之頂側上之後的組合40之俯視圖。舉例而言，介電材料50可為聚合物或塑料，其經加熱且隨後沈積於框架41之頂部上及間隙內。舉例而言，介電材料50可經模製於框架41及晶粒12之頂側上。圖4B及圖4C為展示填充晶粒12周圍 之開口43及導線部分42之間的間隙48之介電材料50之橫截面側視圖。在固化或冷卻後，變硬的介電材料50應在晶粒12上、晶粒12之側面與導線部分42之間的間隙內，及導線部分42之間的間隙48內形成一保護且電隔離罩。視情況，介電材料50可在晶粒12上延伸厚度t2 以完全密封全部晶粒12及導線部分42。
圖5A及圖5B為在移除釋放層45及支撐基板47以暴露晶粒12之底側表面52(例如，有效側)且暴露導線部分42之底側表面54後的組合40之橫截面側視圖及仰視圖。晶粒12之底側表面52含有電耦接至晶粒12內之積體電路(未圖示)的結合襯墊56(或有效特徵)。介電材料50將晶粒12固持於適當位置處，且將晶粒12與導線部分42分隔開。
圖6為在晶粒12之底側表面52處形成介電間隔層34之一實施例後之組合40的橫截面側視圖。間隔層34含有將結合襯墊56電耦接至導線部分42及封裝結合襯墊36之金屬跡線32。間隔層34可由諸如非傳導性氧化物或聚合物之材料製造。舉例而言，金屬跡線32及封裝結合襯墊36可由銅或鋁製造。間隔層34可因此為重分布結構。亦期望在某些實施例中，可省略封裝結合襯墊36。舉例而言，在圖1中，可省略晶粒封裝10b－d之封裝結合襯墊，因為此等襯墊未電連接至任何外部結合襯墊。
圖7為在藉由化學蝕刻、背面研磨或化學機械拋光製程移除介電材料50之一部分以形成殼14後之組合40的橫截面側視圖。舉例而言，介電材料50可經蝕刻以暴露內部導線 表面26(圖1)及形成殼14之頂側22及側向殼側21。另外，雖然展示為具有傾斜表面，但在其他實施例中，側向殼側21可經形成使得其大體上與頂部殼側22垂直。然而，預期側向殼側21之傾斜、彎的、錐形或其他分級構形向個別導線提供位於上部之導線或晶粒封裝下方彎曲或壓縮的空間。同樣地，傾斜的側向殼側21可用以增加個別導線與側向殼側21之上部分之間的側向間隔距離，以為在內部導線表面26上形成連接器提供較多空間。
圖8A為在經由切割道44進行分離(例如，藉由修剪及形成設備)以產生收容於殼14中且耦接至個別「L」型導線16之分隔之晶粒12後之封裝10a之一實施例的橫截面側視圖。圖8B展示在晶粒封裝60a之分離後的替代實施例，該晶粒封裝60a經形成以具有含有側向朝向側向殼側21延伸之分層導線部分67之個別「C」型導線66。在兩個實施例中，側向導線部分29離開側向殼側21突出，有角度的導線部分28延伸離開側向導線部分29，使得內部表面區域27大體與在側向殼側21處之一表面對準，且外部導線表面25大體背向側向殼側21，且經配置以收納一外部封裝間連接器。有角度的導線部分28可含有各種各樣的有角度的、彎的或其他傾斜的構形，視情況，其可含有大體上與側向導線部分29垂直之構形或大體上朝向側向殼側21傾斜之構形。在圖8B之實施例中，有角度的導線部分28大體上與側向導線部分29垂直，且有角度的導線部分28將分層導線部分67定位於側向導線部分29上方。此允許個別導線66容納 額外類型之外部封裝間連接器，諸如，金屬焊料凸塊(例如，見圖9)。因此，晶粒封裝10a或60a可被置放於堆疊系統(諸如，堆疊系統100)內，且可在有角度的導線部分28、側向導線部分29或分層導線部分67處的導線16或66之暴露的或其他可接取的表面中之任一者處，沿著晶粒封裝10a或60a形成連接器114。
圖9為含有至少部分由黏接層112a－c實體耦接於一起之個別晶粒封裝60a以及晶粒封裝60b－d的堆疊系統200之一實施例之橫截面側視圖。晶粒封裝60a－d之導線66由外部封裝間連接器214實體且電耦接於一起。在此實施例中，連接器214含有插入於分層導線部分67與對應的晶粒封裝上之側向導線部分29之間的金屬焊料凸塊。個別晶粒封裝60之導線66相互垂直分隔開一跨越距離t3 之間隙68，距離t3 可大約為60微米或更小。個別連接器214橋接間隙68且沿著分層導線部分67以及有角度的導線部分28及側向導線部分29附著至外部導線表面25之部分。類似於堆疊系統100，堆疊系統200可藉由一方法形成，該方法含有堆疊晶粒封裝60a－d使得晶粒封裝60a－d之導線對準且在晶粒封裝60a－d之個別導線66處形成連接器214。可使用金屬焊料凸塊製程來形成連接器214，該製程含有形成附著至外部導線表面25之部分的金屬焊料點。如所展示，焊接點可經組態以沿著有角度的導線部分28附著至外部導線表面25，使得連接器214經定位於個別晶粒封裝60a－d之間，且自側向導線部分29向外突出。在其他實施例中，連接器214可進 一步耦接至內部導線表面26之部分。
圖10為展示含有具有對應的微電子晶粒74a－c之微電子晶粒封裝72a－c的堆疊系統300之一實施例之橫截面側視圖。晶粒封裝72a－c共用一共同的側向尺寸d1 ，但微電子晶粒74a－c具有不同的側向尺寸d2 、d3 及d4 (不按彼次序)。在一實施例中，堆疊系統300可為一記憶體模組，其含有在晶粒74a處之一界面電路、在晶粒74b處之一控制電路及在晶粒74c處之一記憶體。因為晶粒封裝72a－c共用共同的側向尺寸d1 ，所以藉由堆疊較佳的晶粒封裝或交換某些晶粒封裝，可創造出大量不同類型之堆疊系統。舉例而言，藉由使用收容於具有側向尺寸d1 之晶粒封裝中的較小的基於磁阻RAM(MRAM)之晶粒，可組裝基於DRAM之記憶體模組之一替代實施例。因此，可用基於MRAM之晶粒封裝替換基於DRAM之晶粒封裝72b－c。
圖11為展示含有由介電間隔層84a－d分隔且具有分別由第一連接器414a及第二連接器414b耦接於一起之第一金屬導線86a－d及第二金屬導線88a－d的微電子晶粒封裝82a－d之堆疊系統400之一實施例之橫截面側視圖。在此視圖中，間隔層84a含有對應的金屬跡線90a－b，間隔層84c含有對應的金屬跡線91a－b，間隔層84d含有一單一金屬跡線92，但間隔層84b不具有沿著第二封裝82b之此視圖的任何對應的金屬跡線(亦即，晶粒封裝82a－d在其他橫截面圖中可具有不同金屬跡線配置，使得第二封裝82b不具有沿著說明之橫截面的金屬跡線)。第一連接器414a經施加於第一導線 86a－d上以選擇性地電耦接第一封裝82a、第三封裝82c及第四封裝82d；及第二連接器414b經施加於第二導線88a－d上以選擇性地電耦接第一封裝82a及第三封裝82c。因此，晶粒封裝82d之一側及晶粒封裝82b之兩側與連接器414a－b電隔離。堆疊晶粒封裝82a－d之製程可與參看圖1及圖9描述之製程相同。形成晶粒封裝82a－d之製程可類似於參看圖2A至圖8B描述之製造方法，但替代將金屬跡線連接至每一金屬導線，已省略了個別金屬跡線與導線的耦接。
可進行對上述堆疊系統之許多其他類型之變化(含有與此等系統相關的某些特徵之各種組合)。舉例而言，代替結合襯墊連接106(圖1及圖9)，線結合可將一堆疊系統電耦接至一插入式基板。在一些實施例中，可省略插入於堆疊封裝之間的黏接層。舉例而言，外部封裝間連接器單獨地可用以藉由臨時地夾緊封裝直至施加金屬焊料且形成連接器而將個別晶粒封裝固持於一起。在其他實施例中，連接器可經組態以藉由將金屬焊料施加於有限數目個導線上而選擇性地路由導線之個別集合。未經焊接之導線保持與堆疊系統電隔離。在一具體實施例中，堆疊系統含有收容同一類型之晶粒的晶粒封裝。舉例而言，堆疊系統可為記憶體，諸如，靜態動態存取記憶體(SRAM)。在此實施例中，個別導線將提供對收容於個別晶粒封裝中之個別SRAM晶粒之字線及位元線存取。因此，累積的個別SRAM晶粒形成大的SRAM，相對於相同大小之習知SRAM，其具有減小之佔據面積。同樣，堆疊系統可含有 具有比說明之實施例中呈現的封裝多或少之封裝之任何數目個個別微電子晶粒封裝。
以上參看圖1至圖11描述的微電子裝置中之任一者可被併入於大量較大或較複雜的系統490中之任一者內，系統490之一代表示意性地展示於圖12中。系統490可含有一處理器491、一記憶體492(例如，SRAM、DRAM、快閃記憶體或其他記憶體裝置)、輸入/輸出裝置493或其他子系統或組件494。圖12中展示之組件中的任一者中可含有微電子裝置。所得系統490可執行廣泛的各種各樣之計算、處理、儲存、感測器、成像或其他功能中之任一者。因此，代表性系統490含有(但不限於)電腦或其他資料處理器，例如，桌上型電腦、膝上型電腦、網際網路器具、手持式裝置(例如，掌上型電腦、可佩帶式電腦、蜂巢式或行動電話、個人數位助理)、多處理器系統、基於處理器或可程式之消費者電子器件、網路電腦及小型電腦。其他代表性系統490含有相機、光或其他輻射感測器、伺服器及相關伺服器子系統、顯示器裝置或記憶體裝置。在此等系統中，個別晶粒可含有成像器陣列，諸如，CMOS成像器。系統490之組件可收容於一單一單元中或分布於多個互連之單元上，例如，經由一通信網路。組件可因此含有本端或遠端記憶體儲存裝置及廣泛的各種各樣之電腦可讀媒體中之任何者。
自前述內容，將瞭解，為了說明之目的，本文中已描述了具體實施例，但尚未詳細展示或描述熟知結構及功能以 避免不必要地使前述實施例之描述模糊不清。在上下文允許的情況下，單數或複數術語亦可分別包含複數或單數術語。此外，除非詞「或」明確限制為僅意謂一單一項而排除關於兩項或更多項之列表中的其它項，否則在此列表中「或」之使用應解釋為含有(a)該列表中任何單一項，(b)該列表中所有項，或(c)該列表中之項的任何組合。另外，術語「包含」為包括性的，且遍及全文使用以意謂含有至少該(等)所述特徵，使得並不排除任何更大數量之相同特徵及/或額外類型之其他特徵。亦應瞭解，為了說明之目的，本文中已描述了具體實施例，但在不脫離本發明之情況下，可進行各種修改。舉例而言，除了其他實施例之元件以外或代替其他實施例之元件，一實施例之許多元件可與其他實施例相組合。因此，除如由隨附申請專利範圍所限制之外，本發明不受限制。
10a‧‧‧晶粒封裝
10b‧‧‧晶粒封裝
10c‧‧‧晶粒封裝
10d‧‧‧晶粒封裝
12‧‧‧晶粒
14‧‧‧殼
16‧‧‧導線
21‧‧‧側向殼側
22‧‧‧頂部殼側
23‧‧‧底部殼側
25‧‧‧外部導線表面
26‧‧‧內部導線表面
27‧‧‧內部表面區域
28‧‧‧有角度的導線部分
29‧‧‧側向導線部分
32‧‧‧跡線
34‧‧‧介電間隔層
36‧‧‧封裝結合襯墊
40‧‧‧組合
41‧‧‧框架
42‧‧‧導線部分
43‧‧‧開口
44‧‧‧切割道
45‧‧‧釋放層
47‧‧‧支撐基板
48‧‧‧間隙
50‧‧‧介電材料
52‧‧‧晶粒之底側表面
54‧‧‧導線部分之底側表面
56‧‧‧結合襯墊
60a‧‧‧晶粒封裝
60b‧‧‧晶粒封裝
60c‧‧‧晶粒封裝
60d‧‧‧晶粒封裝
66‧‧‧導線
67‧‧‧分層導線部分
68‧‧‧間隙
72a‧‧‧晶粒封裝
72b‧‧‧晶粒封裝
72c‧‧‧晶粒封裝
74a‧‧‧晶粒
74b‧‧‧晶粒
74c‧‧‧晶粒
82a‧‧‧晶粒封裝
82b‧‧‧晶粒封裝
82c‧‧‧晶粒封裝
82d‧‧‧晶粒封裝
84a‧‧‧間隔層
84b‧‧‧間隔層
84c‧‧‧間隔層
84d‧‧‧間隔層
86a‧‧‧第一導線
86b‧‧‧第一導線
86c‧‧‧第一導線
86d‧‧‧第一導線
88a‧‧‧第二導線
88b‧‧‧第二導線
88c‧‧‧第二導線
88d‧‧‧第二導線
90a‧‧‧金屬跡線
90b‧‧‧金屬跡線
91a‧‧‧金屬跡線
91b‧‧‧金屬跡線
92‧‧‧金屬跡線
100‧‧‧堆疊系統
102‧‧‧插入式基板
104‧‧‧金屬凸塊襯墊
106‧‧‧結合襯墊連接
112a‧‧‧黏接層
112b‧‧‧黏接層
112c‧‧‧黏接層
114‧‧‧連接器
214‧‧‧連接器
300‧‧‧堆疊系統
400‧‧‧堆疊系統
414a‧‧‧連接器
414b‧‧‧連接器
490‧‧‧系統
491‧‧‧處理器
492‧‧‧記憶體
493‧‧‧輸入/輸出裝置
494‧‧‧其他子系統或組件
d1 ‧‧‧側向尺寸
d2 ‧‧‧側向尺寸
d3 ‧‧‧側向尺寸
d4 ‧‧‧側向尺寸
s1 ‧‧‧間隔距離
t1 ‧‧‧厚度
t2 ‧‧‧厚度
t3 ‧‧‧距離
圖1為含有根據本揭示案之一實施例組態且堆疊的微電子晶粒封裝之一堆疊系統之橫截面側視圖。
圖2A為含有一框架、一釋放層及一支撐基板的微電子組合之俯視圖。
圖2B及圖2C為圖2A之組合之部分分解橫截面側視圖。
圖3A為圖2A之具有定位於框架之開口中的微電子晶粒之組合之俯視圖。
圖3B及圖3C為圖3A之組合之橫截面側視圖。
圖4A為圖3A之經密封於介電材料中的組合之俯視圖。
圖4B及圖4C為圖4A之組合之橫截面側視圖。
圖5A及圖5B為在移除支撐基板後的圖4A之組合之橫截面側視及仰視圖。
圖6為在形成一間隔層後的圖5A及圖5B之組合之橫截面側視圖。
圖7為在介電材料之部分移除後的圖6A之組合之橫截面側視圖。
圖8A為在分離及金屬導線之形成後的圖7之組合之橫截面側視圖。
圖8B為根據本揭示案之一替代實施例的在分離及金屬導線之形成後的圖7之組合之橫截面側視圖。
圖9為含有根據本揭示案之一替代實施例組態且堆疊的微電子晶粒封裝之一堆疊系統之橫截面側視圖。
圖10為根據本揭示案之一實施例的具有含有不同大小之晶粒之微電子晶粒封裝的一堆疊系統之橫截面側視圖。
圖11為根據本揭示案之一實施例的具有用於選擇性地電耦接個別微電子晶粒封裝之金屬跡線的一堆疊系統之橫截面側視圖。
圖12為其中可併入有微電子晶粒封裝及堆疊系統之一系統之示意性說明。
10a‧‧‧晶粒封裝
10b‧‧‧晶粒封裝
10c‧‧‧晶粒封裝
10d‧‧‧晶粒封裝
12‧‧‧晶粒
14‧‧‧殼
16‧‧‧導線
21‧‧‧側向殼側
22‧‧‧頂部殼側
23‧‧‧底部殼側
25‧‧‧外部導線表面
26‧‧‧內部導線表面
27‧‧‧內部表面區域
28‧‧‧有角度的導線部分
29‧‧‧側向導線部分
32‧‧‧跡線
34‧‧‧介電間隔層
36‧‧‧封裝結合襯墊
100‧‧‧堆疊系統
102‧‧‧插入式基板
104‧‧‧金屬凸塊襯墊
106‧‧‧結合襯墊連接
112a‧‧‧黏接層
112b‧‧‧黏接層
112c‧‧‧黏接層
114‧‧‧連接器

Claims (35)

  1. 一種微電子晶粒封裝之堆疊系統，其包含：一第一晶粒封裝，其具有一底側且含有一第一微電子晶粒、至少部分覆蓋該第一微電子晶粒之一第一介電殼，及耦接至該第一微電子晶粒且具有一第一外表面之個別第一金屬導線；一第二晶粒封裝，其具有一附著至該第一晶粒封裝之該底側之一頂側，且含有一第二微電子晶粒、至少部分覆蓋該第二微電子晶粒且具有一側面之一第二介電殼，及耦接至該第二微電子晶粒且具有一第二外表面及一大體面向該側面之內表面區域之個別第二金屬導線，其中該等個別第二金屬導線至少大體與該等個別第一金屬導線對準，且至少部分朝向該第一晶粒封裝突出；及外部封裝間連接器，其將個別第一外表面之一第一部分與個別第二外表面之一第二部分耦接。
  2. 如請求項1之堆疊系統，其中該等個別第二金屬導線具有一L形且實體接觸對應的個別第一金屬導線。
  3. 如請求項1之堆疊系統，其中該等個別第二金屬導線具有一C形且含有一朝向該第二介電殼之該側面突出之分層部分。
  4. 如請求項1之堆疊系統，其中該等個別第二金屬導線耦接至該第二介電殼之一底側。
  5. 如請求項1之堆疊系統，其中該第二晶粒封裝之一底側進一步含有耦接至與一插入式基板相關之金屬凸塊襯墊 之封裝結合。
  6. 如請求項1之堆疊系統，其中該等外部封裝間連接器自該等第一外表面之該第一部分及該等第二外表面之該第二部分側向向外突出。
  7. 如請求項6之堆疊系統，其中該等外部封裝間連接器進一步朝向該第二介電殼之該側面而在該第一晶粒封裝與該第二晶粒封裝之間延伸。
  8. 如請求項1之堆疊系統，其中該第二介電殼之該側面具有一傾斜構形，且該等個別第二金屬導線之該等內表面區域與該側面間隔開一間隙。
  9. 如請求項1之堆疊系統，其中該第二晶粒封裝之該等個別第二金屬導線以若干垂直間隙與該第一晶粒封裝之對應的個別第一金屬導線分隔開，且其中該等外部封裝間連接器包含橋接對應之成對之第一金屬導線與第二金屬導線之間之該等垂直間隙的焊料鏈接。
  10. 如請求項1之堆疊系統，其中該第一微電子晶粒具有一第一側向尺寸，及該第二微電子晶粒具有一與該第一側向尺寸不同之第二側向尺寸，且其中該第一介電殼及該第二介電殼具有相等的側向尺寸。
  11. 一種計算系統，其包含一處理器、一記憶體及一輸入/輸出裝置中之至少一者，其中該計算系統含有一堆疊系統，該系統包含：一第一晶粒封裝，其具有一底側且含有一第一微電子晶粒、至少部分覆蓋該第一微電子晶粒之一第一介電 殼，及耦接至該第一微電子晶粒且具有一第一外表面之個別第一金屬導線；一第二晶粒封裝，其具有一附著至該第一晶粒封裝之該底側之一頂側，且含有一第二微電子晶粒、至少部分覆蓋該第二微電子晶粒且具有一側面之一第二介電殼，及耦接至該第二微電子晶粒且具有一第二外表面及一大體面向該側面之內表面區域之個別第二金屬導線，其中該等個別第二金屬導線至少大體與該等個別第一金屬導線對準，且至少部分朝向該第一晶粒封裝突出；及外部封裝間連接器，其將個別第一外表面之一第一部分與個別第二外表面之一第二部分耦接。
  12. 一種微電子晶粒封裝之堆疊系統，其包含：一第一微電子晶粒封裝，其含有一第一介電殼，該第一介電殼具有一第一底側及附著至該第一底側之第一金屬導線；一第二微電子晶粒封裝，其附著至該第一微電子晶粒封裝，且其含有一第二介電殼，該第二介電殼具有一側面、一第二底側及耦接至該第二底側之第二金屬導線，其中個別第二金屬導線含有一遠離該側面突出之側向部分、一彎曲及一自該彎曲朝向一對應之個別第一金屬導線突出之有角度的部分；及金屬焊料連接器，其附著至該等個別第一金屬導線及該等第二金屬導線之個別有角度之部分之一表面。
  13. 如請求項12之堆疊系統，其中該有角度的部分大體上朝 向該第二介電殼之該側面向內傾斜，且其中該等第二金屬導線直接接觸對應的第一金屬導線。
  14. 如請求項12之堆疊系統，其中個別金屬焊料連接器將個別有角度的部分附著至一對應之第一金屬導線之一表面。
  15. 一種微電子裝置之堆疊系統，其包含：一第一微電子裝置，其具有一第一底側及耦接至該第一底側之第一金屬導線；一第二微電子裝置，其具有一側面、一第二底側及耦接至該第二底側之第二金屬導線，該等第二金屬導線含有一遠離該側面側向突出之側向部分、一朝向該側面側向突出之分層部分，及一將該分層部分定位於該側向部分上之在該側向部分與該分層部分之間之有角度的部分；及金屬焊料凸塊，其處於個別第一金屬導線及該等第二金屬導線之個別分層部分之間。
  16. 如請求項15之堆疊系統，其中該等金屬焊料凸塊進一步在該有角度之部分之大體背向該側面之一表面處，附著至該第二微電子裝置之該等個別第二金屬導線。
  17. 如請求項15之堆疊系統，其中該分層部分與一對應之第一金屬導線分隔開一高達60微米之垂直距離。
  18. 如請求項15之堆疊系統，其中該有角度的部分大體上與該側向部分垂直。
  19. 一種微電子晶粒封裝，其包含： 一微電子晶粒；一介電殼，其至少部分密封該微電子晶粒且具有一底側；及複數個個別金屬接觸，其耦接至該微電子晶粒及該介電殼之該底側，且含有遠離該介電殼突出之一側向部分、遠離該底側彎曲之一彎曲部及自該彎曲部遠離該介電殼之該底側延伸之一有角度的部分，該有角度的部分具有一面向該介電殼表面之第一表面及一大體背向該介電殼表面之第二表面，且其中該第二表面經組態以接收一外部封裝間連接器。
  20. 如請求項19之微電子晶粒封裝，其中該外部封裝間連接器包含一金屬焊料線及一金屬焊料凸塊中之至少一者。
  21. 如請求項20之微電子晶粒封裝，其中該個別金屬接觸具有一L形，且該第一表面及該第二表面中之至少一者經組態為一濕的表面，以附著至該外部封裝間連接器。
  22. 如請求項20之微電子晶粒封裝，其中該個別金屬接觸具有一C形，該C形含有一自該有角度的部分朝向該介電殼表面向內延伸的分層部分，該分層部分具有一第三表面，其大體背向該側向部分，且經組態為一濕的表面，以與該外部封裝間連接器附著在一起。
  23. 一種製造一微電子裝置之方法，該方法包含：在具有一含有一第二底側及一側面之第二介電殼之一第二晶粒封裝的頂部上，堆疊具有一含有一第一底側之第一介電殼之一第一晶粒封裝； 將耦接至該第一晶粒封裝之該第一底側的第一金屬導線與耦接至該第二晶粒封裝之該第二底側的第二金屬導線對準；及形成附著至個別第一金屬導線之一第一部分及附著至與該第二介電殼之該側面間隔開且朝向該第一晶粒封裝突出之個別第二金屬導線之一第二部分的個別外部封裝間連接器。
  24. 如請求項23之方法，進一步包含壓縮該等第二金屬導線，使得該等第二金屬導線朝向該第二介電殼之該側面彎曲。
  25. 如請求項23之方法，其中形成該等外部封裝間連接器包含將金屬焊料潤濕至該等個別第一金屬導線之該第一部分及該等個別第二金屬導線之該第二部分。
  26. 如請求項25之方法，進一步包含將該金屬焊料潤濕至該等個別第二金屬導線之內部及外部表面部分。
  27. 如請求項23之方法，其中該等個別第二金屬導線包含一L形，且其中該第二部分含有該等個別第二金屬導線之一有角度的部分。
  28. 如請求項23之方法，其中該等個別第二金屬導線包含一C形，且其中該第二部分進一步含有一朝向該第二介電殼之該側面突出的分層。
  29. 如請求項28之方法，其中形成該等外部封裝間連接器包含將金屬焊料凸塊潤濕至該等個別第一金屬導線之該第一部分及該等個別第二金屬導線之該第二部分。
  30. 如請求項23之方法，進一步包含將該第二晶粒封裝之封裝結合襯墊耦接至與一插入式基板相關的金屬凸塊襯墊。
  31. 一種製造一微電子晶粒封裝之方法，該方法包含：形成一至少部分密封一微電子晶粒且含有一底側及一側面之介電殼；及形成具有一側向部分及一有角度之部分之個別金屬接觸，該側向部分耦接至該介電殼之該底側且遠離該介電殼之該側面突出，該有角度之部分與該介電殼之該側面間隔開且遠離該側向部分延伸，使得該有角度之部分之一內表面面向該介電殼之該側面，且其中該有角度之部分經組態以潤濕至一外部封裝間金屬焊料連接器。
  32. 如請求項31之方法，進一步包含在該介電殼之該底側處形成一介電間隔層，其中該介電間隔層含有將該微電子晶粒電耦接至該個別金屬接觸之金屬跡線。
  33. 如請求項31之方法，其中金屬跡線經選擇性地路由以用於將該等個別金屬接觸之一部分耦接至該微電子晶粒。
  34. 如請求項31之方法，其中形成該等個別金屬接觸進一步包含形成一自該有角度之部分向內朝向該介電殼之該側面延伸的分層部分，其中該分層部分經組態以潤濕至該外部封裝間金屬焊料連接器。
  35. 如請求項31之方法，其中該等金屬接觸之該等有角度的部分與該介電殼之該側面並列。
TW097128170A 2007-07-24 2008-07-24 具有金屬導線之微電子晶粒封裝、含有金屬導線之堆疊晶粒封裝及相關方法及系統 TWI508260B (zh)

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