CN101755336A - 具有包含用于堆叠型裸片封装的金属引线的金属引线的微电子裸片封装以及相关联的系统和方法 - Google Patents

具有包含用于堆叠型裸片封装的金属引线的金属引线的微电子裸片封装以及相关联的系统和方法 Download PDF

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CN101755336A
CN101755336A CN200880024992A CN200880024992A CN101755336A CN 101755336 A CN101755336 A CN 101755336A CN 200880024992 A CN200880024992 A CN 200880024992A CN 200880024992 A CN200880024992 A CN 200880024992A CN 101755336 A CN101755336 A CN 101755336A
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lead
indivedual
nude film
encapsulation
wires
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CN101755336B (zh
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翁妙君
谢永富
文传勇
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本文中揭示微电子裸片封装、裸片封装的堆叠系统及其制造方法。在一个实施例中，堆叠封装的系统包含：第一裸片封装，其具有底侧、第一介电壳体和第一金属引线；第二裸片封装，其具有附接到所述第一封装的所述底侧的顶侧、具有侧面的介电壳体和第二金属引线，所述第二金属引线与所述第一金属引线对准且朝向所述第一金属引线突出，且包含外表面和大体上面向所述侧面的内表面区域；以及金属焊料连接器，其将个别第一引线耦合到个别第二引线。在又一实施例中，所述个别第二引线具有“L”形状且物理上接触对应的个别第一引线。在另一实施例中，所述个别第二引线具有“C”形状且包含朝向所述第二壳体的所述侧面突出的分层部分。

Description

具有包含用于堆叠型裸片封装的金属引线的金属引线的微电子裸片封装以及相关联的系统和方法
技术领域
本发明大体上是针对具有金属引线的微电子裸片封装，且更明确地说，是针对经配置以用于堆叠裸片封装的金属引线。
背景技术
经封装的微电子组合件(例如，存储器芯片和微处理器芯片)通常包含安装到衬底且封入塑料保护覆盖物中的微电子裸片。所述裸片包含功能特征，例如存储器单元、处理器电路和互连电路。所述裸片还通常包含电耦合到功能特征的结合垫。结合垫电连接到在保护覆盖物外部延伸的引脚或其它类型的端子，用于将裸片连接到总线、电路或其它微电子组合件。
在一个常规布置中，将裸片安装到支撑衬底(例如，印刷电路板)，且用线结合将裸片结合垫电耦合到衬底的对应的结合垫。在包封后，可用焊球或其它合适的连接来将衬底电连接到外部装置。因此，衬底支撑裸片，且提供裸片与外部装置之间的电链接。
在其它常规布置中，可将裸片安装到具有连接到可拆卸式框架的导电引线指状物的引线框架。在制造期间，所述框架相对于裸片临时地将引线指状物支撑在适当位置中。每一引线指状物耦合到裸片的对应的结合垫(例如，经由线结合或金属重分布层)，且以框架和引线指状物中的每一者的一部分在包封材料外部延伸的方式来包封所述组合件。接着修整所述框架，且每一引线指状物的暴露部分将裸片连接到外部组件。一般来说，个别引线指状物可弯曲且接着耦合到对应的外部结合垫。
裸片制造商们已承受减小由裸片占据的体积却增加所得经包封组合件的容量的不断增加的压力。为了满足这些需求，裸片制造商常将多个裸片堆叠在彼此顶部上以增加在电路板或裸片所安装到的其它元件上的有限表面积内的装置的容量或性能。
附图说明
图1为包含根据本发明实施例配置且堆叠的微电子裸片封装的堆叠系统的横截面侧视图。
图2A为包含框架、释放层和支撑衬底的微电子组合件的俯视图。
图2B和图2C为图2A的组合件的部分分解横截面侧视图。
图3A为图2A的具有定位于框架的开口内的微电子裸片的组合件的俯视图。
图3B和图3C为图3A的组合件的横截面侧视图。
图4A为图3A的被包封于介电材料中的组合件的俯视图。
图4B和图4C为图4A的组合件的横截面侧视图。
图5A和图5B为在移除支撑衬底后的图4A的组合件的横截面侧视和仰视图。
图6为在形成间隔层后的图5A和图5B的组合件的横截面侧视图。
图7为在部分移除介电材料后的图6A的组合件的横截面侧视图。
图8A为在单一化和形成金属引线后的图7的组合件的横截面侧视图。
图8B为根据本发明替代实施例的在单一化和形成金属引线后的图7的组合件的横截面侧视图。
图9为包含根据本发明替代实施例配置和堆叠的微电子裸片封装的堆叠系统的横截面侧视图。
图10为根据本发明实施例的具有包含不同大小的裸片的微电子裸片封装的堆叠系统的横截面侧视图。
图11为根据本发明实施例的具有用于选择性地电耦合个别微电子裸片封装的金属迹线的堆叠系统的横截面侧视图。
图12为其中可并入有微电子裸片封装和堆叠系统的系统的示意性说明。
具体实施方式
以下参照半导体装置和用于制造半导体装置的方法来描述本发明的若干实施例的具体细节。在可包含衬底的半导体晶片上制造半导体组件，在所述半导体晶片上或其中制造微电子装置、微机械装置、数据存储元件、光学器件、读取/写入组件和其它特征。举例来说，可将SRAM、DRAM(例如，DDR/SDRAM)、快闪存储器(例如，NAND快闪存储器)、处理器、成像器和其它类型的装置构造于半导体晶片上。虽然以下相对于具有集成电路的半导体装置描述许多实施例，但制造于其它类型的衬底上的其它类型的装置可处于本发明的范围内。此外，本发明的若干其它实施例可具有与此章节中所描述的配置、组件或程序不同的配置、组件或程序。因此，所属领域的技术人员将因此理解本发明可具有带有额外元件的其它实施例，或者本发明可具有没有在下文参看图1至图12展示和描述的特征中的若干者的其它实施例。
图1为具有多个裸片封装10(个别地由参考数字10a到10d识别)的堆叠系统100的一个实施例的横截面侧视图。个别裸片封装10可包含微电子裸片12、模制介电壳体14和与壳体14侧向间隔开的金属引线16(或金属触点)。壳体14具有侧向壳体侧21、顶部壳体侧22和底部壳体侧23，且壳体14包封裸片12和引线16的至少一部分。在图1所展示的实例中，个别引线16耦合到底部壳体侧23且至少部分朝向位于上部的裸片封装或堆叠系统100的顶部突出。个别引线16可进一步包含外部引线表面25和内部引线表面26，所述内部引线表面26具有大体上面向个别侧向壳体侧21的区27。所说明的实例的内部表面区27位于个别引线16的斜角引线部分28上，所述斜角引线部分28通过所述引线的侧向引线部分29与侧向壳体侧21侧向间隔开。裸片封装10可进一步包含将引线16电耦合到裸片12的金属迹线32和封闭迹线32和裸片12的有源侧的一部分的介电间隔层34。裸片封装10还可包含耦合到迹线32的封装结合垫36。举例来说，堆叠系统100具有插入式衬底102，所述插入式衬底102具有金属凸块垫104，所述金属凸块垫104通过结合垫连接106电连接到在第一裸片封装10a处的封装结合垫36。
图1中所示的堆叠系统100的实施例包含由粘合层112a-c在对应的顶侧和底侧处物理上耦合在一起的四个堆叠裸片封装10a-d，且所述裸片封装10a-d的引线16由外部封装间连接器114电耦合在一起。举例来说，连接器114可为沿着外部引线表面25的对应于垂直对准的引线16的集合的部分和任选地沿着内部引线表面26的部分而形成的金属焊料线。因此，金属垫104经由包含引线16和连接器114的传导路径电耦合到裸片封装10a-d内的微电子裸片。在许多实施例中，且如图1中所示，对应于裸片封装10a-c的引线16延伸超出顶部壳体侧22，接触位于上部的裸片封装10上的外部引线表面25的一部分，且通过个别连接器114固持到外部引线表面25的所述部分。另外，图1中所展示的个别连接器114的实施例沿着斜角引线部分28和侧向引线部分29附接到外部引线表面25和内部引线表面26的部分。在替代实施例中，连接器114可仅沿着斜角引线部分28附接到外部引线表面25的一部分，且任选地，沿着侧向引线部分29附接到外部引线表面26的一部分。因此，连接器114的若干实施例至少从斜角引线部分28侧向向外突出，且任选地，可朝向侧向壳体侧21在个别裸片封装10之间延伸。
堆叠系统100可由一方法形成，所述方法包含堆叠裸片封装10a-d且在裸片封装10a-d的个别引线16处形成连接器114。堆叠且对准引线16可包含依次堆叠裸片封装10a-d，使得一个封装的引线16置放于邻近的裸片封装上的对应引线上方或下方，且使得下部封装的引线16朝向上部封装的引线16向上突出。可使用波焊或回焊工艺来形成连接器114。在波焊工艺中，可将抽吸的波状或级联的液相金属焊料施加于斜角引线部分28上。在回焊工艺中，可将具有金属粉末粒子的焊料膏施加于斜角引线部分28上且接着经加热以熔化金属粒子。在这些或其它焊接工艺中，金属焊料选择性地润湿(例如，当经加热时)到外部引线表面25的至少一部分，且任选地，润湿到内部引线表面26的一部分，但焊料并不润湿到壳体14的介电材料。当金属焊料冷却时，形成连接器114，且个别裸片封装10的个别引线16与上部或下部裸片封装上的对应的引线耦合。在其它实施例中，个别引线16中的一些可不物理上接触紧邻的裸片封装上的对应引线，使得仅某些引线与邻近的裸片封装互连。在任何这些实施例中，连接器114可桥接邻近的裸片的垂直对准的引线16之间的垂直间隙(例如，见图9，参考68)。举例来说，60微米或更小的垂直引线间隔距离可产生足够的表面张力以用于形成个别引线16之间的焊料桥。
一般来说，且与堆叠系统100相比，堆叠封装或裸片的常规方法已具有挑战性且花费高。举例来说，因为常规引线未经布置以面向介电壳体或朝向位于上部的裸片封装突出，所以其可难以定位，且如果未准确地对准，则可在封装下方崩塌。此外，将一个封装上的常规引线附接到对应封装上的常规引线很耗时，且需要仔细地手动操纵并检查每一常规的引线间互连。举例来说，位于上部的裸片封装上的常规的引线通常向下弯曲，使得其朝向位于下部的裸片封装上的引线突出。当常规引线经受附接工艺时，需要检查引线间连接以验证弯曲的引线相对于下部的封装正确地定位。同样，堆叠常规封装的工艺难以标准化，因为裸片是按各种大小制造，且封装同样地在大小上变化。因此，需要根据特定封装类型的布置裁定堆叠并互连常规封装的工艺。
微电子裸片封装10的若干实施例可易于堆叠且为稳固的。举例来说，在堆叠且对准了裸片封装10a-d后，对应的裸片封装的引线16自动地充分对准以供连接器114将引线相互耦合，且并不需要手动操纵来使个别引线彼此对准。另外，因为引线16从壳体14的侧面向外延伸，所以其提供位于个别引线的侧向部分与有角度部分两者上的接触表面；这使得能够使用简单的焊接工艺来使裸片封装10a-d相互耦合，且产生不需要严格的对准容限的可靠的引线间互连。同样，通过为个别引线16提供一表面以在其上压缩或回弹，裸片封装10的侧向壳体侧21可防止引线16在裸片封装堆叠期间崩塌。此外，引线16可进一步确立外部封装尺寸，使得可使用标准化的封装大小来收容多种不同大小的裸片，如以下参看图10进一步详细地解释。
图2A至图8B说明根据本发明的若干实施例形成微电子裸片封装的阶段。图2A为包含位于释放层45顶部上的金属框架41的微电子组合件40的俯视图。框架41包括引线部分42、开口43和切割道44。开口43暴露释放层45的一部分，用于邻近于引线部分42附接且定位裸片12(图1)，且切割道44提供切割或分裂路径以用于从框架41单一化个别裸片封装(参看图8A和图8B进一步地描述)。在一个实施例中，框架41可由铜制造，且可包含沿着引线部分42的选择性的铜镀层。在其它实施例中，框架41可包括多种其它金属材料，例如，铝或铝铜合金。举例来说，释放层45可为热或UV释放膜。
图2B和图2C为组合件40的部分分解横截面侧视图，其展示框架41、引线部分42、释放层45和支撑衬底47(例如，硅晶片或具有平面表面的其它类型的结构)。图2B进一步展示个别切割道44，且图2C进一步展示个别引线部分42之间的间隙48。间隙48与开口43和支撑衬底47一起界定一空穴的底侧和侧面，所述空穴随后将被填充有介电材料(参看图4A至图4C进一步描述)。个别引线部分42彼此间隔开间隔距离s1，其应足够大以防止连接器114在个别引线上侧向桥接。
图3A为在将微电子裸片附接到释放层45后的组合件40的俯视图。更具体来说，图3A展示框架41、引线部分42和开口43，其中个别裸片12置放于开口43内且邻近于引线部分42。图3B和图3C为进一步展示开口43和引线部分42的横截面侧视图，引线部分42位于裸片12的顶侧表面下，且具有厚度t1。在若干实施例中，引线部分42可具有在约50微米到250微米的范围内的厚度t1。
图4A为在介电材料50已形成于金属框架41的顶侧和裸片12的顶侧的顶部上之后的组合件40的俯视图。举例来说，介电材料50可为聚合物或塑料，其经加热且随后沉积于框架41的顶部上和间隙内。举例来说，介电材料50可经模制于框架41上和裸片12的顶侧上。图4B和图4C为展示填充裸片12周围的开口43和引线部分42之间的间隙48的介电材料50的横截面侧视图。在固化或冷却后，硬化的介电材料50应在裸片12上、裸片12的侧面与引线部分42之间的间隙内，和引线部分42之间的间隙48内形成保护性且电隔离的覆盖物。任选地，介电材料50可在裸片12上延伸厚度t2以完全包封所有裸片12和引线部分42。
图5A和图5B为在移除释放层45和支撑衬底47以暴露裸片12的底侧表面52(例如，有源侧)且暴露引线部分42的底侧表面54后的组合件40的横截面侧视图和仰视图。裸片12的底侧表面52包含电耦合到裸片12内的集成电路(未图示)的结合垫56(或有效特征)。介电材料50将裸片12固持于适当位置处，且将裸片12与引线部分42分离。
图6为在裸片12的底侧表面52处形成介电间隔层34的一实施例后的组合件40的横截面侧视图。间隔层34包含将结合垫56电耦合到引线部分42和封装结合垫36的金属迹线32。间隔层34可由例如非导电氧化物或聚合物等材料制成。举例来说，金属迹线32和封装结合垫36可由铜或铝制成。间隔层34可因此为重分布结构。还预期在某些实施例中可省略封装结合垫36。举例来说，在图1中，可省略裸片封装10b-d的封装结合垫，因为这些垫未电连接到任何外部结合垫。
图7为在通过化学蚀刻、背面研磨或化学机械抛光工艺移除介电材料50的一部分以形成壳体14后的组合件40的横截面侧视图。举例来说，介电材料50可经蚀刻以暴露内部引线表面26(图1)且形成壳体14的顶侧22和侧向壳体侧21。另外，虽然展示为具有倾斜表面，但在其它实施例中，可形成侧向壳体侧21以使得其大体上垂直于顶部壳体侧22。然而，预期侧向壳体侧21的倾斜、弯曲、锥形或其它方式分级的轮廓向个别引线提供用以在位于上部的引线或裸片封装下方弯曲或压缩的空间。同样地，倾斜的侧向壳体侧21可用以增加个别引线与侧向壳体侧21的上部部分之间的侧向间隔距离，以为在内部引线表面26上形成连接器提供较多空间。
图8A为在经由切割道44进行单一化(例如，通过修整和成形装备)以产生收容于壳体14中且耦合到个别“L”型引线16的分离的裸片12后的封装10a的一实施例的横截面侧视图。图8B展示在裸片封装60a的单一化后的替代实施例，所述裸片封装60a经形成以具有包含朝向侧向壳体侧21侧向延伸的分层引线部分67的个别“C”型引线66。在两个实施例中，侧向引线部分29远离侧向壳体侧21突出，斜角引线部分28延伸远离侧向引线部分29，使得内部表面区域27大体上与侧向壳体侧21处的表面对准，且外部引线表面25大体上背向侧向壳体侧21，且经布置以接纳外部封装间连接器。斜角引线部分28可包含多种斜角、弯曲或以其它方式倾斜的轮廓，其可任选地包含实质上垂直于侧向引线部分29的轮廓或实质上朝向侧向壳体侧21倾斜的轮廓。在图8B的实施例中，斜角引线部分28实质上与侧向引线部分29垂直，且斜角引线部分28将分层引线部分67定位于侧向引线部分29上方。这允许个别引线66容纳额外类型的外部封装间连接器，例如，金属焊料凸块(例如，见图9)。因此，裸片封装10a或60a可被置放于堆叠系统(例如，堆叠系统100)内，且可在斜角引线部分28、侧向引线部分29或分层引线部分67处的引线16或66的暴露的或以其它方式可接近的表面中的任一者处沿着裸片封装10a或60a形成连接器114。
图9为包含至少部分由粘合层112a-c物理耦合在一起的个别裸片封装60a以及裸片封装60b-d的堆叠系统200的一实施例的横截面侧视图。裸片封装60a-d的引线66由外部封装间连接器214物理且电耦合在一起。在此实施例中，连接器214包含插入于分层引线部分67与对应的裸片封装上的侧向引线部分29之间的金属焊料凸块。个别裸片封装60的引线66彼此垂直分离一跨越距离t3的间隙68，距离t3可大约为60微米或更小。个别连接器214桥接间隙68且沿着分层引线部分67以及斜角引线部分28和侧向引线部分29附接到外部引线表面25的部分。类似于堆叠系统100，可通过一方法形成堆叠系统200，所述方法包含堆叠裸片封装60a-d以使得裸片封装60a-d的引线对准，且在裸片封装60a-d的个别引线66处形成连接器214。可使用金属焊料凸块工艺来形成连接器214，所述工艺包含形成附接到外部引线表面25的部分的金属焊料点。如所展示，焊料点可经配置以沿着斜角引线部分28附接到外部引线表面25，使得连接器214定位于个别裸片封装60a-d之间，且从侧向引线部分29向外突出。在其它实施例中，连接器214可进一步耦合到内部引线表面26的部分。
图10为展示包含具有对应的微电子裸片74a-c的微电子裸片封装72a-c的堆叠系统300的一实施例的横截面侧视图。裸片封装72a-c共享共同的侧向尺寸d1，但微电子裸片74a-c具有不同的侧向尺寸d2、d3和d4(不按此次序)。在一个实施例中，堆叠系统300可为存储器模块，其包含裸片74a处的接口电路、裸片74b处的控制电路和裸片74c处的存储器。因为封装72a-c共享共同的侧向尺寸d1，所以通过堆叠优选的裸片封装或交换某些裸片封装，可创造出大量不同类型的堆叠系统。举例来说，通过使用收容于具有侧向尺寸d1的裸片封装中的较小的基于磁阻RAM(MRAM)的裸片，可组装基于DRAM的存储器模块的替代实施例。因此，可用基于MRAM的裸片封装交换基于DRAM的裸片封装72b-c。
图11为展示包含由介电间隔层84a-d分离且具有分别由第一连接器414a和第二连接器414b耦合在一起的对应第一金属引线86a-d和第二金属引线88a-d的微电子裸片封装82a-d的堆叠系统400的一实施例的横截面侧视图。在此视图中，间隔层84a包含对应的金属迹线90a-b，间隔层84c包含对应的金属迹线91a-b，间隔层84d包含单个金属迹线92，但间隔层84b不具有沿着第二封装82b的此视图的任何对应的金属迹线(即，裸片封装82a-d在其它横截面图中可具有不同金属迹线布置，使得第二封装82b不具有沿着所说明的横截面的金属迹线)。第一连接器414a应用于第一引线86a-d上以选择性地电耦合第一封装82a、第三封装82c和第四封装82d；且第二连接器414b被应用于第二引线88a-d上以选择性地电耦合第一封装82a和第三封装82c。因此，裸片封装82d的一侧和裸片封装82b的两侧与连接器414a-b电隔离。堆叠裸片封装82a-d的工艺可与参看图1和图9描述的工艺相同。形成裸片封装82a-d的工艺可类似于参看图2A至图8B描述的制造方法，但改为将金属迹线连接到每一金属引线，个别金属迹线与引线的耦合已被省略。
可作出对上述堆叠系统的许多其它类型的变化(包含与这些系统相关联的某些特征的各种组合)。举例来说，代替于结合垫连接106(图1和图9)，线结合可将堆叠系统电耦合到插入式衬底。在一些实施例中，可省略插入于堆叠封装之间的粘合层。举例来说，可单独使用外部封装间连接器以通过临时地夹持封装直到施加金属焊料且形成连接器为止而将个别裸片封装固持在一起。在其它实施例中，连接器可经配置以通过将金属焊料施加于有限数目个引线上而选择性地路由引线的个别集合。未经焊接的引线保持与堆叠系统电隔离。在一个具体实施例中，堆叠系统包含收容同一类型的裸片的裸片封装。举例来说，堆叠系统可为存储器，例如，静态动态存取存储器(SRAM)。在此实施例中，个别引线将提供对收容于个别裸片封装中的个别SRAM裸片的字线和位线存取。因此，聚集的个别SRAM裸片形成大的SRAM，其相对于相同大小的常规SRAM具有减小的占据面积。同样，堆叠系统可包含具有比所说明的实施例中呈现的封装多或少的封装的任何数目的个别微电子裸片封装。
以上参看图1至图11描述的微电子装置中的任一者可并入于无数较大或较复杂的系统490中的任一者内，代表性系统490示意性地展示于图12中。系统490可包含处理器491、存储器492(例如，SRAM、DRAM、快闪存储器或其它存储器装置)、输入/输出装置493或其它子系统或组件494。图12中展示的组件中的任一者中可包含微电子装置。所得系统490可执行广泛多种计算、处理、存储、传感器、成像或其它功能中的任一者。因此，代表性系统490包含(但不限于)计算机或其它数据处理器，例如，桌上型计算机、膝上型计算机、因特网器具、手持式装置(例如，掌上型计算机、可佩带式计算机、蜂窝式或移动电话、个人数字助理)、多处理器系统、基于处理器的或可编程的消费者电子器件、网络计算机和小型计算机。其它代表性系统490包含相机、光或其它辐射传感器、服务器和相关联的服务器子系统、显示器装置或存储器装置。在此类系统中，个别裸片可包含成像器阵列，例如，CMOS成像器。系统490的组件可收容于单个单元中或例如经由通信网络分布于多个互连的单元上。组件可因此包含本地或远程存储器存储装置和广泛多种计算机可读媒体中的任一者。
从前述内容将了解，为了说明的目的，本文中已描述了具体实施例，但尚未详细展示或描述众所周知的结构和功能以避免不必要地使前述实施例的描述模糊不清。在上下文允许的情况下，单数或复数术语也可分别包含复数或单数术语。此外，除非词“或”明确限于仅指单个项目而根据两个或两个以上项目的列表排除其它项，否则在此列表中“或”的使用应解释为包含(a)所述列表中的任何单个项目，(b)所述列表中的所有项目，或(c)所述列表中的项目的任何组合。另外，术语“包括”为包含性的，且在全文中使用以指包含至少所陈述的特征，使得不排除任何更大数量的相同特征或额外类型的其它特征。还将了解，为了说明的目的，本文中已描述了具体实施例，但在不脱离本发明的情况下，可作出各种修改。举例来说，除了其它实施例的元件以外或代替其它实施例的元件，一个实施例的许多元件可与其它实施例相组合。因此，除了由随附权利要求书限制外，本发明不受限制。

Claims (35)

1.一种微电子裸片封装的堆叠系统，其包括：
第一裸片封装，其具有底侧且包含第一微电子裸片、至少部分覆盖所述第一裸片的第一介电壳体，和耦合到所述第一裸片且具有第一外表面的个别第一金属引线；
第二裸片封装，其具有附接到所述第一封装的所述底侧的顶侧且包含第二微电子裸片、至少部分覆盖所述第二裸片且具有第二侧面的第二介电壳体，和耦合到所述第二裸片且具有第二外表面和大体上面向所述侧面的内表面区域的个别第二金属引线，其中所述个别第二引线至少大体上与所述个别第一引线对准且至少部分朝向所述第一封装突出；以及
外部封装间连接器，其将个别第一外表面的第一部分与个别第二外表面的第二部分耦合。
2.根据权利要求1所述的堆叠系统，其中所述个别第二引线具有L形状且物理上接触对应的个别第一引线。
3.根据权利要求1所述的堆叠系统，其中所述个别第二引线具有C形状且包含朝向所述第二壳体的所述侧面突出的分层部分。
4.根据权利要求1所述的堆叠系统，其中所述个别第二引线耦合到所述第二壳体的底侧。
5.根据权利要求1所述的堆叠系统，其中所述第二裸片封装的底侧进一步包含耦合到与插入式衬底相关联的金属凸块垫的封装结合。
6.根据权利要求1所述的堆叠系统，其中所述连接器从所述第一外表面的所述第一部分和所述第二外表面的所述第二部分侧向向外突出。
7.根据权利要求6所述的堆叠系统，其中所述连接器进一步在所述第一裸片封装与第二裸片封装之间朝向所述第二壳体的所述侧面延伸。
8.根据权利要求1所述的堆叠系统，其中所述第二壳体的所述侧面具有倾斜轮廓，且所述引线的所述内表面区域通过间隙与所述侧面间隔开。
9.根据权利要求1所述的堆叠系统，其中所述第二裸片封装的所述个别第二引线通过垂直间隙与所述第一裸片封装的对应的个别第一引线分离，且其中个别连接器包括桥接对应的成对的第一引线与第二引线之间的所述垂直间隙的焊料链接。
10.根据权利要求1所述的堆叠系统，其中所述第一裸片具有第一侧向尺寸，且所述第二裸片具有与所述第一侧向尺寸不同的第二侧向尺寸，且其中所述第一壳体和第二壳体具有相等的侧向尺寸。
11.一种计算系统，其包括处理器、存储器和输入/输出装置中的至少一者，其中所述计算系统包含根据权利要求1所述的堆叠系统。
12.一种微电子裸片封装的堆叠系统，其包括：
第一微电子裸片封装，其包含第一介电壳体，所述第一介电壳体具有第一底侧和附接到所述第一底侧的第一金属引线；
第二微电子裸片封装，其附接到所述第一裸片封装且包含第二介电壳体，所述第二介电壳体具有侧面、第二底侧和耦合到所述第二底侧的第二金属引线，其中个别第二引线包含远离所述侧面突出的侧向部分、弯曲部和从所述弯曲部朝向对应的个别第一引线突出的斜角部分；以及
金属焊料连接器，其附接到所述个别第一引线和所述第二引线的个别斜角部分的表面。
13.根据权利要求12所述的堆叠系统，其中所述斜角部分实质上朝向所述第二壳体的所述侧面向内倾斜，且其中所述第二引线直接接触对应的第一引线。
14.根据权利要求12所述的堆叠系统，其中个别金属焊料连接器将个别的斜角部分附接到对应的第一引线的表面。
15.一种微电子装置的堆叠系统，其包括：
第一微电子装置，其具有第一底侧和耦合到所述第一底侧的第一金属引线；
第二微电子装置，其具有侧面、第二底侧和耦合到所述第二底侧的第二金属引线，所述第二引线包含远离所述侧面侧向突出的侧向部分、朝向所述侧面侧向突出的分层部分，和将所述分层部分定位于所述侧向部分上的在所述侧向部分与所述分层部分之间的斜角部分；以及
金属焊料凸块，其处于个别第一引线与所述第二引线的个别分层部分之间。
16.根据权利要求15所述的堆叠系统，其中所述金属焊料凸块进一步在所述斜角部分的大体上背向所述第二壳体的所述侧面的表面处附接到所述第二微电子装置的所述个别第二引线。
17.根据权利要求15所述的堆叠系统，其中所述分层部分与对应的第一引线分离高达60微米的垂直距离。
18.根据权利要求15所述的堆叠系统，其中所述斜角部分实质上垂直于所述侧向部分。
19.一种微电子裸片封装，其包括：
微电子裸片；
介电壳体，其至少部分包封所述裸片且具有底侧；以及
多个个别金属触点，其耦合到所述裸片和所述壳体的所述底侧且包含远离所述壳体突出的侧向部分、远离所述底侧弯曲的弯曲部和从所述弯曲部远离所述壳体的所述底侧延伸的斜角部分，所述斜角部分具有面向所述壳体表面的第一表面和大体上背向所述壳体表面的第二表面，且其中所述第二表面经配置以接纳外部封装间连接器。
20.根据权利要求19所述的装置，其中所述连接器包括金属焊料线和金属焊料凸块中的至少一者。
21.根据权利要求20所述的装置，其中个别触点具有L形状，且所述第一表面和第二表面中的至少一者被配置为润湿表面以附接到所述连接器。
22.根据权利要求20所述的装置，其中个别触点具有C形状，所述C形状包含从所述斜角部分朝向所述壳体表面向内延伸的分层部分，所述分层部分具有第三表面，所述第三表面大体上背向所述侧向部分且被配置为润湿表面以与所述连接器附接。
23.一种制造微电子装置的方法，所述方法包括：
在具有包含第二底侧和侧面的第二介电壳体的第二裸片封装的顶部上堆叠具有包含第一底侧的第一介电壳体的第一裸片封装；
将耦合到所述第一裸片封装的所述第一底侧的第一金属引线与耦合到所述第二裸片封装的所述第二底侧的第二金属引线对准；以及
形成附接到个别第一引线的第一部分和附接到与所述第二壳体的所述侧面间隔开且朝向所述第一封装突出的个别第二引线的第二部分的个别外部封装间连接器。
24.根据权利要求23所述的方法，其进一步包括压缩所述第二金属引线，使得所述第二引线朝向所述第二壳体的所述侧面弯曲。
25.根据权利要求23所述的方法，其中形成所述连接器包括将金属焊料润湿到所述个别第一引线的所述第一部分和所述个别第二引线的所述第二部分。
26.根据权利要求25所述的方法，其进一步包括将所述金属焊料润湿到所述个别第二引线的内部和外部表面部分。
27.根据权利要求23所述的方法，其中所述个别第二引线包括L形状，且其中所述第二部分包含所述个别第二引线的斜角部分。
28.根据权利要求23所述的方法，其中所述个别第二引线包括C形状，且其中所述第二部分进一步包含一朝向所述第二壳体的所述侧面突出的层。
29.根据权利要求28所述的方法，其中形成所述连接器包括将金属焊料凸块润湿到所述个别第一引线的所述第一部分和所述个别第二引线的所述第二部分。
30.根据权利要求23所述的方法，其进一步包括将所述第二裸片封装的封装结合垫耦合到与插入式衬底相关联的金属凸块垫。
31.一种制造微电子裸片封装的方法，所述方法包括：
形成至少部分包封微电子裸片且包含底侧和侧面的介电壳体；以及
形成具有侧向部分和斜角部分的个别金属触点，所述侧向部分耦合到所述壳体的所述底侧且远离所述壳体的所述侧面突出，所述斜角部分与所述壳体的所述侧面间隔开且远离所述侧向部分延伸，使得所述斜角部分的内表面面向所述壳体的所述侧面，且其中所述斜角部分经配置以润湿到外部封装间金属焊料连接器。
32.根据权利要求31所述的方法，其进一步包括在所述介电壳体的所述底侧处形成介电间隔层，其中所述间隔层包含将所述裸片电耦合到个别触点的金属迹线。
33.根据权利要求31所述的方法，其中选择性地路由所述金属迹线以用于将所述触点的一部分耦合到所述裸片。
34.根据权利要求31所述的方法，其中形成所述个别金属触点进一步包括形成从所述斜角部分朝向所述壳体的所述侧面向内延伸的分层部分，其中所述分层部分经配置以润湿到所述连接器。
35.根据权利要求31所述的方法，其中使所述金属触点的所述斜角部分与所述壳体的所述侧面并列。
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CN102569217B (zh) * 2010-10-15 2015-10-07 海力士半导体有限公司 半导体封装件

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US20170207206A1 (en) 2017-07-20
US8536702B2 (en) 2013-09-17
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US20120241957A1 (en) 2012-09-27
US8906744B2 (en) 2014-12-09
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US10056359B2 (en) 2018-08-21
US20160099237A1 (en) 2016-04-07
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US20140015130A1 (en) 2014-01-16
CN101755336B (zh) 2013-08-28
US7843050B2 (en) 2010-11-30
US20090026600A1 (en) 2009-01-29
US20180323179A1 (en) 2018-11-08
US10396059B2 (en) 2019-08-27
KR101199224B1 (ko) 2012-11-07
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US20150091166A1 (en) 2015-04-02
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US20110068454A1 (en) 2011-03-24
US9653444B2 (en) 2017-05-16

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