TWI494996B - 使基板穿孔側壁及其他深度蝕刻特徵結構光滑之後期蝕刻反應電漿研磨 - Google Patents

使基板穿孔側壁及其他深度蝕刻特徵結構光滑之後期蝕刻反應電漿研磨 Download PDF

Info

Publication number
TWI494996B
TWI494996B TW098128841A TW98128841A TWI494996B TW I494996 B TWI494996 B TW I494996B TW 098128841 A TW098128841 A TW 098128841A TW 98128841 A TW98128841 A TW 98128841A TW I494996 B TWI494996 B TW I494996B
Authority
TW
Taiwan
Prior art keywords
etched
depth
substrate
plasma
feature
Prior art date
Application number
TW098128841A
Other languages
English (en)
Chinese (zh)
Other versions
TW201009933A (en
Inventor
法強
帕瑪西沙馬
西拉朱汀克哈林德
Original Assignee
應用材料股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 應用材料股份有限公司 filed Critical 應用材料股份有限公司
Publication of TW201009933A publication Critical patent/TW201009933A/zh
Application granted granted Critical
Publication of TWI494996B publication Critical patent/TWI494996B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H01J37/32146—Amplitude modulation, includes pulsing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW098128841A 2008-08-27 2009-08-27 使基板穿孔側壁及其他深度蝕刻特徵結構光滑之後期蝕刻反應電漿研磨 TWI494996B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/229,946 US9039908B2 (en) 2008-08-27 2008-08-27 Post etch reactive plasma milling to smooth through substrate via sidewalls and other deeply etched features

Publications (2)

Publication Number Publication Date
TW201009933A TW201009933A (en) 2010-03-01
TWI494996B true TWI494996B (zh) 2015-08-01

Family

ID=41725875

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098128841A TWI494996B (zh) 2008-08-27 2009-08-27 使基板穿孔側壁及其他深度蝕刻特徵結構光滑之後期蝕刻反應電漿研磨

Country Status (6)

Country Link
US (1) US9039908B2 (https=)
JP (1) JP5674663B2 (https=)
KR (1) KR101468614B1 (https=)
CN (1) CN102165565B (https=)
TW (1) TWI494996B (https=)
WO (1) WO2010027400A2 (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8133349B1 (en) 2010-11-03 2012-03-13 Lam Research Corporation Rapid and uniform gas switching for a plasma etch process
US8987140B2 (en) 2011-04-25 2015-03-24 Applied Materials, Inc. Methods for etching through-silicon vias with tunable profile angles
KR101867998B1 (ko) * 2011-06-14 2018-06-15 삼성전자주식회사 패턴 형성 방법
KR102021510B1 (ko) 2011-06-30 2019-09-16 어플라이드 머티어리얼스, 인코포레이티드 고속 가스 교환, 고속 가스 전환 및 프로그램 가능한 가스 전달을 위한 방법 및 장치
US9023227B2 (en) 2011-06-30 2015-05-05 Applied Materials, Inc. Increased deposition efficiency and higher chamber conductance with source power increase in an inductively coupled plasma (ICP) chamber
CN103159163B (zh) 2011-12-19 2016-06-08 北京北方微电子基地设备工艺研究中心有限责任公司 基片刻蚀方法及基片处理设备
US9041210B2 (en) 2012-06-19 2015-05-26 International Business Machines Corporation Through silicon via wafer and methods of manufacturing
US9159574B2 (en) * 2012-08-27 2015-10-13 Applied Materials, Inc. Method of silicon etch for trench sidewall smoothing
CN103887164B (zh) * 2012-12-20 2017-07-04 北京北方微电子基地设备工艺研究中心有限责任公司 一种深硅刻蚀方法
US20150087144A1 (en) * 2013-09-26 2015-03-26 Taiwan Semiconductor Manufacturing Company Ltd. Apparatus and method of manufacturing metal gate semiconductor device
KR102148336B1 (ko) 2013-11-26 2020-08-27 삼성전자주식회사 표면 처리 방법, 반도체 제조 방법 및 이에 의해 제조된 반도체 장치
CN104752331B (zh) * 2013-12-31 2018-08-07 中微半导体设备(上海)有限公司 一种硅通孔刻蚀方法
KR102233577B1 (ko) 2014-02-25 2021-03-30 삼성전자주식회사 반도체 소자의 패턴 형성 방법
TWI614806B (zh) * 2015-12-16 2018-02-11 提升矽晶穿孔製程速度之方法
US9892969B2 (en) * 2016-05-11 2018-02-13 Semiconductor Components Industries, Llc Process of forming an electronic device
GB201608926D0 (en) * 2016-05-20 2016-07-06 Spts Technologies Ltd Method for plasma etching a workpiece
GB201620680D0 (en) * 2016-12-05 2017-01-18 Spts Technologies Ltd Method of smoothing a surface
JP7281741B2 (ja) * 2019-08-23 2023-05-26 パナソニックＩｐマネジメント株式会社 素子チップのスムージング方法および素子チップの製造方法
KR102297835B1 (ko) * 2019-11-21 2021-09-02 (재)한국나노기술원 테이퍼 형태의 경사벽을 갖는 비아 홀 제조 방법
GB202020822D0 (en) * 2020-12-31 2021-02-17 Spts Technologies Ltd Method and apparatus
JP2025532820A (ja) * 2022-09-29 2025-10-03 ラム リサーチ コーポレーション 側壁の汚染物質および粗さを低減するためのポストエッチングプラズマ処理
GB202319985D0 (en) * 2023-12-22 2024-02-07 Spts Technologies Ltd Methods of treating a semiconductor substrate and apparatus
WO2025197721A1 (ja) * 2024-03-22 2025-09-25 東京エレクトロン株式会社 基板処理方法及びプラズマ処理装置
CN120809574B (zh) * 2025-09-16 2025-11-21 上海邦芯半导体科技有限公司 硬掩膜刻蚀方法及刻蚀设备
CN121123021B (zh) * 2025-11-14 2026-02-17 上海邦芯半导体科技有限公司 一种高深宽比刻蚀结构及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165032A (ja) * 2004-12-02 2006-06-22 Ulvac Japan Ltd エッチング方法および装置
JP2008034508A (ja) * 2006-07-27 2008-02-14 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900007687B1 (ko) 1986-10-17 1990-10-18 가부시기가이샤 히다찌세이사꾸쇼 플라즈마처리방법 및 장치
JPH0689880A (ja) * 1992-09-08 1994-03-29 Tokyo Electron Ltd エッチング装置
US5352324A (en) * 1992-11-05 1994-10-04 Hitachi, Ltd. Etching method and etching apparatus therefor
JP3217875B2 (ja) * 1992-11-05 2001-10-15 株式会社日立製作所 エッチング装置
US6187685B1 (en) * 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
JP4548873B2 (ja) * 1998-07-08 2010-09-22 株式会社アルバック ＴｉＮ層を等方性エッチングなしにアッシングするドライアッシング方法
US6593244B1 (en) * 2000-09-11 2003-07-15 Applied Materials Inc. Process for etching conductors at high etch rates
US6566270B1 (en) * 2000-09-15 2003-05-20 Applied Materials Inc. Integration of silicon etch and chamber cleaning processes
KR100403130B1 (ko) * 2001-12-27 2003-10-30 동부전자 주식회사 반도체 소자용 금속 배선의 클리닝 방법
US6846746B2 (en) 2002-05-01 2005-01-25 Applied Materials, Inc. Method of smoothing a trench sidewall after a deep trench silicon etch process
US20040097077A1 (en) * 2002-11-15 2004-05-20 Applied Materials, Inc. Method and apparatus for etching a deep trench
JP2004326083A (ja) * 2003-04-09 2004-11-18 Seiko Instruments Inc ミラーの製造方法とミラーデバイス
US20050170670A1 (en) * 2003-11-17 2005-08-04 King William P. Patterning of sacrificial materials
US7481943B2 (en) * 2005-08-08 2009-01-27 Silverbrook Research Pty Ltd Method suitable for etching hydrophillic trenches in a substrate
JP4812512B2 (ja) * 2006-05-19 2011-11-09 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
CN101148765B (zh) 2006-09-19 2010-05-12 北京北方微电子基地设备工艺研究中心有限责任公司 硅片蚀刻方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165032A (ja) * 2004-12-02 2006-06-22 Ulvac Japan Ltd エッチング方法および装置
JP2008034508A (ja) * 2006-07-27 2008-02-14 Sanyo Electric Co Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
CN102165565B (zh) 2015-08-12
US9039908B2 (en) 2015-05-26
CN102165565A (zh) 2011-08-24
US20100055400A1 (en) 2010-03-04
WO2010027400A3 (en) 2010-04-29
KR101468614B1 (ko) 2014-12-04
JP2012501540A (ja) 2012-01-19
JP5674663B2 (ja) 2015-02-25
KR20110052723A (ko) 2011-05-18
WO2010027400A2 (en) 2010-03-11
TW201009933A (en) 2010-03-01

Similar Documents

Publication Publication Date Title
TWI494996B (zh) 使基板穿孔側壁及其他深度蝕刻特徵結構光滑之後期蝕刻反應電漿研磨
JP7210538B2 (ja) 周期的な不動態化およびエッチングを使用する高アスペクト比の選択的横方向エッチング
US10096487B2 (en) Atomic layer etching of tungsten and other metals
TWI445081B (zh) 用於含矽薄膜的平滑ＳｉＣｏｎｉ蝕刻法
US9287124B2 (en) Method of etching a boron doped carbon hardmask
TWI733431B (zh) 用於tsv/mems/功率元件蝕刻的化學物質
JP5085997B2 (ja) プラズマエッチング性能強化方法及び装置
JP5357710B2 (ja) 基板処理方法，基板処理装置，プログラムを記録した記録媒体
JP2020529736A (ja) 水平表面上におけるＳｉＮの選択的堆積
TW201642339A (zh) 蝕刻氮化矽時達成超高選擇性之方法
CN104103510A (zh) 用于半导体制造的内部等离子体格栅
JP7639013B2 (ja) 無限選択性を有する高アスペクト比エッチング
TWI766866B (zh) 蝕刻方法
TW201601190A (zh) 蝕刻之方法
TWI713486B (zh) 蝕刻方法（二）
TWI767897B (zh) 用於蝕刻硬體之基於氫電漿清洗處理
WO2023137275A1 (en) High selectivity and uniform dielectric etch
JP2020177958A (ja) 基板処理方法及び基板処理装置
JP2025100297A (ja) 半導体基板を処理する方法および装置
JP2024521260A (ja) ３ｄ－ｎａｎｄ用の高アスペクト比エッチングのための化学物質
TW202531320A (zh) 朝向高深寬比特徵的底部之原位側壁鈍化
TW202409343A (zh) 在非晶形碳膜中的氫減少
CN121014101A (zh) 用于选择性含金属硬掩模移除的系统和方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees