TWI487113B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI487113B
TWI487113B TW101148337A TW101148337A TWI487113B TW I487113 B TWI487113 B TW I487113B TW 101148337 A TW101148337 A TW 101148337A TW 101148337 A TW101148337 A TW 101148337A TW I487113 B TWI487113 B TW I487113B
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Taiwan
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nanowire
source
drain
region
channel
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TW101148337A
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TW201344909A (zh
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Willy Rachmady
Van H Le
Ravi Pillarisetty
Jack T Kavalieros
Robert S Chau
Seung Hoon Sung
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Intel Corp
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半導體裝置及其製造方法
本發明的實施例關於半導體裝置的領域，特別關於非平面閘極全環繞裝置結構及具有變化閘極寬度的此結構的製造方法。
積體裝置製造商持續縮小電晶體裝置的特徵尺寸以取得更大的電流密度及更高的性能，對於下一代裝置，需要管理電晶體驅動電流，並降低例如寄生電容及關閉狀態洩漏等短通道效應。
例如鰭部為基礎的雙及三閘極電晶體等非平面電晶體增進短通道效應的控制。舉例而言，根據三閘極電晶體，閘極形成為相鄰於通道區的三側。由於閘極結構圍繞三表面上的鰭部，所以，電晶體基本上具有控制流經鰭部的通道區的電流之三閘極。歸因於更陡峭的次臨界電流擺幅(SS)及更小的汲極感應障壁下降(DIBL)，這些三閘極允許鰭部內更完整的空乏以及造成較低的短通道效應。近年來，已開發纏繞閘極結構，其中，閘極電極及源極/汲極接點纏繞半導體奈米佈線的全周邊，即使驅動電流增加時，仍然能夠更大幅地管理主動區中的洩漏及電容。
藉由改變閘極寬度，使驅動電流典型上調整成適合裝置規格。在雙及三閘極裝置中，改變鰭部高度。但是，新的纏繞電晶體要求不同的策略以改變奈米佈線為基礎的裝 置之閘極寬度，也要求進一步發展能整合於目前製程中的新製造方法。
說明具有可變閘極寬度的閘極全環繞電晶體及此電晶體的形成方法。參考特定細節，說明本發明的實施例，以提供完整瞭解本發明。具有此技藝的一般技術者將瞭解，不用這些特定細節仍能實施本發明。在其它情形中，未特別詳細地說明習知的半導體製程及設備，以免不必要地模糊本發明。此外，圖式中所示的不同實施例是說明表示，不一定依比例繪製。
於此說明具有一或更多主動奈米佈線及一或更多非主動奈米佈線之奈米佈線為基礎的閘極全環繞電晶體裝置。也說明此電晶體的製造方法。針對改變包括具有不同數目的奈米佈線之垂直奈米堆疊的電晶體結構的閘極寬度之方式，說明本發明的一或更多實施例。這些方式包含藉由分開奈米佈線的通道部、藉由掩埋奈米佈線的源極和汲極部、或二者，以使某些數目的奈米佈線非主動(亦即，以致於電流不流經奈米佈線的通道部份)。整體而言，藉由使某些數目的奈米佈線不致動而其它奈米佈線維持主動，改變具有複數奈米佈線之奈米佈線為基礎的結構之閘極寬度。
在一實施例中，藉由蝕刻奈米佈線的通道部份，使垂直奈米佈線堆疊非主動。垂直奈米堆疊具有奈米佈線及犠 牲材料的交錯層。犠牲閘極結構纏繞垂直奈米佈線堆疊，界定電晶體的通道區及在通道區的相對立側上的源極和汲極區。移除犠牲閘極結構以使垂直奈米佈線堆疊曝露，以及，移除犠牲材料以曝露通道區內各奈米佈線的通道部份之周邊。然後，在通道區內形成介電材料，以致於下奈米佈線的通道部份被覆蓋，而上奈米佈線的通道部份在通道區的頂部曝露。然後，藉由蝕刻以分開上奈米佈線的曝露通道部份，形成非主動的奈米佈線。移除介電材料以使下奈米佈線的各未被蝕刻的通道部份曝露。在通道區中形成功能閘極結構，繞圍下、主動的奈米佈線之未被蝕刻的通道部份。
在另一實施例中，藉由隔離非主動的通道部份，而使垂直奈米佈線堆疊中的奈米佈線非主動。在實施例中，蝕刻接點開口以曝露電晶體的源極/汲極區中垂直的奈米佈線堆疊。然後，從奈米佈線的源極/汲極部份之間移除犠牲材料。在接點開口之內形成介電材料，以致於下奈米佈線的源極/汲極部份，亦即，最接近基底的奈米佈線被掩埋。然後，源極/汲極接點形成在接點開口之內，纏繞各上奈米佈線的曝露的源極/汲極部份。未對被掩埋的下奈米佈線的源極/汲極部份作接觸。確切而言，通道部份與源極/汲極區電隔離，以及，奈米佈線是非主動的。
電晶體中各主動奈米佈線的周邊形成通道的導電部份。確切而言，電晶體的全閘極寬度是主動的奈米佈線的周長總合。非主動的奈米佈線對於全閘極寬度沒有貢獻。 因此，對於具有給定數目的奈米佈線之奈米佈線堆疊，藉由改變奈米佈線堆疊之內的主動的及非主動的奈米佈線的數目，以改變全閘極寬度。
圖1A及1B顯示根據本發明的實施例之奈米佈線為基礎的半導體裝置之實施例。圖1A是具有對閘極寬度有貢獻的二主動奈米佈線及一非主動奈米佈線之設有不連續通道部份的電晶體的二維剖面視圖。圖1B是具有對閘極寬度有貢獻的二主動奈米佈線及一非主動奈米佈線之設有掩埋的源極和汲極部份的電晶體的二維剖面視圖。雖然圖1A-1B中顯示三奈米佈線，但是，須瞭解，其它實施例可以包括更多或更少的奈米佈線。
在圖1A中，根據本發明的實施例，複數垂直堆疊的奈米佈線110配置在基底102的上方。閘極結構纏繞各主動奈米佈線110A，界定配置在各主動奈米佈線110A中的通道部份113A及裝置的通道區140。源極和汲極區145配置在各通道區140的相對側上。閘極結構包括閘極介電層143和閘極電極144。藉由完全地纏繞各主動奈米佈線110A的通道部份113，閘極結構藉由完全地切斷寄生電容漏電路徑而比平面及鰭為基礎的電晶體增加閘極控制，藉以改良短通道效應。在本發明的實施例中，非主動的奈米佈線110B具有不連續的通道部份113B，以致於電流不在源極與汲極部份111B之間流動。在實施例中，各奈米佈線110的源極和汲極部份111由犠牲材料112分開。最底部的奈米佈線110A的源極和汲極部份111A設於基部 鰭106上。底部閘極隔離部152隔離閘極結構與基底102。
基底102由適用於半導體裝置製造的材料構成。在一實施例中，使用塊體半導體基底，形成結構。基底102包含但不限於矽、鍺、矽-鍺、或III-V族化合物半導體材料。在另一實施例中，使用絕緣體上矽(SOI)基底，形成結構。SOI基底包含下塊體基底，配置在下塊體基底上的中間絕緣體層，以及頂部單晶層。中間絕緣體層包括二氧化矽、氮化矽、或氧氮化矽。頂部單晶層可為任何適當的半導體材料，例如上述列出用於塊體基底的半導體材料。
在實施例中，奈米佈線110及犠牲材料112均為半導體材料。在一此實施例中，奈米佈線及犠牲材料112是單晶的以及具有晶格常數。在實施例中，犠牲材料112為相對於奈米佈線110而被選擇性地蝕刻的任何材料。在實施例中，犠牲材料112是在奈米佈線110中產生應力的材料。奈米佈線110及犠牲材料112均為例如但不限於矽、鍺、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、及InP等材料。在特定實施例中，奈米佈線110是矽，以及，犠牲材料112是SiGe。在另一特定實施例中，奈米佈線110是鍺，以及，犠牲材料112是SiGe。在實施例中，奈米佈線110包括應力材料，特別是在通道部份113中。
在實施例中，各奈米佈線110可以如下所述般尺寸化 成為佈線或是條紋，以及，具有非方形的或圓化角落。各奈米佈線110的厚度決定電晶體裝置的電特徵、集成度及性能。在實施例中，各奈米佈線110足夠厚以避免造成高通道電阻之過多的表面散射。各奈米佈線110也足夠薄以允許電晶體以完全空乏方式操作。在實施例中，從剖面觀點而言，奈米佈線的尺寸是奈米級。舉例而言，在特定實施例中，奈米佈線110的最小尺寸小於約20 nm。
電晶體的閘極寬度決定電晶體的驅動電流容量。對於奈米佈線為基礎的電晶體，主動的奈米佈線的通道區的周邊之累積長度決定用於該電晶體的閘極寬度。由於奈米佈線的剖面面積受限於空乏及表面散射，所以，藉由增加或降低電晶體中給定尺寸的主動奈米佈線的數目，以增加或降低閘極寬度。藉由增加閘極寬度，較大數目的主動奈米佈線110A允許電晶體裝置較大的驅動電流容量。但是，主動的奈米佈線的數目受限於包括主動的及非主動的奈米佈線之奈米佈線堆疊的總高度之限制。隨著奈米佈線堆疊的高度增加，非集成的風險增加。奈米佈線電晶體具有從1至10的奈米佈線。在實施例中，如圖1A所示，奈米佈線堆疊包括三奈米佈線。
在實施例中，閘極介電層143包括高k介電材料。舉例而言，在一實施例中，閘極介電層143由例如但不限於氧化鉿、氧氮化鉿、矽酸鉿、氧化鑭、氧化鋯、矽酸鋯、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、鉛鈧鉭氧化物、鈮酸鉛鋅、或其組合所構成。
在實施例中，閘極電極144由例如但不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鈷、鎳、或導電金屬氧化物等材料構成。在特定實施例中，閘極電極由形成於金屬功函數設定層上方的非功函數設定填充材料構成。在實施例中，閘極電極144包括p型功函數金屬。在另一實施例中，閘極電極144包括n型功函數金屬。
在一態樣中，如圖1A所示，奈米佈線110的源極和汲極部份111以及在源極與汲極部份111之間的犠牲材料112形成異質源極和汲極區145。在實施例中，異質源極和汲極區145可以經過摻雜或未經摻雜。
在另一態樣中，從源極與汲極部份111之間移除犠牲層112，以致於源極和汲極區145包括奈米佈線110的源極和汲極部份111。然後，形成金屬接點，纏繞源極和汲極部份111A以建立主動奈米佈線110A。
在另一態樣中，形成同質源極和汲極區145。在實施例中，奈米佈線110和犠牲材料112的源極和汲極部份111都從源極和汲極區145移除。在特定實施例中，從基底生長半導體材料，形成對於各奈米佈線110的通道部份113的接點。在實施例中，同質源極和汲極區145可以經過摻雜或未經摻雜。在另一特定實施例中，在源極和汲極區145之內形成金屬物，形成對奈米佈線110的通道部份113的接點。
側壁間隔器134形成於閘極結構的垂直側壁上，以補 償源極和汲極區的選加摻雜及/或使閘極電極與後續生長於源極和汲極區上的任何磊晶材料相絕緣。側壁間隔器134由例如但不限於二氧化矽、氧氮化矽、或氮化矽等絕緣的介電材料構成。
圖1B顯示本發明的另一實施例，其中，非主動的奈米佈線的通道部份與電晶體的源極和汲極區電隔離。根據本發明的實施例，複數垂直堆疊的奈米佈線110配置在基底102上方。包括閘極電極144及閘極介電質143之閘極結構界定裝置的通道區140以及通道區的相對立側上的源極和汲極區145。主動的奈米佈線110A具有通道部份113A以及源極和汲極部份111A。非主動的奈米佈線110B具有通道部份113B以及非主動的源極和汲極部份111B。
在實施例中，各主動的奈米佈線110A的源極和汲極部份111A由源極和汲極接點148完全圍繞。在實施例中，非主動的奈米佈線110B未電耦合至源極和汲極區145。在實施例中，各非主動的奈米佈線110B的源極和汲極部份111B由介電材料146掩埋，以經過源極和汲極部份11B電隔離通道部份113B。在實施例中，如圖1B所示，所有奈米佈線110均具有完好如初的通道部份113。
在實施例中，源極和汲極接點148由金屬物製成。金屬物可為例如鎳、鈷、或鈀等純金屬或是例如金屬-金屬合金或金屬-半導體合金(例如矽化物材料)等合金。在實施例中，在形成接點金屬之前，在溝槽內形成氮化鈦底 層。
在本發明的另一態樣中，提供奈米佈線為基礎的半導體裝置的製造方法。圖2A-2K顯示代表根據本發明的實施例之製造奈米為基礎的電晶體之方法中的不同操作之三維透視圖及二維剖面視圖。
半導體裝置的製造方法包含在基底上方形成複數奈米佈線。圖2A顯示形成三條奈米佈線的特定實例。設置具有垂直奈米佈線堆疊208配置於上的基底202。在實施例中，垂直奈米佈線堆疊208包括奈米佈線210材料及犠牲材料212的交錯層。在實施例中，奈米佈線堆疊包括三條奈米佈線210及二層犠牲材料212。
在實施例中，藉由在塊體半導體基底的表面上生長交錯的材料層，形成奈米佈線210及犠牲材料212，然後，以例如掩罩及電漿蝕刻製程，將這些層圖型化以形成鰭型式結構。在實施例中，在單晶矽基底上形成交錯層。在另一實施例中，在具有頂部SiGe層的塊體矽基底上形成交錯層。在實施例中，鰭型式結構包括配置在基部鰭206上的垂直奈米佈線堆疊208。在實施例中，基部鰭206從基底202的頂部部份形成，其中，基底材料作為最底部奈米佈線之下方的犠牲材料。在另一實施例中，基部鰭206由與犠牲材料212相同的材料形成。在另一實施例中，基部鰭206由基底202及犠牲材料212等二材料的結合形成。犠牲材料212由基底202的表面形成或是沉積於基底202的表面，以形成塊體鰭206的一部份。塊體鰭206也包括 複數緩衝層，這些緩衝層用以使晶格常數從基底至垂直奈米佈線堆疊208自其生長的表面漸變。
在實施例中，基底202也包含淺溝槽隔離(STI)區204，SIT區204用以降低相鄰裝置之間的漏電流。STI區204由傳統的半導體圖型化方法形成(例如，微影術及蝕刻)。STI區204包括例如氧化矽、氮化矽、氧氮化矽、及其組合等介電材料。
在另一實施例中，垂直奈米佈線堆疊208形成在SOI基底上，SOI基底包括底部基底、中間絕緣層、及頂部單晶半導體層。在實施例中，包括垂直奈米佈線堆疊208的層從頂部單晶半導體層生長，然後，被圖型化成為鰭型式結構。在實施例中，中間絕緣層作為隔離層。
在實施例中，奈米佈線210及犠牲材料212均由具有晶格常數的單晶材料形成。在實施例中，奈米佈線210及犠牲材料212由半導體材料形成。在實施例中，犠牲材料212由相對於奈米佈線210被選擇性地蝕刻之材料形成。在實施例中，選取犠牲材料212以在奈米佈線210中產生應力。理想地，在垂直奈米佈線堆疊208中奈米佈線210及犠牲材料212均由單晶半導體材料形成，單晶半導體材料為例如但不限於Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb及InP。在實施例中，奈米佈線210是矽以及犠牲材料212是SiGe，以形成n型電晶體。在實施例中，奈米佈線210是未經摻雜的鍺以及犠牲材料212是SiGe，以形成p型電晶體。
垂直奈米佈線堆疊208具有高度224、寬度222、及長度220。垂直奈米佈線208形成為具有小於30 nm的寬度222以及理想上小於25 nm。在實施例中，高度224小於例如鰭倒塌、鰭輪廓扭曲、及鰭關鍵尺寸不良均勻性等集成議題開始發生的高度。奈米佈線210及犠牲材料212的厚度也影響高度224。在實施例中，奈米佈線210及犠牲材料212足夠薄以取得小於集成議題開始發生時的高度之高度224。
接著，犠牲閘極介電層228是沉積於垂直奈米佈線堆疊208的頂部及側壁上的覆蓋層。犠牲閘極介電層228沉積至從約10-50的厚度。在特定實施例中，犠牲閘極介電層228是例如氧化矽、氮化矽、及氧氮化矽等介電材料。以習知的化學汽相沉積(CVD)法，沉積犠牲閘極介電層228。如圖2B中所示，然後，犠牲閘極材料250覆蓋沉積於結構上，包含犠牲閘極介電層228。犠牲閘極端250沉積至超過垂直奈米佈線堆疊208的高度。在實施例中，犠牲閘極材料250由例如多晶矽等半導體材料形成。
接著，根據圖2C中所示之本發明的實施例，使用傳統的微影術及蝕刻方法，將犠牲閘極材料250圖型化，形成犠牲閘極電極230。用以形成犠牲閘極電極230之犠牲閘極材料250的蝕刻使垂直奈米佈線堆疊208的源極和汲極區上的犠牲閘極介電層228曝露。在犠牲閘極230的圖型化及形成期間，犠牲閘極介電層228作為蝕刻停止層，藉以防止對垂直奈米佈線堆疊208的源極和汲極區造成傷 害。在實施例中，犠牲閘極介電層228及犠牲閘極電極230由具有充分不同的蝕刻選擇性之材料形成，以致於犠牲閘極介電層228在犠牲閘極電極230的蝕刻期間作為蝕刻停止層。
接著，使用例如傳統的濕蝕刻製程，將犠牲閘極介電層228從垂直奈米佈線堆疊208的頂部及側壁移除。在實施例中，犠牲閘極介電層228是使用稀釋的HF濕蝕刻而被移除的氧化矽層。在犠牲閘極結構的形成之後，舉例而言，如此技藝中熟知般，以尖端佈植或是暈佈植，將奈米佈線210摻雜。
根據圖2C中所示的本發明的實施例，在犠牲閘極電極230的側壁上形成成對的側壁間隔器234，以補償源極和汲極區的選加摻雜及/或使閘極電極與後續生長於源極和汲極區上的任何磊晶材料相絕緣。使用此技藝中所知的形成選取間隔器之習知方法，形成成對的側壁間隔器234。側壁間隔器234可為任何適當的介電材料，例如但不限於氧化矽、氮化矽、氧氮化矽及其組合。在實施例中，側壁間隔器234形成為從20至100厚。
在實施例中，源極和汲極區245是異質的，包括如圖2C中所示的垂直奈米佈線堆疊的源極和汲極部份211及犠牲材料212。在實施例中，在源極和汲極區245之內，在垂直奈米佈線堆疊208的表面上生長磊晶材料。異質的源極和汲極區245可以經過摻雜或未被摻雜。在實施例中，以離子佈植，摻雜異質的源極和汲極區245。
在另一實施例中，源極和汲極區245包括奈米佈線210的源極和汲極部份211。在實施例中，從源極和汲極區245之內移除犠牲材料212及至少部份基部鰭206，以曝露奈米佈線210的源極和汲極部份211的周邊。在實施例中，接點纏繞奈米佈線210的曝露的源極和汲極部份211。在實施例中，接點包括導電金屬物。
在另一實施例中，源極和汲極區245是同質的。移除源極和汲極部份211、犠牲材料212、及至少部份基部鰭206，以形成同質源極和汲極區。然後，材料沉積於源極和汲極區之內，以形成與各奈米佈線210的通道部份213之接觸。在實施例中，從基底生長單晶半導體材料以形成升起的源極和汲極區。在實施例中，同質源極和汲極區245提供應力給奈米佈線210的通道部份213。假使需要時，半導體材料可為原地摻雜的。在另一實施例中，藉由沉積金屬物以形成與奈米佈線210的通道部份213的接觸，形成同質源極和汲極區245。
如圖2D中所示，根據本發明的實施例，層間介電(ILD)層238覆蓋沉積於基底上。使用CVD，沉積覆蓋ILD層238。在實施例中，ILD層238由任何熟知的介電材料形成，例如但不限於未經摻雜的氧化矽、經過摻雜的氧化矽(例如，BPSG、PSG)、氮化矽、及氧氮化矽。然後，使用習知的化學機械平坦化方法，背拋光ILD層238以使犠牲閘極電極230的頂部及側壁間隔器234的頂部曝露。
接著，如圖2E中所示的實施例中所示般，移除犠牲閘極電極230以使通道區240之內的垂直奈米佈線堆疊208上的犠牲閘極介電質228。圖2E是延著線A-A’之圖2D中所示的實施例之二維、剖面視圖。在犠牲閘極電極230的移除期間，ILD層238保護源極和汲極區245之內的垂直奈米佈線堆疊208。此外，在通道區240之內的垂直奈米佈線堆疊208上的犠牲閘極介電層228作為蝕刻停止，在犠牲閘電極230移除期間，保護垂直奈米佈線堆疊208。使用例如電漿乾蝕刻或濕蝕刻等傳統的蝕刻方法，移除犠牲閘電極230。在實施例中，使用例如TMAH溶液等濕蝕刻劑以選擇性地移除犠牲閘電極。
在實施例中，接著移除犠牲閘介電層228以曝露通道區240之內的垂直奈米佈線堆疊208。使用傳統的蝕刻方法，移除犠牲閘極介電層228。在實施例中，犠牲閘極介電層228是可由稀釋的HF濕蝕刻移除之氧化矽。
接著，如圖2F所示般，從通道區240之內的奈米佈線210之間移除犠牲材料212。在實施例中，從奈米佈線210之間完全地蝕刻犠牲材料212。在實施例中，蝕刻製程曝露通道區240之內的奈米佈線210的所有表面。如圖2F所示，犠牲材料212的移除在相鄰的奈米佈線210之間留下空乏。使用對奈米佈線210有選擇性的任何習知的蝕刻劑，移除犠牲材料212。對於犠牲材料相較於奈米佈線材料，蝕刻劑的選擇率大於50：1。在實施例中，選擇率大於100：1。在奈米佈線210是矽及犠牲材料212是矽 鍺的實施例中，使用例如但不限於含水羧酸/硝酸/HF溶液及含水的檸檬酸/硝酸/HF溶液等濕蝕刻劑，選擇性地移除犠牲材料212。在奈米佈線210是鍺及犠牲材料212是矽鍺的實施例中，使用例如但不限於氫氧化銨(NH4 OH)、氫氧化四甲銨(TMAH)、乙二胺鄰苯二酚(EDP)、或氫氧化鉀(KOH)溶液等濕蝕刻劑，選擇性地移除犠牲材料212。
然後，如圖2G中所示的實施例所示般，將介電材料242覆蓋沉積於基底上，圍繞奈米佈線210及完全地填充通道區240。介電材料242完全地填充奈米佈線210之間的空乏，也填充最底部奈米佈線與基底202的頂部表面之間的空間。介電材料242也形成於ILD層238的頂部表面上。在實施例中，介電材料242由例如但不限於氧化矽、氮化矽、及氧氮化矽等任何習知的介電材料形成。在特定實施例中，介電材料242由二氧化矽形成。理想上，使用例如低壓化學汽相沉積(LPCVD)、原子層沉積(ALD)、介電質上旋轉塗敷製程、或是這些製程的組合等高保形沉積方法，形成介電材料242，以確保奈米佈線210之間的空乏被完全填充。
接著，根據本發明的實施例，介電材料242從ILD層238的表面被移除、以及接著部份地凹陷於通道區240之內。介電材料242凹陷至通道區240之內的深度，此深度足以完全地曝露各奈米佈線210的通道部份213。由必須不被致動之奈米佈線210的數目決定曝露的通道部份213 的數目，以取得所需的電晶體閘極寬度。在圖2H所示的實施例中，曝露上奈米佈線210B的通道部份213B的全周邊，而各下奈米佈線210A的通道部份213A維持由介電材料242完全掩埋。在實施例中，使用計時HF濕蝕刻，將介電材料242蝕刻。
然後，根據本發明的實施例，分開上奈米佈線210B的曝露通道部份213B。在實施例中，上奈米佈線210B的曝露通道部份213B被蝕刻達到上奈米佈線210B無法在源極與汲極區245之間導通電流的程度。在實施例中，如圖2I中所示般，完全地移除通道部份213B。以對介電材料242有選擇性的任何蝕刻製程，蝕刻通道部份213B。以濕或乾蝕刻製程，蝕刻通道部份213B。介電材料242保護各下奈米佈線210A的通道部份213A，以致於它們不被蝕刻。
然後，如圖2J中所示的實施例中所示般，介電材料242接著又凹陷以曝露各下奈米佈線210A的受保護通道部份213A。介電材料242餘留在基底202上以形成底部閘極隔離252。底部閘極隔離252的厚度取決於介電材料242被蝕刻的時間長度。在實施例中，足夠長時間地執行濕蝕刻凹陷，以取得厚至足以隔離基底202的頂表面免於電容地耦合後續形成的閘極電極之電容底部閘極隔離厚度。在實施例中，足夠長時間地執行濕蝕刻凹陷，以取得薄至足以允許後續形成的閘極介電層與閘極電極形成為全圍繞各下奈米佈線210A的通道部份213A之底部閘極隔 離厚度。
接著，根據本發明的實施例，閘極介電層243形成為圍繞各下奈米佈線210A的通道部份213A。如先前所述般，閘極介電層243由任何習知的閘極介電材料形成。使用例如原子層沉積(ALD)等高保形沉積製程，形成閘極介電層243，以確保形成圍繞各下奈米佈線210A的通道部份213A之具有均勻厚度的閘極介電層。閘極介電層243可為例如高k介電質等任何適當材料。在特定實施例中，閘極介電層243是沉積至10-60之間的厚度之氧化鉿。
接著，閘極電極材料覆蓋地沉積於閘極介電層243以形成閘極電極244。閘極電極244可由如先前所述之任何習知的閘極電極材料形成。使用例如ALD等高保形沉積製程，沉積閘極電極材料243，以確保閘極電極244形成在閘極介電層243上而圍繞下奈米佈線210A的通道部份213A及在下奈米佈線210A的通道部份213A之間。然後，將ILD層238的頂部上之閘極電極材料及閘極介電層243化學機械地平坦化，直到ILD層238的頂部表面如圖2K中所示地露出為止，而形成電晶體裝置。根據本發明的實施例，各通道部份213A的周邊之累積長度決定電晶體的閘極寬度。
在本發明的另一實施例中，如圖3A-3C所示，藉由蝕刻各別的通道部份，使一條以上的奈米佈線非主動。在一實施例中，提供如參考圖2A-2G之顯示及上述所述般 形成的結構。在實施例中，介電層342從ILD層338的頂表面移除以及凹陷至通道區340內，以曝露各上奈米佈線310B的通道部份313B。通道部份313B的全周邊曝露。下奈米佈線310A的通道部份313A維持掩埋在介電層342中。然後，各上奈米佈線312B的通道部份313B被充分地蝕刻，以致於上奈米佈線312B無法在源極與汲極區345之間。在實施例中，如圖3B中所示般，通道部份313B被完全地蝕刻。以圖2J中的上奈米佈線210B的通道部份213B的蝕刻有關的上述製程，蝕刻各上奈米佈線310B的通道部份313B。
然後，如圖3C中所示的實施例中所示般，介電材料342凹陷於通道區之內以曝露下奈米佈線310A的通道部份313A。在實施例中，將介電材料342蝕刻至足以允許形成全圍繞通道部份313A的全周邊之閘極介電質及閘極電極層之深度。在實施例中，部份介電材料342留在下奈米佈線310A之下方的基底302的表面上以形成底部閘極隔離區352。
然後，根據本發明的實施例，閘極介電質343及閘極電極344形成在通道區340之內。如圖2K中所示，關於閘極電極243及閘極電極244之上述所述般，形成閘極介電質343及閘極電極344。閘極介電質343及閘極電極344全纏繞下奈米佈線310A的通道部份313A，以致於下奈米佈線310A的周邊決定用於顯示之電晶體的實施例之閘極寬度。
在另一實施例中，其中，例如圖3A-3C中所示般，二奈米佈線非主動，介電材料342從ILD層338的頂表面移除以及凹陷至溝槽內，以曝露僅最上方的奈米佈線310B的通道部份313B。然後，以例如上奈米佈線210B有關的上述所述的製程，蝕刻單一曝露的通道部份313B。接著，在實施例中，介電材料342進一步凹陷以曝露第二上奈米佈線310B的通道部份313B。然後，以例如關於上奈米佈線210B之上述所述的製程，蝕刻單一曝露的通道部份313B，以形成圖3B中所示的結構。在實施例中，然後，如同下奈米佈線210A有關的上述所述及圖3C中所示般，介電材料342從下奈米佈線310A的通道部份313A的表面移除，以致於形成功能閘極結構，纏繞完好如初的通道部份313A。因此，形成具有二非主動的上奈米佈線310B及一主動的下奈米佈線310A之電晶體。
如圖2A-2K及3A-3C中上述所示般，具有相同數目的奈米佈線的電晶體的閘極寬度可以改變。在本發明的其它實施例中，奈米佈線堆疊可以含有更多或更少的奈米佈線。一般而言，至少一奈米佈線是主動的，但是，揭示的製程可以用以形成具有零條主動奈米佈線的犠牲電晶體。
在本發明的另一態樣中，藉由將一或更多奈米佈線的通道部份與裝置的源極/汲極區隔離，改變奈米佈線為基礎的電晶體的閘極寬度。圖4A-E顯示代表根據本發明的實施例之奈米佈線為基礎的電晶體之製造方法的不同操作之二維剖面視圖。
如圖4A中所示般，提供包括複數以垂直堆疊沉積於基底402上的奈米佈線410的結構。包括閘極介電質443及閘極電極444的閘極結構纏繞各奈米佈線410的通道區。在實施例中，閘極介電質443是犠牲閘極介電質，以及，閘極電極444是犠牲閘極電極。底部閘極隔離區452將閘極結構與基底402相隔離。各奈米佈線410的源極和汲極部份411由鰭基部鰭部406及犠牲材料412支撐。ILD層438覆蓋源極和汲極區445中的頂部奈米佈線。如同參考圖2A-2K之上述中所述般，形成結構，省略操作，因而奈米佈線的通道部份被分開。
如圖4B中所示般，為形成源極和汲極接點，從ILD層438的表面至基底402的表面蝕刻開口460，移除ILD層438、犠牲材料412及基部鰭部406等的部份，以曝露各奈米佈線410的源極和汲極部份411的全周邊。以對奈米佈線410材料有選擇性的蝕刻製程，移除ILD層438、犠牲材料412、及鰭部406。在實施例中，使用微影製程，蝕刻開口406。
如圖4B所示，在移除犠牲材料412之後，奈米佈線410由閘極結構支撐。在實施例中，奈米佈線410由相鄰於源極/汲極部份411的犠牲閘極結構增加地支撐。在另一實施例中，奈米佈線410又由與相鄰的裝置相關連的功能閘極結構支撐。在另一實施例中，奈米佈線410終止於源極/汲極部份411的端部。
接著，如圖4C所示般，介電材料456覆蓋地沉積於 基底上，完全地填充開口460。然後，如圖4D中所示般，從ILD層438的表面蝕刻介電材料446，且介電材料446凹陷於開口460之內以曝露對應於所需的主動奈米佈線的數目之源極和汲極部份411的數目。在實施例中，各上奈米佈線410A的源極和汲極部份411A的周邊完全地曝露。在實施例中，介電材料446完全地覆蓋在開口460的底部之下奈米佈線410B的源極和汲極部份411B。
如圖4E所示，在實施例中，源極和汲極接點458形成在開口460中。在實施例中，源極和汲極接點458全纏繞各主動奈米佈線410A的源極和汲極部份411A。源極和汲極接點458由任何適合確保各上奈米佈線410A的源極和汲極部份411A之保形接點的方法所形成。在實施例中，以CVD沉積源極和汲極接點458。在實施例中，源極和汲極接點458由關於圖1B中所示的源極和汲極接點158之上述中所述的金屬物形成。在另一實施例中，在形成接點之前，從開口460之內移除源極和汲極部份411A。在實施例中，金屬沉積於開口460之內以形成與通道部份411A的接點。在開口460的底部之介電材料防止源極和汲極接點458與非主動的奈米佈線410B的源極和汲極部份411B電接觸。
在閘極介電質443是犠牲閘極介電質、以及閘極電極444是犠牲閘極電極的實施例中，在形成接點458之後，以更換閘極製程，形成功能閘極。
如此，形成包括二主動奈米佈線410A及一非主動奈 米佈線410B的電晶體。電晶體的閘極寬度等於主動奈米佈線410A的通道部份411A的周邊之結合長度。雖然圖4A-4E顯示通道部份與源極區和汲極區相隔離，但是，須瞭解，僅與源極區或汲極區隔離即足以使奈米佈線非主動。
在奈米佈線堆疊中主動及非主動的奈米佈線之數目可以改變，以取得具有不同閘極寬度的電晶體。在圖5A所示的實施例中，電晶體包括配置在基底502上方的奈米佈線510的垂直堆疊。包括閘極介電層543及閘極電極544的閘極結構纏繞奈米佈線510的通道部份513。閘極結構具有側壁間隔器534，顯示為在奈米佈線的頂部上方。奈米佈線堆疊具有一條主動的奈米佈線510A以及二條非主動的奈米佈線510B，其中，各非主動的奈米佈線510B的源極和汲極部份511B掩埋在介電材料546中，以致於通道部份513B與源極和汲極區545電隔離。源極/汲極接點558形成為纏繞主動的奈米佈線510A的源極和汲極部份511A。主動的奈米佈線510A的通道部份513的周邊決定電晶體的閘極寬度。
在另一實施例中，如圖5B中所示，介電材料546被蝕刻，以致於一部份維持相鄰於閘極結構。介電材料包含在閘極與源極和汲極接點之間的米勒(Miller)電容。在實施例中，在覆蓋沉積介電材料546於結構上之後，如同參考圖4C之上述所述般，介電材料被拋光成與閘極結構的上表面齊平。然後，在相鄰於閘極結構的介電材料上形 成掩罩。然後，接點溝槽被蝕刻以曝露主動的奈米佈線510A的源極和汲極部份，而一部份介電材料546保留在與閘極結構相鄰的源極/汲極區中。在實施例中，溝槽蝕刻曝露部份源極和汲極部份，而源極/汲極部份的另一部份在相鄰於閘極結構的介電材料546之間延伸。然後，接點形成在溝槽中、在覆蓋非主動的奈米佈線510B的源極和汲極部份之介電材料546的上方。相鄰於閘極結構的介電材料的寬度延著溝槽的深度而變，從0至500寬。
在另一實施例中，如圖5C中所示般，ILD層538、犠牲材料512、及基部鰭506等的部份保留成相鄰於閘極結構。在接點溝槽的蝕刻期間，藉由覆蓋ILD層538的部份，可以保留ILD層538、犠牲材料512、及基部鰭506等的部份。在本實施例中，犠牲材料512是絕緣的或半絕緣的，以致於犠牲材料512不產生或實際上不產生漏電路徑、以及以致於非主動的奈米佈線的通道部份維持與裝置的源極和汲極區電隔離。
圖6顯示根據本發明的一實施之計算裝置600。計算裝置600容納主機板602。主機板602包含多個組件，多個組件包括但不限於處理器604及至少一通訊晶片606。處理器604實體地及電耦合至主機板602。在某些實施中，至少一通訊晶片606也實體地及電耦合至主機板602。在另外的實施中，通訊晶片606是處理器604的一部份。
取決於其應用，計算裝置600包含可以或不可以實體 地及電耦合至主機板602的其它組件。這些其它組件包含但不限於依電性記憶體(例如，DRAM)、非依電性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位訊號處理器、密碼處理器、晶片組、天線、顯示器、觸控幕顯示器、觸控幕控制器、電池、音頻編解碼、視頻編解碼、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、揚音器、相機、及大量儲存裝置(例如硬碟機、光碟(CD)、數位多樣式光碟(DVD)、等等)。
通訊晶片606能夠無線通訊以用於對計算裝置600傳輸資料。「無線」一詞及其衍生詞用以說明經由使用通過非固體介質之調變的電磁輻射來傳輸資料的電路、裝置、系統、方法、技術、通訊通道、等等。此詞並非意指相關連裝置未含有任何接線，但是，在某些實施例中，它們可能未含任何接線。通訊晶片606可以實施任何無線標準或是通信協定，包含但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期進化(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生、以及以3G、4G、5G、及更新的世代來標示的任何其它無線通信協定。計算裝置600包含複數通訊晶片606。舉例而言，第一通訊晶片606可以專用於較短範圍的無線通訊，例如Wi-Fi及藍牙，而第二通訊晶片606可以專用於較長範圍的無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、等等。
計算裝置600的處理器604包含封裝在處理器604之內的積體電路晶粒。在本發明的某些實施中，處理器的積體電路晶粒包含根據本發明的實例之一或更多具有設有至少一非主動的奈米佈線之奈米佈線垂直堆疊的閘極全環繞電晶體。「處理器」一詞意指處理來自暫存器及/或記憶體的電子資料以將電子資料轉換成儲存在暫存器及/或記憶體中的其它電子資料之任何裝置或裝置的一部份。
通訊晶片606也包含封裝於通訊晶片606之內的積體電路晶粒。根據本發明的另一實施，通訊晶片的積體電路晶粒包含根據本發明的實例之一或更多具有設有至少一非主動的奈米佈線之奈米佈線垂直堆疊的閘極全環繞電晶體。
在其它實施中，容納於計算裝置600之內的另一組件含有積體電路晶粒，積體電路晶粒包含根據本發明的實例之一或更多具有設有至少一非主動的奈米佈線之奈米佈線垂直堆疊的閘極全環繞電晶體。
在各式各樣的實施中，計算裝置600可以是膝上型電腦、筆記型電腦、超薄筆記型電腦、智慧型電話、平板電腦、個人數位助理(PDA)、及超薄行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或是數位攝影機。在又其它實施中，計算裝置600可為處理資料的任何其它電子裝置。
102‧‧‧基底
106‧‧‧基部鰭
110‧‧‧垂直堆疊奈米佈線
110A‧‧‧主動奈米佈線
110B‧‧‧非主動奈米佈線
111‧‧‧源極和汲極部份
111A‧‧‧源極和汲極部份
111B‧‧‧源極和汲極部份
112‧‧‧犠牲材料
113‧‧‧通道部份
113A‧‧‧通道部份
113B‧‧‧通道部份
134‧‧‧側壁間隔器
140‧‧‧通道區
143‧‧‧閘極介電層
144‧‧‧閘極電極
145‧‧‧源極和汲極區
146‧‧‧介電材料
148‧‧‧源極和汲極接點
152‧‧‧底部閘極隔離
202‧‧‧基底
204‧‧‧溝槽隔離區
206‧‧‧基部鰭
208‧‧‧垂直奈米佈線堆疊
210‧‧‧奈米佈線
210A‧‧‧下奈米佈線
210B‧‧‧上奈米佈線
211‧‧‧源極和汲極部份
212‧‧‧犠牲材料
213‧‧‧通道部份
213A‧‧‧通道部份
213B‧‧‧通道部份
220‧‧‧長度
222‧‧‧寬度
224‧‧‧高度
228‧‧‧犠牲閘極介電層
230‧‧‧犠牲閘極 電極
234‧‧‧側壁間隔器
238‧‧‧層間介電質
240‧‧‧通道區
242‧‧‧介電材料
243‧‧‧閘極介電層
244‧‧‧閘極電極
245‧‧‧源極和汲極區
250‧‧‧犠牲閘極 材料
252‧‧‧底部閘極隔離
302‧‧‧基底
310A‧‧‧下奈米佈線
310B‧‧‧上奈米佈線
312B‧‧‧上奈米佈線
313A‧‧‧通道部份
313B‧‧‧通道部份
338‧‧‧層間介電層
340‧‧‧通道部份
342‧‧‧介電材料
343‧‧‧閘極介電質
344‧‧‧閘極電極
345‧‧‧源極和汲極區
352‧‧‧底部閘極隔離區
402‧‧‧基底
406‧‧‧鰭基部鰭
410‧‧‧奈米佈線
410A‧‧‧上奈米佈線
410B‧‧‧下奈米佈線
411‧‧‧源極和汲極部份
411A‧‧‧源極和汲極部份
411B‧‧‧源極和汲極部份
412‧‧‧犠牲材料
438‧‧‧層間介電層
443‧‧‧閘極介電質
444‧‧‧閘極電極
446‧‧‧介電材料
452‧‧‧底部閘極隔離區
458‧‧‧源極和汲極接點
460‧‧‧開口
502‧‧‧基底
506‧‧‧基部鰭
510‧‧‧奈米佈線
510A‧‧‧主動奈米佈線
510B‧‧‧非主動奈米佈線
511A‧‧‧源極和汲極部份
511B‧‧‧源極和汲極部份
512‧‧‧犠牲材料
513‧‧‧通道部份
513B‧‧‧通道部份
534‧‧‧側壁間隔器
538‧‧‧層間介電層
543‧‧‧閘極介電層
544‧‧‧閘極電極
545‧‧‧源極和汲極區
546‧‧‧介電材料
558‧‧‧源極/汲極接點
600‧‧‧計算裝置
602‧‧‧主機板
604‧‧‧處理器
606‧‧‧通訊晶片
圖1A顯示根據本發明的實施例之奈米為基礎的半導體結構之二維剖面視圖。
圖1B顯示根據本發明的實施例之奈米為基礎的半導體結構之二維剖面視圖。
圖2A-2D顯示根據本發明的實施例之形成奈米為基礎的電晶體之製程中的操作之三維透視圖。
圖2E-2K顯示根據本發明的實施例之形成奈米為基礎的電晶體之製程中的操作之二維剖面視圖。
圖3A-3C顯示根據本發明的實施例之形成奈米為基礎的電晶體之製程中的操作之二維剖面視圖。
圖4A-4E顯示根據本發明的實施例之形成奈米為基礎的電晶體之製程中的操作之二維剖面視圖。
圖5A-5C顯示奈米為基礎的半導體結構之實施例的二維剖面視圖。
圖6顯示根據本發明的一實施例之計算裝置。
102‧‧‧基底
106‧‧‧基部鰭
110A‧‧‧主動奈米佈線
110B‧‧‧非主動奈米佈線
111A‧‧‧源極和汲極部份
111B‧‧‧源極和汲極部份
112‧‧‧犠牲材料
113A‧‧‧通道部份
113B‧‧‧通道部份
134‧‧‧側壁間隔器
140‧‧‧通道區
143‧‧‧閘極介電層
144‧‧‧閘極電極
145‧‧‧源極和汲極區
152‧‧‧底部閘極隔離

Claims (20)

  1. 一種半導體裝置，包括：複數垂直堆疊的奈米佈線，配置在基底上，其中，該複數奈米佈線中之一是主動奈米佈線以及該複數奈米佈線中之一是非主動奈米佈線；閘極結構，纏繞該主動奈米佈線，界定該裝置的通道區；以及源極區和汲極區，在該通道區的相對側上。
  2. 如申請專利範圍第1項之裝置，其中，該非主動奈米佈線具有在該通道區內的非主動通道部份，以及，其中，該非主動通道部份是不連續的。
  3. 如申請專利範圍第2項之裝置，其中，該源極區和該汲極區由同質材料形成。
  4. 如申請專利範圍第3項之裝置，其中，該同質材料是單晶半導體。
  5. 如申請專利範圍第3項之裝置，其中，該同質材料是金屬。
  6. 如申請專利範圍第2項之裝置，其中，該源極區和該汲極區由複數半導體膜的異質堆疊形成。
  7. 如申請專利範圍第2項之裝置，其中，該主動奈米佈線具有在該裝置的該源極區內的主動源極部份、以及具有在該裝置的該汲極區內的主動汲極部份，以及，其中，金屬源極接點纏繞該主動源極部份以及金屬汲極接點纏繞該主動汲極部份。
  8. 如申請專利範圍第1項之裝置，其中，該非主動奈米佈線具有在該通道區內的非主動通道部份，該非主動通道部份與該源極區和該汲極區中至少之一電隔離。
  9. 如申請專利範圍第8項之裝置，其中，該非主動奈米佈線具有在該源極區內的源極部份以及在該汲極區內的汲極部份，該源極部份與該汲極部份中至少之一由介電材料包封，以致於該非主動奈米佈線的通道部份與該源極區和該汲極區中至少之一電隔離。
  10. 如申請專利範圍第1項之裝置，其中，該主動奈米佈線以及該非主動奈米佈線是矽。
  11. 如申請專利範圍第1項之裝置，其中，該主動奈米佈線以及該非主動奈米佈線是鍺。
  12. 一種半導體裝置的製造方法，包括：設置基底，該基底具有：奈米佈線及犠牲材料的交錯層之垂直堆疊，其中，一奈米佈線是下奈米佈線以及一奈米佈線是上奈米佈線，犠牲閘極，纏繞該垂直堆疊，其中，該犠牲閘極界定該裝置的通道區，以及源極區和汲極區，在該通道區的相對側上；蝕刻該犠牲閘極以曝露該垂直堆疊；蝕刻該通道區內的該犠牲材料以曝露該上奈米佈線的第一通道部份、曝露該下奈米佈線第二通道部份、以及在該第一通道部份與該第二通道部份之間形成空乏； 以介電材料填充該通道區，其中，該介電材料填充該空乏；蝕刻該介電材料以曝露該第一通道部份，而該第二通道部份維持由該介電材料覆蓋；蝕刻該第一通道部份以形成非主動奈米佈線；蝕刻該介電材料以曝露該第二通道部份；以及形成圍繞該第二通道部份的閘極結構以形成主動奈米佈線。
  13. 如申請專利範圍第12項之方法，其中，蝕刻該第一通道部份移除該通道區內的實質上全部該上奈米佈線。
  14. 如申請專利範圍第12項之方法，又包括：形成該源極區和該汲極區內的該垂直堆疊的源極/汲極接點。
  15. 如申請專利範圍第12項之方法，又包括：蝕刻除掉該源極區和該汲極區中的該垂直堆疊以曝露該下奈米佈線下方的半導體表面；以及從該半導體表面生成單晶半導體材料，以形成同質源極/汲極區，其中，該同質源極/汲極區形成該第一通道部份的接點。
  16. 如申請專利範圍第12項之方法，又包括：蝕刻掉該源極區和該汲極區中至少之一中的該犠牲材料，以曝露該主動奈米佈線的主動源極/汲極部份；以及形成纏繞該主動源極/汲極部份的金屬接點。
  17. 一種半導體裝置的製造方法，包括：設置基底，該基底具有：奈米佈線及犠牲材料的交錯層之垂直堆疊，其中，一奈米佈線是下奈米佈線以及一奈米佈線是上奈米佈線，閘極結構，纏繞該垂直堆疊，其中，該閘極結構界定該裝置的通道區，以及源極區和汲極區，在該通道區的相對側上；在該源極/汲極區中至少之一內蝕刻接點開口以曝露該上奈米佈線的第一源極/汲極部份以及該下奈米佈線的第二源極/汲極部份，其中，該犠牲材料從該第一源極/汲極部份與該第二源極/汲極部份之間移除；在該接點開口中形成介電材料，其中，該介電材料覆蓋該第二源極/汲極部份，而該一源極/汲極部份維持曝露在該接點開口內；以及在該接點開口中形成接點，其中，該接點纏繞該第一源極/汲極部份。
  18. 如申請專利範圍第17項之方法，其中，在該接點開口中形成介電材料又包括：覆蓋地沉積該介電材料以填充該接點開口；以及蝕刻該接點開口內的該介電材料，以曝露該第一源極/汲極部份。
  19. 如申請專利範圍第17項之方法，其中，該閘極結構包括閘極介電質及閘極電極。
  20. 如申請專利範圍第17項之方法，又包括：在形成該接點之後，移除該閘極結構；以及形成功能閘極。
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