TWI485838B - 具有橋型中介層的半導體封裝 - Google Patents
具有橋型中介層的半導體封裝 Download PDFInfo
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- TWI485838B TWI485838B TW101146368A TW101146368A TWI485838B TW I485838 B TWI485838 B TW I485838B TW 101146368 A TW101146368 A TW 101146368A TW 101146368 A TW101146368 A TW 101146368A TW I485838 B TWI485838 B TW I485838B
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Description
本公開涉及具有橋型中介層(bridge interposer)的半導體封裝。
封裝解決方案持續發展來滿足由有著不斷增大的積體電路密度的電子裝置和系統施加的日益嚴格的設計約束。例如一個使單個的半導體封裝中的主動式晶片(active die)成倍增加的用於提供電源和接地的連接以及輸入/輸出信號的解決方案,採用一個以上的中介層來將主動式晶片電耦接至封裝基板。
為了該目的而實現的傳統中介層通常包括形成在半導體基板上的中介層電介質。直通矽晶穿孔(TSV)通常用於提供電源和接地連接以及將I/O信號提供給主動式晶片。然而,在TSV之中的寄生耦合導致的經由(through)半導體基板的洩漏可以不利地影響經由傳統中介層的電信號。
基本上如結合至少一個附圖所顯示/描述的並且如在申請專利範圍中更完整地提出的,本公開涉及具有橋型中介層的半導體封裝。
本發明提供了一種半導體封裝,包括:橋型中介層;第一主動式晶片,具有位於橋型中介層之上的第一部分,以及不位於橋型中介層之上的第二部分;第二主動式晶片,具有位於橋型中介
層之上的第一部分,以及不位於橋型中介層之上的第二部分;第一主動式晶片的第二部分和第二主動式晶片的第二部分包括安裝在封裝基板上的焊球;第一主動式晶片和第二主動式晶片採用焊球而不採用直通矽晶穿孔將電信號傳遞至封裝基板。
優選地,第一主動式晶片和第二主動式晶片經由橋型中介層來傳遞晶片至晶片信號。
優選地,第一主動式晶片經由採用在橋型中介層中的AC信號墊來將AC信號傳遞至第二主動式晶片。
優選地,橋型中介層由中介層電介質形成,該中介層電介質具有在其中形成的中介層內佈線軌跡。
優選地,橋型中介層由包括味素TM
組成膜的中介層電介質形成,該味素TM
組成膜具有在其中形成的中介層內佈線軌跡。
優選地,焊球經由各自的導電柱而耦接至第一主動式晶片的第二部分以及第二主動式晶片的第二部分。
優選地,第一主動式晶片和第二主動式晶片採用焊球和各自的導電柱將電信號傳遞至封裝基板。
優選地,該半導體封裝還包括在第一主動式晶片的第二部分和第二主動式晶片的第二部分上在各自的導電柱之間形成的鈍化層。
本發明還提供了一種半導體封裝,包括:橋型中介層;第一主動式晶片,具有位於橋型中介層之上的第一部分,以及不位於橋型中介層之上的第二部分;第二主動式晶片,具有位於橋型中介層之上的第一部分,以及不位於橋型中介層之上的第二部分;第一主動式晶片的第二部分和第二主動式晶片經由橋型中介層來傳遞晶片至晶片信號;封裝基板,位於第一主動式晶片和第二主動式晶片之下,第一主動式晶片和第二主動式晶片採用接合配線將電信號傳遞至封裝基板。
優選地,第一主動式晶片經由橋型中介層將DC信號傳遞至第
二主動式晶片。
優選地,第一主動式晶片經由採用在橋型中介層中的AC信號墊將AC信號傳遞至第二主動式晶片。
優選地,橋型中介層由中介層電介質形成,該中介層電介質具有在其中形成的中介層內佈線軌跡。
優選地,橋型中介層由包括味素TM
組成膜的中介層電介質形成,該味素TM
組成膜具有在其中形成的中介層內佈線軌跡。
本發明還提供了一種半導體封裝,包括:橋型中介層,具有包括AC信號墊的第一表面;第一主動式晶片,具有面向橋型中介層的第一表面的第一部分;第二主動式晶片,具有面向橋型中介層的第一表面的第一部分;第一主動式晶片和第二主動式晶片採用橋型中介層的AC信號墊來傳遞AC晶片至晶片信號。
優選地,第一主動式晶片和第二主動式晶片被配置為經由橋型中介層來傳遞DC晶片至晶片信號。
優選地,橋型中介層由中介層電介質形成,該中介層電介質具有在其中形成的中介層內佈線軌跡。
優選地,橋型中介層由包括味素TM
組成膜的中介層電介質形成,該味素TM
組成膜具有在其中形成的中介層內佈線軌跡。
優選地,第一主動式晶片的第二部分和第二主動式晶片的第二部分包括安裝在封裝基板上的焊球;第一主動式晶片和第二主動式晶片採用焊球而不採用直通矽晶穿孔將電信號傳遞至封裝基板。
優選地,焊球經由各自的導電柱而耦接至第一主動式晶片的第二部分以及第二主動式晶片的第二部分。
優選地,該半導體封裝還包括在第一主動式晶片的第二部分和第二主動式晶片的第二部分上在各自的導電柱之間形成的鈍化層。
100A、100B、100C、200、300‧‧‧半導體封裝
102、202、302‧‧‧封裝基板
104、304‧‧‧DAF
106A‧‧‧接點高度
110、210、310‧‧‧第一主動式晶片
111、121、211、221、311、321‧‧‧第一部分
112、122、212、222、312、322‧‧‧第二部分
120、220、320‧‧‧第二主動式晶片
130、230、330‧‧‧橋型中介層
131、231、331‧‧‧第一表面
132‧‧‧中介層電介質
134、234、334‧‧‧佈線軌跡
142‧‧‧焊球
144‧‧‧微凸塊
146‧‧‧導電杆
148‧‧‧鈍化層
208‧‧‧填充材料
232‧‧‧中介層電介質
237、247、337、347‧‧‧信號墊
238、338‧‧‧黏附層
245‧‧‧接合配線
332‧‧‧中介層
342‧‧‧焊球
圖1A顯示了包括橋型中介層的半導體封裝的一個實施方式的截面圖。
圖1B顯示了包括橋型中介層的半導體封裝的另一個實施方式的截面圖。
圖1C顯示了包括橋型中介層的半導體封裝的又一個實施方式的截面圖。
圖2顯示了包括非接觸橋型中介層的半導體封裝的一個實施方式的截面圖。
圖3顯示了包括非接觸橋型中介層的半導體封裝的另一個實施方式的截面圖。
以下描述包含關於本公開的實施方式的具體資訊。本領域的技術人員應理解的是本公開可以按照與本文中具體描述的不同的方式來實現。在本申請中的附圖和它們的詳細描述僅針對範例性實施方式。除非另有指出,否則在附圖中相似或對應的元件可以由相似或對應的參考數位標明。此外在本申請中的附圖和說明通常不按比例,並且目的不在於對應實際的相對尺寸。
圖1A顯示了包括橋型中介層的半導體封裝的一個實施方式的截面圖。如圖1A中所示,半導體封裝100A包括具有第一部分111和第二部分112的第一主動式晶片110、具有第一部分121和第二部分122的第二主動式晶片120、橋型中介層(bridge interposer)130以及封裝基板(package substrate)102。如與1A中進一步所示,橋型中介層130具有第一表面131,並且包括中介層電介質(interposer dielectric)132,該第一表面131面向第一和第二主動式晶片分別的第一部分111和121,該中介層電介質具有在其中形成的中介層內佈線軌跡(routing trace)134。在圖1A中還顯示了焊球142、微凸塊(micro-bump)144、將橋型中介層130固定至封裝基板102的晶片接合膜(DAF)104以及第一主動式晶片110和
第二主動式晶片120距封裝基板102的接點高度(stand-off height)106A。
應注意,雖然在圖1中只有一個範例性中介層內佈線軌跡由參考數字134具體標明,但是在中介層電介質132中顯示的四個中介層內佈線軌跡中的任一或全部都可以被表徵為中介層內佈線軌跡134。還應注意雖然在圖1A中每個焊球142和微凸塊144中各自只有一個由參考數字具體標明,但是圖1中所示的八個焊球和八個微凸塊的任一或全部可以分別表徵為焊球142和微凸塊144。
例如,第一主動式晶片110和第二主動式晶片120可以是封裝或未封裝的晶片。雖然在圖1A中第一主動式晶片和第二主動式晶片120以倒裝晶片的構造顯示,但是這種表示僅為範例,並且在其他實施方式中,第一主動式晶片110和第二主動式晶片120中的一個或兩者可以表現為不同的構造。此外,應理解雖然圖1A中所示的實施方式顯示了例如第一主動式晶片110和第二主動式晶片120的兩個主動式晶片經由橋型中介層130耦接,但是在一個實施方式中,多於兩個的主動式晶片可以經由橋型中介層130耦接。
如圖1A所示,在半導體封裝100A中,第一主動式晶片110具有位於橋型中介層130之上的第一部分111,以及不位於橋型中介層130之上的第二部分112。此外,在半導體封裝100A中,第二主動式晶片120具有位於橋型中介層130之上的第一部分121,以及不位於橋型中介層130之上的第二部分122。如進一步在圖1A中顯示的,第一主動式晶片110的第二部分112和第二主動式晶片120的第二部分122包括安裝在封裝基板102上的焊球142。因此,第一主動式晶片110和第二主動式晶片120被配置為採用焊球142而不採用直通矽晶穿孔(TSV)將電信號傳遞(communicate)至封裝基板102。此外,第一主動式晶片110和第二
主動式晶片120同樣被配置為經由橋型中介層130來傳遞晶片至晶片信號。換言之,例如第一主動式晶片110和第二主動式晶片120可以將焊球142用於接地、電源以及輸入/輸出(I/O)連接,同時使用在橋型中介層120的中介層電介質132中形成的微凸塊144以及中介層內佈線軌跡134來傳遞晶片至晶片信號。
例如,中介層電介質132可以由諸如纖維強化(fiber reinforced)雙馬來醯亞胺三氮雜苯樹脂(BT,bismaleimide triazine)、FR-4、玻璃或陶瓷的剛性電介質材料形成。可選地,中介層電介質132可以是由聚醯亞胺膜(polymide film)或其他合適的帶材料形成的柔性電介質。在一些實施方式中,中介層電介質132可以是由環氧酚醛樹脂(epoxy-phenolic)或氰酸酯環氧(cyanate ester-epoxy)構造材料形成的。作為具體範例,在一個實施方式中,中介層電介質132可以由味素TM
(AjinomotoTM
)組成膜(ABF)形成。根據該範例性實施方式,中介層內佈線軌跡134可以在用於形成中介層電介質132的構造過程中使用本領域中已知的任何合適的技術形成。
根據圖1A中所示的實施方式,第一主動式晶片110和第二主動式晶片120經由微凸塊144而電連接至橋型中介層130。然而應注意,更一般地,微凸塊144可以對應於適用於將第一主動式晶片110和第二主動式晶片120耦接至橋型中介層130的任何電接觸體。因此,在其他實施方式中,微凸塊144可以由各個導電杆或導電柱來代替,例如由銅形成的金屬杆或金屬柱。可選地,在橋型中介層130中,一些或全部的微凸塊144可以被交流(AC)信號墊(經由對以下的圖2和圖3的參考顯示並描述的AC信號墊)替換。即,在一個實施方式中,橋型中介層130可以包括:用於在第一主動式晶片110和第二主動式晶片120之間經由中介層內佈線軌跡134來傳遞直流(DC)晶片到晶片信號(“DC信號”)的微凸塊144或其他電接觸體,以及用於在第一主動式晶片110
和第二主動式晶片120之間傳遞AC晶片到晶片信號的AC信號墊。
現參見圖1B,圖1B顯示了包括橋型中介層的半導體封裝的另一實施方式的截面圖。半導體封裝100B包括先前參考圖1A描述的全部特徵。此外,半導體封裝100B包括將第一主動式晶片110的第二部分112和第二主動式晶片120的第二部分耦接至相應的焊球142的導電柱或導電杆146(下文中的“導電柱146”)。應注意雖然在圖1B中只有一個導電柱146由參考數字具體地標明,但是圖1B中所示的將第一主動式晶片110的第二部分112和/或第二主動式晶片120的第二部分耦接至相應的焊球142的八個導電柱的任一或全部,都可以被表徵為導電柱146。
導電柱146可以是例如在位於第一主動式晶片110的第二部分112和第二主動式晶片120的第二部分122上的導電盤(在圖1B中沒有顯示導線盤)上形成的金屬柱。根據一個實施方式,導電柱146可以是使用電化學鍍層處理而形成的銅柱。例如,如圖1B中所示,導電柱146的使用導致相比於圖1A中的接點高度106A,接點高度106增加了,並且在由焊球142單獨提供的接點高度106A不足的情況下,導電柱146的使用是有利的。如圖1B中進一步所示,在包括導電柱146的實施方式中,第一主動式晶片110和第二主動式晶片120採用焊球142和相應的導電柱146將電信號傳遞至封裝基板102。
繼續至圖1C,圖1C顯示了包括橋型中介層的半導體封裝的又一個實施方式的截面圖。半導體封裝100C包括先前參考圖1A和圖1B而描述的全部特徵。此外,半導體封裝100C包括在第一主動式晶片110的第二部分112以及第二主動式晶片120的第二部分122上在導電柱146之間形成的鈍化層148。鈍化層148可以是例如使用化學氣相沈積處理(CVD)或用於製造鈍化層148的任何其他適合的處理而形成的氧化物層,或諸如氮化矽(Si3N4)
的氮化物層。例如,當採用導電柱146時,提供鈍化層148可以增強機械強度以及經由焊球142到封裝基板102的接地、電源和I/O連接的穩定性。
對比於中介層通常包括中介層電介質層和中介層半導體基板的傳統半導體封裝,半導體封裝100A、100B和100C使用可以省略半導體基板的橋型中介層130來實現。此外,進一步地對比於採用TSV的傳統封裝解決方案,半導體封裝100A、100B和100C採用導電柱146和/或焊球142從而在第一主動式晶片110和封裝基板102之間,以及在第二主動式晶片120和封裝基板102之間提供電子連接而不採用TSV,同時能夠經由不使用TSV的橋型中介層130在第一主動式晶片110和第二主動式晶片120之間傳遞晶片至晶片信號。因此,半導體封裝100A、100B、100C有利地避免了在傳統技術中被認為會不利地影響經過TSV的信號的在TSV中的半導體洩漏和電耦合。
現移至圖2,圖2顯示了包括非接觸橋型中介層的半導體封裝的一個實施方式的截面圖。如圖2中所示,半導體封裝200包括具有第一部分211和第二部分212的第一主動式晶片210、具有第一部分221和第二部分222的第二主動式晶片220、顯示為非接觸橋型中介層的橋型中介層230以及封裝基板202。如圖2中進一步所示,橋型中介層230具有面向第一主動式晶片210和第二主動式晶片220分別的第一部分211和221的第一表面231,並且包括中介層電介質232,該中介層電介質232具有在其中形成的中介層內佈線軌跡234以及AC信號墊237。圖2中還顯示了接合配線245,將橋型中介層230固定至第一主動式晶片210的第一部分211和第二主動式晶片220的第一部分221的黏附層(adhesion layer)238、在第一主動式晶片210的第一部分211和第二主動式晶片220的第一部分221中的AC信號墊247以及在第一主動式晶片210和第二主動式晶片220之間形成的填充材料208。
雖然在圖200中只有一個範例性中介層內佈線軌跡由參考數字234具體表明,但是需要理解的是,在中介層電介質232中顯示的四個中介層內佈線軌跡的任一或全部都可以表徵為中介層內佈線軌跡234。此外,雖然在圖2中,在橋型中介層230中的每個AC信號墊237和在第一主動式晶片110和第二主動式晶片220中的每個AC信號墊247中,只有一個由參考數字具體標明,但是在橋型中介層230中的八個AC信號墊和分佈在第一主動式晶片210和第二主動式晶片220之間的八個AC信號墊中的任一或全部都可以分別表徵為AC信號墊237和AC信號墊247。
第一主動式晶片210和第二主動式晶片220可以是例如封裝或未封裝的晶片。雖然在圖2中,橋型中介層230被顯示為在第一主動式晶片210的第一部分211和第二主動式晶片220的第一部分221之上具有倒裝晶片取向,但是該表示僅是範例性的,並且在其他的實施方式中,第一主動式晶片210、第二主動式晶片220以及橋型連接器的配置可以不同地構造。此外,應理解的是,雖然圖2中所示的實施方式顯示了經由橋型中介層230耦接的例如第一主動式晶片210和第二主動式晶片220的兩個主動式晶片,但是在一個實施方式中,可以經由橋型中介層230來耦接多於兩個的主動式晶片。
如圖2中所示,在半導體封裝200中,第一主動式晶片210具有位於橋型中介層230之下的第一部分211以及不位於橋型中介層230之下的第二部分212。此外,在半導體封裝200中,第二主動式晶片220具有位於橋型中介層230之下的第一部分221以及不位於橋型中介層230之下的第二部分222。如圖2中進一步所示,第一主動式晶片210和第二主動式晶片220被配置為經由橋型中介層230傳遞晶片至晶片信號。此外,並且也如圖2中所示,第一主動式晶片210的第二部分212和第二主動式晶片220的第二部分222經由接合配線245耦接至封裝基板202。換言之,第一
主動式晶片210和第二主動式晶片220可以採用接合配線245來將電信號傳遞至封裝基板202,同時,採用AC信號墊247經由黏附層238、在橋型中介層230中的AC信號墊237以及形成在中介層電介質232中的中介層內佈線軌跡234來傳遞晶片至晶片信號。
例如,中介層電介質232可以由諸如纖維強化BT、FR-4、玻璃或陶瓷的剛性電介質材料形成。可選地,中介層電介質232可以是由聚醯亞胺膜或其他合適的帶材料形成的柔性電介質。在一些實施方式中,中介層電介質132可以是由環氧酚醛樹脂或氰酸酯環氧構造材料形成。作為具體範例,在一個實施方式中,中介層電介質232可以由ABFTM
形成。根據該後面的範例性實施方式,中介層內佈線軌跡234可以在用於形成中介層電介質232的構造過程中使用本領域中已知的任何合適的技術形成。
根據圖2中所示的實施方式,第一主動式晶片的第一部分211和第二主動式晶片的第一部分221經由AC信號墊247、黏附層238以及在橋型中介層230中的AC信號墊237來電容性地連接至橋型中介層230。黏附層238可以由例如DAF,或任何在提供黏性同時擁有使黏附層238適合於用作電容電介質的介電常數的材料形成,該電容電介質用於在AC信號墊247和AC信號墊237之間傳遞AC信令。填充材料208可以是能夠提供第一主動式晶片對第二主動式晶片的隔離的任何材料,例如,填充材料208和黏附層238可以由諸如DAF的相同的物質形成。
雖然圖2和本討論關注於第一主動式晶片210和第二主動式晶片220之間的AC晶片至晶片信令,但是可選地,例如,在第一主動式晶片210的第一部分211和橋型中介層230之間、以及在第二主動式晶片220的第一部分221和橋型中介層230之間的電連接可以使用諸如微凸塊的接觸體或經由接觸體和非接觸互連的組合來提供。因此,在一個實施方式中,可以使用用於在第一主動式晶片210和第二主動式晶片220之間傳遞DC晶片至晶片信號
的微凸塊或其他接觸體,將橋型中介層230耦接至第一主動式晶片210的第一部分211以及第二主動式晶片220的第一部分221,並且也可以使用用於在第一主動式晶片210和第二主動式晶片220之間傳遞AC晶片至晶片信號的AC信號墊,將橋型中介層230耦接至第一主動式晶片210的第一部分211以及第二主動式晶片220的第一部分221。
繼續至圖3,圖3顯示了包括非接觸橋型中介層的半導體封裝的另一個實施方式的截面圖。如圖3所示,半導體封裝300包括具有第一部分311和第二部分312第一主動式晶片310、具有第一部分321和第二部分322第二主動式晶片320、在圖3中表示為的非接觸性橋型中介層的橋型中介層330以及封裝基板302。如圖3中進一步所示,橋型中介層230具有面向第一主動式晶片210和第二主動式晶片320分別的第一部分311和321的第一表面331,並且包括中介層電介質332,該中介層電介質332具有在其中形成的中介層內佈線軌跡334以及AC信號墊337。圖3中還顯示了焊球342、AC信號墊347、將橋型中介層330固定至封裝基板302的DAF 304以及將橋型中介層330固定至第一主動式晶片310的第一部分311以及第二主動式晶片320的第一部分321的黏附層338。
第一主動式晶片310、第二主動式晶片320、焊球342、DAF 304以及封裝基板302分別對應在圖1A、圖1B和圖1C中的第一主動式晶片110、第二主動式晶片120、焊球142、DAF 104以及封裝基板102,並且可以共用由以上那些對應特徵所屬的特性。此外,在圖3中,AC信號墊347和黏附層338分別對應在圖2中的AC信號墊247和黏附層238。在圖3中,具有第一表面331並且包括中介層電介質332、中介層內佈線軌跡334以及AC信號墊337的橋型中介層330、結構上對應於在圖2中的具有第一表面231並且包括中介層電介質232、中介層內佈線軌跡234以及AC信號墊237
的橋型中介層230,並且可以共用由先前那些對應特徵所屬的特性。例如,類似於中介層電介質232,在一個實施方式中,圖3中的中介層332可以由ABFTM
形成。然而,應注意與圖2中所示的構造相反,類似於圖1A、圖1B和圖1C所示的構造,在半導體封裝300中,第一主動式晶片310的第一部分311和第二主動式晶片320的第一部分321位於橋型中介層330之上。
如圖3中所示,橋型中介層300的第一表面331包括AC信號墊337。此外如圖3中所示,第一主動式晶片310的第一部分311面向橋型中介層330的第一表面331,並且第二主動式晶片310的第一部分321也面向橋型中介層330的第一表面331。根據圖3中所示的實施方式,第一主動式晶片310和第二主動式晶片320被配置為採用橋型中介層330的AC信號墊337來傳遞AC晶片至晶片信號。此外,第一主動式晶片310和第二主動式晶片320被配置為採用焊球342而不採用直通矽晶穿孔(TSV)將電信號傳遞至封裝基板302。
如在圖1A、圖1B和圖1C中所示的實施方式的情況下,圖3中的半導體封裝300可以經由增加鈍化層和/或導電柱或導電杆來修改,該增加的鈍化層和/或導電柱或導電杆分別對應於圖1B和圖1C中所示的鈍化層148和導電柱146。此外,雖然圖3顯示了在第一主動式晶片310和第二主動式晶片320之間的AC晶片至晶片信令(信號傳遞),但是可選地,在第一主動式晶片310的第一部分311和橋型中介層330之間以及在第二主動式晶片320的第一部分320和橋型中介層330之間的電連接,例如可以使用諸如微凸塊(對應於圖1A、圖1B和圖1C中的微凸塊144)的接觸體,或經由AC信號墊和諸如微凸塊的接觸體的組合來提供。隨後,在一個實施方式中,可以使用用於在第一主動式晶片310和第二主動式晶片320之間傳遞DC晶片至晶片信號的微凸塊或其他接觸體,將橋型中介層330耦接至第一主動式晶片310的第一部分311
以及第二主動式晶片320的第一部分321,並且也可以使用用於在第一主動式晶片310和第二主動式晶片320之間傳遞AC晶片至晶片信號的AC信號墊,將橋型中介層耦接至第一主動式晶片310的第一部分311以及第二主動式晶片320的第一部分321。
因此,經由使用由中介層電介質形成的橋型中介層,本文中公開的概念的各種實施方式有利地實現了經由中介層的洩漏被基本上消除的半導體封裝。此外,描述的實施方式有利地公開了省略了TVS的半導體封裝。因此,本文中公開的概念和實施方式能夠避免在傳統半導體封裝方案中的經過TSV的信號的不利影響。
從以上描述中顯而易見的是,多種技術可以用於實現在本申請中描述的概念而不偏離這些概念的範圍。此外,雖然具體參考了特定的實施方式來描述概念,但是該發明所屬領域中具有通常知識者應當理解,在不偏離這些概念的實質和範圍的條件下,可以在形式和細節上進行改變。因此,所描述的實施方式在所有方面都應當被認為是範例性的而非限制性的。還需要理解的是,本申請不受本文中描述的具體實施方式的限制,而在不偏離本公開的範圍的條件下,多種重新配置、修改和替代都是可行的。
100A‧‧‧半導體封裝
102‧‧‧封裝基板
104‧‧‧DAF
106A‧‧‧接點高度
110‧‧‧第一主動式晶片
111、121‧‧‧第一部分
112、122‧‧‧第二部分
120‧‧‧第二主動式晶片
130‧‧‧橋型中介層
131‧‧‧第一表面
132‧‧‧中介層電介質
134‧‧‧佈線軌跡
142‧‧‧焊球
144‧‧‧微凸塊
Claims (7)
- 一種半導體封裝,包括:橋型中介層,由中介層電介質形成,所述中介層電介質不具有直通矽晶穿孔;第一主動式晶片,具有位於所述橋型中介層之上的第一部分,以及不位於所述橋型中介層之上的第二部分;以及第二主動式晶片,具有位於所述橋型中介層之上的第一部分,以及不位於所述橋型中介層之上的第二部分;其中,所述第一主動式晶片的所述第二部分和所述第二主動式晶片的所述第二部分包括安裝在封裝基板上的焊球;其中,所述第一主動式晶片和所述第二主動式晶片採用所述焊球而不採用直通矽晶穿孔將電信號傳遞至所述封裝基板;其中,所述第一主動式晶片和第二主動式晶片經由所述橋型中介層來傳遞DC信號至晶片。
- 根據申請專利範圍第1項所述的半導體封裝,其中,所述第一主動式晶片經由採用在所述橋型中介層中的AC信號墊來將AC信號傳遞至所述第二主動式晶片。
- 根據申請專利範圍第1項所述的半導體封裝,其中,所述中介層電介質包括在其中形成的中介層內佈線軌跡。
- 一種半導體封裝,包括:橋型中介層,由中介層電介質形成,所述中介層電介質不具有直通矽晶穿孔;第一主動式晶片,具有位於所述橋型中介層之上的第一部分,以及不位於所述橋型中介層之上的第二部分;第二主動式晶片,具有位於所述橋型中介層之上的第一部分,以及不位於所述橋型中介層之上的第二部分,所述第一主動式晶片的所述第二部分和所述第二主動式晶片經由所述橋型中介層來傳遞晶片至晶片信號;以及 封裝基板,位於所述第一主動式晶片和所述第二主動式晶片之下,所述第一主動式晶片和所述第二主動式晶片採用接合配線將電信號傳遞至所述封裝基板;其中,所述第一主動式晶片經由所述橋型中介層將DC信號傳遞至所述第二主動式晶片。
- 根據申請專利範圍第4項所述的半導體封裝,其中,所述第一主動式晶片經由採用在所述橋型中介層中的AC信號墊將AC信號傳遞至所述第二主動式晶片。
- 一種半導體封裝,包括:橋型中介層,具有包括AC信號墊的第一表面且由中介層電介質形成,其中,所述中介層電介質不具有直通矽晶穿孔;第一主動式晶片,具有面向所述橋型中介層的所述第一表面的第一部分;以及第二主動式晶片,具有面向所述橋型中介層的所述第一表面的第一部分;其中,所述第一主動式晶片和所述第二主動式晶片採用所述橋型中介層的所述AC信號墊來傳遞AC信號至晶片;其中,所述第一主動式晶片和所述第二主動式晶片被配置為經由所述橋型中介層來傳遞DC信號至晶片。
- 根據申請專利範圍第6項所述的半導體封裝,其中,所述中介層電介質包括在其中形成的中介層內佈線軌跡。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI727996B (zh) * | 2015-12-18 | 2021-05-21 | 美商英特爾Ip公司 | 具有暴露在側壁上之導電佈線的中介件 |
Families Citing this family (96)
Publication number | Priority date | Publication date | Assignee | Title |
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US9136236B2 (en) | 2012-09-28 | 2015-09-15 | Intel Corporation | Localized high density substrate routing |
US8946900B2 (en) * | 2012-10-31 | 2015-02-03 | Intel Corporation | X-line routing for dense multi-chip-package interconnects |
US9190380B2 (en) | 2012-12-06 | 2015-11-17 | Intel Corporation | High density substrate routing in BBUL package |
US9064705B2 (en) * | 2012-12-13 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of packaging with interposers |
US9070644B2 (en) | 2013-03-15 | 2015-06-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
US9646894B2 (en) | 2013-03-15 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging mechanisms for dies with different sizes of connectors |
US9147663B2 (en) | 2013-05-28 | 2015-09-29 | Intel Corporation | Bridge interconnection with layered interconnect structures |
US9041205B2 (en) | 2013-06-28 | 2015-05-26 | Intel Corporation | Reliable microstrip routing for electronics components |
US9508636B2 (en) | 2013-10-16 | 2016-11-29 | Intel Corporation | Integrated circuit package substrate |
US9642259B2 (en) | 2013-10-30 | 2017-05-02 | Qualcomm Incorporated | Embedded bridge structure in a substrate |
US9275955B2 (en) * | 2013-12-18 | 2016-03-01 | Intel Corporation | Integrated circuit package with embedded bridge |
US10038259B2 (en) * | 2014-02-06 | 2018-07-31 | Xilinx, Inc. | Low insertion loss package pin structure and method |
US9385110B2 (en) | 2014-06-18 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US9935081B2 (en) * | 2014-08-20 | 2018-04-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid interconnect for chip stacking |
US9542522B2 (en) | 2014-09-19 | 2017-01-10 | Intel Corporation | Interconnect routing configurations and associated techniques |
CN104637909A (zh) * | 2015-01-30 | 2015-05-20 | 华进半导体封装先导技术研发中心有限公司 | 一种三维芯片集成结构及其加工工艺 |
US9418966B1 (en) * | 2015-03-23 | 2016-08-16 | Xilinx, Inc. | Semiconductor assembly having bridge module for die-to-die interconnection |
US9653428B1 (en) * | 2015-04-14 | 2017-05-16 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US10074630B2 (en) | 2015-04-14 | 2018-09-11 | Amkor Technology, Inc. | Semiconductor package with high routing density patch |
CN107924831B (zh) | 2015-09-24 | 2023-10-10 | 英特尔公司 | 用于显露集成电路器件的背侧和相关配置的技术 |
WO2017099788A1 (en) * | 2015-12-11 | 2017-06-15 | Intel Corporation | Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate |
US10312220B2 (en) | 2016-01-27 | 2019-06-04 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
TWI652778B (zh) | 2016-01-27 | 2019-03-01 | 艾馬克科技公司 | 半導體封裝以及其製造方法 |
US10497674B2 (en) | 2016-01-27 | 2019-12-03 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
KR101966328B1 (ko) * | 2016-03-29 | 2019-04-05 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
US20170287838A1 (en) | 2016-04-02 | 2017-10-05 | Intel Corporation | Electrical interconnect bridge |
US10276403B2 (en) * | 2016-06-15 | 2019-04-30 | Avago Technologies International Sales Pe. Limited | High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer |
WO2018009171A1 (en) * | 2016-07-02 | 2018-01-11 | Intel Corporation | Rlink - die to die channel interconnect configurations to improve signaling |
US10366968B2 (en) * | 2016-09-30 | 2019-07-30 | Intel IP Corporation | Interconnect structure for a microelectronic device |
US11277922B2 (en) | 2016-10-06 | 2022-03-15 | Advanced Micro Devices, Inc. | Circuit board with bridge chiplets |
US9984995B1 (en) * | 2016-11-13 | 2018-05-29 | Nanya Technology Corporation | Semiconductor package and manufacturing method thereof |
US11183458B2 (en) * | 2016-11-30 | 2021-11-23 | Shenzhen Xiuyuan Electronic Technology Co., Ltd | Integrated circuit packaging structure and method |
US20180166419A1 (en) * | 2016-12-12 | 2018-06-14 | Nanya Technology Corporation | Semiconductor package |
US11004824B2 (en) | 2016-12-22 | 2021-05-11 | Intel Corporation | Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same |
WO2018125080A1 (en) * | 2016-12-28 | 2018-07-05 | Intel Corporation | Enabling long interconnect bridges |
CN114038809A (zh) * | 2016-12-29 | 2022-02-11 | 英特尔公司 | 用于系统级封装设备的与铜柱连接的裸管芯智能桥 |
CN116190326A (zh) | 2016-12-29 | 2023-05-30 | 英特尔公司 | 超芯片 |
KR20180086804A (ko) | 2017-01-23 | 2018-08-01 | 앰코 테크놀로지 인코포레이티드 | 반도체 디바이스 및 그 제조 방법 |
US20190019776A1 (en) * | 2017-07-11 | 2019-01-17 | Texas Instruments Incorporated | Structures and methods for capacitive isolation devices |
US10622311B2 (en) * | 2017-08-10 | 2020-04-14 | International Business Machines Corporation | High-density interconnecting adhesive tape |
US20190051587A1 (en) * | 2017-08-11 | 2019-02-14 | Marvell Israel (M.I.S.L) Ltd. | Ic package |
US10510721B2 (en) | 2017-08-11 | 2019-12-17 | Advanced Micro Devices, Inc. | Molded chip combination |
US20200144186A1 (en) * | 2017-09-13 | 2020-05-07 | Intel Corporation | Active silicon bridge |
KR102365682B1 (ko) | 2017-11-13 | 2022-02-21 | 삼성전자주식회사 | 반도체 패키지 |
WO2019132970A1 (en) * | 2017-12-29 | 2019-07-04 | Intel Corporation | Microelectronic assemblies |
US11508663B2 (en) | 2018-02-02 | 2022-11-22 | Marvell Israel (M.I.S.L) Ltd. | PCB module on package |
US10580738B2 (en) * | 2018-03-20 | 2020-03-03 | International Business Machines Corporation | Direct bonded heterogeneous integration packaging structures |
US10490503B2 (en) | 2018-03-27 | 2019-11-26 | Intel Corporation | Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same |
US11735570B2 (en) * | 2018-04-04 | 2023-08-22 | Intel Corporation | Fan out packaging pop mechanical attach method |
US10593628B2 (en) | 2018-04-24 | 2020-03-17 | Advanced Micro Devices, Inc. | Molded die last chip combination |
US10593620B2 (en) | 2018-04-27 | 2020-03-17 | Advanced Micro Devices, Inc. | Fan-out package with multi-layer redistribution layer structure |
US10700051B2 (en) | 2018-06-04 | 2020-06-30 | Intel Corporation | Multi-chip packaging |
US10535608B1 (en) * | 2018-07-24 | 2020-01-14 | International Business Machines Corporation | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate |
US10672712B2 (en) | 2018-07-30 | 2020-06-02 | Advanced Micro Devices, Inc. | Multi-RDL structure packages and methods of fabricating the same |
US11393758B2 (en) * | 2018-09-12 | 2022-07-19 | Intel Corporation | Power delivery for embedded interconnect bridge devices and methods |
US11114308B2 (en) | 2018-09-25 | 2021-09-07 | International Business Machines Corporation | Controlling of height of high-density interconnection structure on substrate |
MY202246A (en) * | 2018-10-22 | 2024-04-19 | Intel Corp | Devices and methods for signal integrity protection technique |
US10916507B2 (en) * | 2018-12-04 | 2021-02-09 | International Business Machines Corporation | Multiple chip carrier for bridge assembly |
US11676941B2 (en) | 2018-12-07 | 2023-06-13 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor package and fabricating method thereof |
US11652060B2 (en) * | 2018-12-28 | 2023-05-16 | Intel Corporation | Die interconnection scheme for providing a high yielding process for high performance microprocessors |
KR102620867B1 (ko) * | 2019-03-15 | 2024-01-04 | 에스케이하이닉스 주식회사 | 브리지 다이를 포함한 반도체 패키지 |
KR102644598B1 (ko) | 2019-03-25 | 2024-03-07 | 삼성전자주식회사 | 반도체 패키지 |
CN112136212B (zh) * | 2019-04-24 | 2022-07-29 | 深圳市汇顶科技股份有限公司 | 芯片互联装置、集成桥结构的基板及其制备方法 |
CN111900138B (zh) * | 2019-05-06 | 2022-06-21 | 讯芯电子科技(中山)有限公司 | 系统模组封装结构及系统模组封装方法 |
CN114144875A (zh) | 2019-06-10 | 2022-03-04 | 马维尔以色列(M.I.S.L.)有限公司 | 具有顶侧存储器模块的ic封装 |
US10923430B2 (en) | 2019-06-30 | 2021-02-16 | Advanced Micro Devices, Inc. | High density cross link die with polymer routing layer |
US11367628B2 (en) | 2019-07-16 | 2022-06-21 | Advanced Micro Devices, Inc. | Molded chip package with anchor structures |
US10991635B2 (en) | 2019-07-20 | 2021-04-27 | International Business Machines Corporation | Multiple chip bridge connector |
US11094654B2 (en) * | 2019-08-02 | 2021-08-17 | Powertech Technology Inc. | Package structure and method of manufacturing the same |
US11688660B2 (en) * | 2019-08-07 | 2023-06-27 | Intel Corporation | Bridge for radio frequency (RF) multi-chip modules |
US11742301B2 (en) | 2019-08-19 | 2023-08-29 | Advanced Micro Devices, Inc. | Fan-out package with reinforcing rivets |
US10957650B2 (en) * | 2019-08-21 | 2021-03-23 | International Business Machines Corporation | Bridge support structure |
US11532580B2 (en) * | 2019-08-29 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnect structure, semiconductor structure including interconnect structure and method for forming the same |
US11393759B2 (en) | 2019-10-04 | 2022-07-19 | International Business Machines Corporation | Alignment carrier for interconnect bridge assembly |
US11282806B2 (en) * | 2019-10-11 | 2022-03-22 | Marvell Asia Pte, Ltd. | Partitioned substrates with interconnect bridge |
US11164817B2 (en) | 2019-11-01 | 2021-11-02 | International Business Machines Corporation | Multi-chip package structures with discrete redistribution layers |
US11094637B2 (en) | 2019-11-06 | 2021-08-17 | International Business Machines Corporation | Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers |
US11139269B2 (en) | 2020-01-25 | 2021-10-05 | International Business Machines Corporation | Mixed under bump metallurgy (UBM) interconnect bridge structure |
US11201136B2 (en) | 2020-03-10 | 2021-12-14 | International Business Machines Corporation | High bandwidth module |
US11605594B2 (en) | 2020-03-23 | 2023-03-14 | Qualcomm Incorporated | Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate |
US12074123B2 (en) | 2020-04-03 | 2024-08-27 | Macom Technology Solutions Holdings, Inc. | Multi level radio frequency (RF) integrated circuit components including passive devices |
EP4128360A1 (en) | 2020-04-03 | 2023-02-08 | Wolfspeed, Inc. | Group iii nitride-based radio frequency transistor amplifiers having source, gate and/or drain conductive vias |
KR20220162147A (ko) | 2020-04-03 | 2022-12-07 | 울프스피드, 인크. | 후면측 소스, 게이트 및/또는 드레인 단자들을 갖는 iii족 질화물계 라디오 주파수 증폭기들 |
JP7474349B2 (ja) * | 2020-04-03 | 2024-04-24 | ウルフスピード インコーポレイテッド | Rf増幅器パッケージ |
CN111554656A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种半导体封装器件 |
CN111554658A (zh) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | 一种半导体封装器件 |
US11302674B2 (en) | 2020-05-21 | 2022-04-12 | Xilinx, Inc. | Modular stacked silicon package assembly |
US11551939B2 (en) | 2020-09-02 | 2023-01-10 | Qualcomm Incorporated | Substrate comprising interconnects embedded in a solder resist layer |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
CN112435981A (zh) * | 2020-09-30 | 2021-03-02 | 日月光半导体制造股份有限公司 | 半导体封装装置及其制造方法 |
IT202100001637A1 (it) * | 2021-01-27 | 2022-07-27 | St Microelectronics Srl | Sistema elettronico incapsulato formato da piastrine accoppiate elettricamente e isolate galvanicamente |
KR20220140215A (ko) | 2021-04-09 | 2022-10-18 | 삼성전자주식회사 | 반도체 패키지 |
US20230035627A1 (en) * | 2021-07-27 | 2023-02-02 | Qualcomm Incorporated | Split die integrated circuit (ic) packages employing die-to-die (d2d) connections in die-substrate standoff cavity, and related fabrication methods |
US11848272B2 (en) * | 2021-08-16 | 2023-12-19 | International Business Machines Corporation | Interconnection between chips by bridge chip |
WO2023019516A1 (zh) * | 2021-08-19 | 2023-02-23 | 华为技术有限公司 | 芯片封装结构及电子设备 |
CN116093046A (zh) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | 单颗芯片的制备方法及芯片结构 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070080442A1 (en) * | 2004-03-18 | 2007-04-12 | Georg Meyer-Berg | Semiconductor module having a coupling substrate, and methods for its production |
US20100327424A1 (en) * | 2009-06-24 | 2010-12-30 | Henning Braunisch | Multi-chip package and method of providing die-to-die interconnects in same |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5198963A (en) | 1991-11-21 | 1993-03-30 | Motorola, Inc. | Multiple integrated circuit module which simplifies handling and testing |
US6461895B1 (en) | 1999-01-05 | 2002-10-08 | Intel Corporation | Process for making active interposer for high performance packaging applications |
TW411037U (en) | 1999-06-11 | 2000-11-01 | Ind Tech Res Inst | Integrated circuit packaging structure with dual directions of thermal conduction path |
US6507115B2 (en) * | 2000-12-14 | 2003-01-14 | International Business Machines Corporation | Multi-chip integrated circuit module |
US7573136B2 (en) * | 2002-06-27 | 2009-08-11 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor device components |
TWI221333B (en) | 2003-01-14 | 2004-09-21 | Advanced Semiconductor Eng | Bridge connection type of MCM package |
JP4581768B2 (ja) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
US7671449B2 (en) * | 2005-05-04 | 2010-03-02 | Sun Microsystems, Inc. | Structures and methods for an application of a flexible bridge |
US7402442B2 (en) * | 2005-12-21 | 2008-07-22 | International Business Machines Corporation | Physically highly secure multi-chip assembly |
US7390700B2 (en) | 2006-04-07 | 2008-06-24 | Texas Instruments Incorporated | Packaged system of semiconductor chips having a semiconductor interposer |
JP2008166373A (ja) | 2006-12-27 | 2008-07-17 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7675163B2 (en) | 2007-03-21 | 2010-03-09 | Sun Microsystems, Inc. | Carbon nanotubes for active direct and indirect cooling of electronics device |
KR101413220B1 (ko) | 2007-10-02 | 2014-06-30 | 삼성전자주식회사 | 인터포저를 포함하는 반도체 패키지 및 반도체 패키지의 제조방법 |
US7969009B2 (en) * | 2008-06-30 | 2011-06-28 | Qualcomm Incorporated | Through silicon via bridge interconnect |
US7838337B2 (en) | 2008-12-01 | 2010-11-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming an interposer package with through silicon vias |
US20110024898A1 (en) * | 2009-07-31 | 2011-02-03 | Ati Technologies Ulc | Method of manufacturing substrates having asymmetric buildup layers |
JP5635247B2 (ja) | 2009-08-20 | 2014-12-03 | 富士通株式会社 | マルチチップモジュール |
KR101086972B1 (ko) | 2009-10-01 | 2011-11-29 | 앰코 테크놀로지 코리아 주식회사 | 관통전극을 갖는 웨이퍼 레벨 패키지 및 그 제조 방법 |
US20110241185A1 (en) | 2010-04-05 | 2011-10-06 | International Business Machines Corporation | Signal shielding through-substrate vias for 3d integration |
TWI398943B (zh) | 2010-08-25 | 2013-06-11 | Advanced Semiconductor Eng | 半導體封裝結構及其製程 |
US9007273B2 (en) | 2010-09-09 | 2015-04-14 | Advances Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
KR101817159B1 (ko) | 2011-02-17 | 2018-02-22 | 삼성전자 주식회사 | Tsv를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법 |
US8535981B2 (en) | 2011-03-10 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit package-on-package system with underfilling structures and method of manufacture thereof |
US8779562B2 (en) | 2011-03-24 | 2014-07-15 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer shield and method of manufacture thereof |
US9013037B2 (en) * | 2011-09-14 | 2015-04-21 | Stmicroelectronics Pte Ltd. | Semiconductor package with improved pillar bump process and structure |
US8659126B2 (en) | 2011-12-07 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit ground shielding structure |
-
2011
- 2011-12-28 US US13/339,266 patent/US9059179B2/en active Active
-
2012
- 2012-12-10 TW TW101146368A patent/TWI485838B/zh not_active IP Right Cessation
- 2012-12-27 KR KR1020120154173A patent/KR101436980B1/ko not_active IP Right Cessation
- 2012-12-28 CN CN201210585220.6A patent/CN103187377B/zh active Active
-
2015
- 2015-04-30 US US14/701,388 patent/US9431371B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070080442A1 (en) * | 2004-03-18 | 2007-04-12 | Georg Meyer-Berg | Semiconductor module having a coupling substrate, and methods for its production |
US20100327424A1 (en) * | 2009-06-24 | 2010-12-30 | Henning Braunisch | Multi-chip package and method of providing die-to-die interconnects in same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI727996B (zh) * | 2015-12-18 | 2021-05-21 | 美商英特爾Ip公司 | 具有暴露在側壁上之導電佈線的中介件 |
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US9059179B2 (en) | 2015-06-16 |
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CN103187377B (zh) | 2017-04-26 |
US20150235992A1 (en) | 2015-08-20 |
KR101436980B1 (ko) | 2014-09-02 |
US20130168854A1 (en) | 2013-07-04 |
US9431371B2 (en) | 2016-08-30 |
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