CN114038809A - 用于系统级封装设备的与铜柱连接的裸管芯智能桥 - Google Patents
用于系统级封装设备的与铜柱连接的裸管芯智能桥 Download PDFInfo
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- CN114038809A CN114038809A CN202111003328.5A CN202111003328A CN114038809A CN 114038809 A CN114038809 A CN 114038809A CN 202111003328 A CN202111003328 A CN 202111003328A CN 114038809 A CN114038809 A CN 114038809A
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
一种系统级封装设备包括半导体桥,该半导体桥使用裸管芯柱与诸如处理器管芯的半导体器件耦合。该设备实现了薄形状因子。
Description
本申请为分案申请,其原申请是于2019年5月29日(国际申请日为 2016年12月29日)向中国专利局提交的专利申请,申请号为 201680091214.1,发明名称为“用于系统级封装设备的与铜柱连接的裸管芯智能桥”。
技术领域
本公开涉及系统级封装配置,其中裸管芯半导体连接器与两个器件之间的铜柱耦合。
背景技术
封装小型化带来了器件集成挑战,其中薄型设备是有用的,但在使封装小型化的同时,有源和无源器件两者的互连需要物理保护和热管理。
附图说明
在附图的图示中通过举例而非限制的方式示出了所公开的实施例,在附图中类似的附图标记指代相似的元件,在附图中:
图1A是根据实施例的包括半导体桥的系统级封装设备的截面立视图;
图1B是根据实施例的图1A中所示的系统级封装设备在组装期间的截面立视图;
图1C是根据实施例的在进一步处理图1B中所示结构之后的图1A中所示系统级封装设备的截面立视图;
图1D是根据实施例的在进一步处理图1C中所示结构之后的图1A中所示系统级封装设备的截面立视图;
图1E是根据实施例的在进一步处理图1D中所示结构之后的图1A中所示系统级封装设备的截面立视图;
图2A是根据实施例的包括重新分布层以及至少半导体桥和第一集成电路管芯的系统级封装设备的截面立视图;
图2B是根据实施例的在进一步处理例如图1B和图1C中所示结构之后的图2A中所示系统级封装设备的截面立视图;
图2C是根据实施例的在进一步处理图2B中所示结构之后的图2A中所示系统级封装设备的截面立视图;
图3是根据实施例的包括重新分布层和包括穿硅过孔的半导体桥中的至少一个的系统级封装设备的截面立视图;
图4是根据实施例的包括多个半导体桥的系统级封装设备的截面立视图;
图5是根据实施例示出了包括耦合到互连柱的至少一个半导体桥的系统级封装的组装的工艺流程图;以及
图6被包括以示出用于所公开实施例的更高级器件应用的示例。
具体实施方式
公开的实施例包括裸管芯智能连接器,其使用附着在诸如模制化合物的块体中的半导体桥。智能连接器耦合到用于耦合诸如处理器的半导体器件的互连柱。
图1A是根据实施例的包括半导体桥10的系统级封装设备100的截面立视图。半导体桥10可以被称为智能管芯连接器10。半导体桥10可以被称为裸管芯硅桥10。
半导体桥10附着在诸如包封材料110的块体110中。半导体桥10包括有源表面112和背侧表面114。块体110包括管芯侧116和连接盘侧118。在实施例中,背侧表面114被完全包围在块体110中。
在实施例中,块体110为用于包封诸如半导体桥10的半导体器件的模制化合物。在实施例中,块体110为用于包封诸如半导体桥10的半导体器件的诸如热固化树脂材料的模制化合物。
系统级封装(SiP)设备100还包括也附着在块体110中的互连封装13。在实施例中,互连封装13为层合结构13,其在管芯侧116和连接盘侧118 之间提供互连-和-迹线互连(如图2C所示)。在实施例中,互连封装13为包括过孔条(如图2B所示)的贯穿封装过孔结构13,过孔条直接在管芯侧116和连接盘侧118之间穿过互连封装13。在实施例中,互连封装13由诸如FR4构造的有机材料制成。在实施例中,互连封装13由半导体材料制成。在实施例中,互连封装13由诸如玻璃构造的无机材料制成。
在实施例中,诸如处理器逻辑管芯11的半导体器件11附着在诸如模制封盖120的封盖材料120中。在实施例中,封盖材料120任选地是光学固化树脂。在实施例中,封盖材料是与块体110不同质量的热固化树脂。半导体器件11还可以被称为集成电路(IC)管芯11。在实施例中,处理器逻辑管芯11是由加利福尼亚圣克拉拉的英特尔公司制造的处理器。半导体器件11与半导体桥10的电子通信是由第一多个互连柱促成的,附图标记 121指示了其中一个互连柱。半导体器件11还通过第三多个互连柱耦合到互连封装13,由附图标记123指示其中一个互连柱。
在实施例中,半导体器件11是第一半导体器件11,并且诸如存储器管芯12的第二半导体器件12附着在封盖材料120中。在实施例中,第二半导体器件12是由犹他州Lehi的IM闪存技术所制造的存储器管芯。在存储器管芯实施例中,第二半导体器件12也可以被称为IC存储器管芯12。第二半导体器件12与半导体桥10的电子通信是由第二多个互连柱促成的,附图标记122指示了其中一个互连柱。
在实施例中,互连封装13是第一互连封装13,并且第二互连封装14 也附着在块体110中。在实施例中,第二互连封装14为层合结构14,其在管芯侧116和连接盘侧118之间提供互连-和-迹线互连。在实施例中,第二互连封装14为贯穿封装过孔结构14,其包括管芯侧116和连接盘侧118之间的过孔条。
在实施例中,SiP设备100包括诸如二极管15的无源部件15。在实施例中,无源部件15为平衡-不平衡转换器(balun)15,并且第二半导体器件12是由平衡-不平衡转换器15辅助的基带处理器。无源部件15与半导体桥10的电子通信是由第五多个互连柱促成的,附图标记125示出了其中一个互连柱。
提供封盖材料120以覆盖耦合到半导体桥10的器件。在实施例中,封盖材料是模制封盖化合物。
图1B是根据实施例的图1A中所示SiP设备在组装期间的截面立视图101。在-Z和X中给出了笛卡尔坐标系,因为图1B所示的结构将在进一步处理之后被垂直翻转。提供释放层126,半导体桥10以翻转配置安装到释放层126。此外,在实施例中,第一互连封装13也被定位在释放层126上。此外,在实施例中,第二互连封装14也被定位在释放层126上。
图1C是根据实施例的在进一步处理图1B中所示结构之后的图1A中所示SiP设备100的截面立视图102。块体110已经被施加到半导体桥10、第一和第二互连封装13和14、以及释放层126。通过该工艺,物品10、13 和14被附着并且准备好被翻转以进行进一步处理。
图1D是根据实施例的在进一步处理图1C中所示结构之后的图1A中所示SiP设备100的截面立视图103。在Z和X中给出了笛卡尔坐标系,因为图1C所示的结构已经被垂直翻转。已经去除了图1C中所示的释放层 126。可以看出,示出了用于描述互连柱和电凸块两者的接合位置的接合焊盘。
图1E是根据实施例的在进一步处理图1D中所示结构之后的图1A中所示SiP设备100的截面立视图104。根据实施例,通过在占有面积121’内绘示的多个接合焊盘上原位生长柱121来实现第一多个互连柱121的放置。例如,可以通过贯穿掩模(未示出)生长互连柱121来实现含铜材料的电解沉积。在实施例中,完成给定接合焊盘上的底漆层(例如,前一金属膜,例如金)的无电镀沉积,之后是互连等级铜的电解沉积。根据实施例,通过在占有面积122’内绘示的多个接合焊盘上原位生长柱122来实现第二多个互连柱122的放置。根据实施例,通过在占有面积123’内绘示的多个接合焊盘上原位生长柱123来实现第三多个互连柱123的放置。根据实施例,通过在占有面积124’内绘示的多个接合焊盘上原位生长柱124来实现第四多个互连柱124的放置。根据实施例,通过在占有面积125’内绘示的多个接合焊盘上原位生长柱125来实现第五多个互连柱125的放置。现在可以理解,根据所需的给定有用应用,互连柱组中的每者可以单独生长,或者可以建立所示的柱的子组。在实施例中,所有图示的柱都是同时原位生长的。
再次参考图1A。在先前的附图中的任何附图中所示的处理之后,在互连封装上形成电凸块阵列,其中的一个连接盘侧凸块利用附图标记128被列举。在实施例中,板130被组装到电凸块阵列128。具体而言,电凸块阵列128可以被称为连接盘侧凸块阵列128。
包含半导体桥10的SiP实施例的有用应用包括由于处于例如大约10 微米和50微米之间的范围内的互连柱的长度而引起的降低的Z高度。包含半导体桥10的SiP实施例的有用应用包括由于半导体桥10与互连封装13 大致位于相同Z位置、并且块体110的材料质量足够硬以排除内核材料的使用而引起的降低的Z高度。
在实施例中,半导体桥10被称为智能桥10,其中后段制程(BEOL) 金属化连接第一IC器件11和第二IC器件12之间的智能桥10中的逻辑。在实施例中,智能桥10包括连接第一IC器件11和第二IC器件12之间的智能桥10中的微控制器逻辑的BEOL金属化。在实施例中,智能桥10包括连接第一IC器件11和第二IC器件12之间的智能桥10中的外部传感器逻辑的BEOL金属化。在实施例中,智能桥10包括连接存储器控制器逻辑的BEOL金属化,并且智能桥10中没有存储器功能,但存储器控制器逻辑影响第一IC器件11和存储器IC器件12之间的通信。在实施例中,智能桥10包括包含切换逻辑的BEOL金属化,所述切换逻辑例如用于第一IC器件11和第二IC器件12之间的省电功能或例如温度控制功能。
图2A是根据实施例的包括重新分布层20以及至少半导体桥10和第一 IC管芯11的系统级封装设备200的截面立视图。重新分布层(RDL)20 是有用的,其中,在示例性实施例中,特别是在例如半导体桥10和给定互连封装13之间的区域中希望有增大的引脚数。例如,RDL 20扩展了设计自由度,因为互连柱不需要束缚到半导体桥10上的给定焊盘位置,也不需要束缚到给定互连封装的给定焊盘位置,或是这两者都不需要。在非限制例示性实施例中,可以看出,第一和第三互连柱占有面积121'和123'分别具有在其间从第一IC管芯11连接到RDL 20的若干互连柱(作为非限制性示例示出了三个),并且出于例示的目的,且并非必要,但三个图示的互连柱不在半导体桥10正上方,也不在第一互连封装13正上方。类似地,在非限制例示性实施例中,可以看出,第二和第四互连柱占有面积122'和124’分别具有在其间从第二IC管芯12连接到RDL 20的若干互连柱。应当理解, RDL 20未必在任何互连柱和例如互连柱正下方的器件之间提供直接的Z方向接触,尽管不排除这种直接Z方向接触。
图2B是根据实施例的在进一步处理例如图1B和图1C中所示结构之后的图2A中所示SiP设备200的截面立视图203。不使用项目2A和2B。已经去除了图1C中所示的释放层126。可以看出,互连封装13和14中的接合焊盘被示为与连接盘侧118基本平齐,但RDL 20排除了用于半导体桥 10以及互连封装13和14的接合焊盘的明确图示,其中半导体桥10以及封装13和14与块体110的管芯侧116基本平齐。
图2C是根据实施例的在进一步处理图2B中所示结构之后的图2A中所示SiP设备200的截面立视图204。通过本文针对图1E中所示实施例所公开的任何技术来实现若干多个互连柱121、122、123、124和125的放置。可以看出,示出了比在占有面积121'、122'、123'、124'和125'内分类的那些互连柱更多的互连柱,以便适应实施例中的更高的引脚数。在实施例中,引脚数可以更高或更低,但可以改变若干互连柱的放置以方便RDL 20。
现在可以理解,可以将过孔-柱互连封装13用作任何给定实施例中的互连封装之一或两者。现在可以理解,可以将过孔-迹线互连封装14用作任何给定实施例中的互连封装之一或两者。现在可以理解,可以在任何给定实施例中一起使用过孔-柱互连封装13和过孔-迹线互连封装14的组合。
图3是根据实施例的包括重新分布层10和包括穿硅过孔(TSV)的半导体桥10中的至少一个的系统级封装设备300的截面立视图,利用附图标记310例示穿硅过孔之一。可以看出,已经改变了Z方向的几何结构,以允许半导体桥10的背侧114与块体110的连接盘侧118基本平齐。该配置允许TSV 310被凸块连接在连接盘侧凸块阵列128的层级。
在实施例中,SiP 300可以被配置为没有RDL 20(将互连柱限制到所枚举的占有面积),并且半导体桥10提供了通往连接盘侧118的TSV通信。在没有RDL的实施例中,不使用互连封装(13或14),使得通往连接盘侧 118的所有通信都通过TSV 310。在没有RDL的实施例中,不使用互连封装(13或14),使得通往连接盘侧118的所有通信都通过TSV 310。在没有RDL的实施例中,仅使用一个互连封装(例如,封装13),使得通往连接盘侧118的所有通信部分通过互连封装13,并且部分通过TSV 310。
在包括RDL 20的实施例中,不使用互连封装(13或14),使得通往连接盘侧118的所有通信都通过TSV 310。在包括RDL 20的实施例中,仅使用一个互连封装(例如,封装13),使得通往连接盘侧118的所有通信部分通过互连封装13,并且部分通过TSV 310。
图4是根据实施例的包括多个半导体桥10和16的系统级封装设备400 的截面立视图。在SiP设备400中看到了与前文公开的实施例的相似性。在实施例中,半导体桥10为第一半导体桥10,并且半导体桥16是后续半导体桥16。后续半导体桥16包括有源表面132和背侧表面134。在仅有两个半导体桥的情况下,可以将后续半导体桥16称为第二半导体桥16。
可以看出,几个互连柱耦合器件以及互连封装13、14和18,使得电子通信可以通过几个互连柱系列而从IC管芯11到外部装置17是连续的。在实施例中,外部装置17是具有镜头17’的相机。在实施例中,外部装置 17包括触敏显示屏17’。在实施例中,外部装置17包括用户接口17’。
尽管SiP设备400被示为裸管芯半导体桥耦合的设备,但要理解,在互连柱系列和块体110的管芯侧116之间可以使用RDL,如其它公开的实施例中所示。
图5是工艺流程图500,其示出了根据实施例的包括耦合到互连柱的至少一个半导体桥的SiP的组装。
在510处,该过程包括将半导体桥和互连封装附接到释放层。
在520处,该过程包括将半导体桥和互连封装附着在块体中。
在530处,该过程包括移除释放层。
在540处,该过程包括将第一、第二和第三多个互连柱组装到半导体桥。
在550处,该过程包括将第一半导体器件组装到第一和第三多个互连柱。
在560处,该过程包括施加封盖材料以覆盖第一半导体器件并接触互连柱。
在570处,该过程包括将SiP(包括智能桥)组装到计算系统。
图6被包括以示出用于所公开实施例的更高级器件应用的示例。在实施例中,计算系统600包括但不限于台式计算机。在实施例中,系统600 包括但不限于膝上型计算机。在实施例中,系统600包括但不限于上网本。在实施例中,系统600包括但不限于平板电脑。在实施例中,系统600包括但不限于笔记本计算机。在实施例中,系统600包括但不限于个人数字助理(PDA)。在实施例中,系统600包括但不限于服务器。在实施例中,系统600包括但不限于工作站。在实施例中,系统600包括但不限于蜂窝电话。在实施例中,系统600包括但不限于移动计算装置。在实施例中,系统600包括但不限于智能电话。在实施例中,系统600包括但不限于互联网应用设备。其它类型的计算装置可以被配置有包括具有半导体桥实施例的系统级封装设备的微电子装置。
在一些实施例中,具有半导体桥实施例600的系统级封装设备包括片上系统(SoC)系统。
在实施例中,处理器610具有一个或多个处理内核612和612N,其中 612N代表处理器610内部的第N个处理器内核,其中N是正整数。在实施例中,电子装置系统600使用具有包括多个处理器(包括610和605)的半导体桥实施例的系统级封装,其中处理器605具有的逻辑类似或等同于处理器610的逻辑。在实施例中,处理内核612包括但不限于用于抓取指令的预抓取逻辑、用于对指令解码的解码逻辑、用于执行指令的执行逻辑、等等。在实施例中,处理器610具有高速缓存存储器616以高速缓存用于 SiP装置系统600的指令和数据中的至少一者。高速缓存存储器616可以被组织成包括高速缓存存储器的一个或多个层级的分级结构。
在实施例中,处理器610包括存储器控制器614,其可操作用于执行使得处理器610能够访问存储器630并与其通信的功能,存储器630包括易失性存储器632和非易失性存储器634中的至少一种。在实施例中,处理器610与存储器630和芯片组620耦合。处理器610还可以耦合到无线天线678,以与被配置为发射无线信号和接收无线信号中的至少一者的任何装置通信。在实施例中,无线天线接口678根据但不限于IEEE 802.11标准及其相关系列、Home Plug AV(HPAV)、超宽带(UWB)、蓝牙、WiMax或任何形式的无线通信协议而进行操作。
在实施例中,易失性存储器632包括但不限于同步动态随机存取存储器(SDRAM)、动态随机存取存储器(DRAM)、RAMBUS动态随机存取存储器(RDRAM)和/或任何其它类型的随机存取存储器件。非易失性存储器634包括但不限于闪存存储器、相变存储器(PCM)、只读存储器(ROM)、电可擦可编程只读存储器(EEPROM)、或任何其它类型的非易失性存储器件。
存储器630存储要由处理器610执行的信息和指令。在实施例中,存储器630还可以存储在处理器610执行指令时的临时变量或其它中间信息。在例示的实施例中,芯片组620经由点到点(PtP或P-P)接口617和622 与处理器610连接。可以使用本公开中阐述的具有半导体实施例的系统级封装设备来实现这些PtP实施例中的任一种。芯片组620使得处理器610 能够连接到SiP装置系统600中的其它元件。在实施例中,接口617和622 根据诸如快速路径互连(QPI)等的PtP通信协议而进行操作。在其它实施例中,可以使用不同的互连。
在实施例中,芯片组620可操作用于与处理器610、605N、显示装置 640和其它装置672、676、674、660、662、664、666、677等通信。芯片组620还可以耦合到无线天线678,以与被配置为至少完成发射无线信号和接收无线信号的其中之一的任何装置通信。
芯片组620经由接口626连接到显示装置640。例如,显示器640可以是液晶显示器(LCD)、等离子体显示器、阴极射线管(CRT)显示器或任何其它形式的视觉显示装置。在实施例中,处理器610和芯片组620被合并到单个SOC中。此外,芯片组620连接到互连各种元件674、660、662、 664和666的一个或多个总线650和655。总线650和655可以经由总线桥 672互连在一起。在实施例中,芯片组620与非易失性存储器660、大容量存储装置662、键盘/鼠标664、以及经由接口624和674中的至少一个的网络接口666、智能电视676和消费电子装置677等耦合。
在实施例中,大容量存储装置662包括但不限于固态驱动器、硬盘驱动器、通用串行总线闪存存储器驱动器、或任何其它形式的计算机数据存储介质。在一个实施例中,网络接口666是通过任何类型的公知网络接口标准实施的,包括但不限于以太网接口、通用串行总线(USB)接口、外围部件互连(PCI)快速接口、无线接口和/或任何其它适当类型的接口。在一个实施例中,无线接口根据但不限于IEEE 802.11标准及其相关系列、 Home Plug AV(HPAV)、超宽带(UWB)、蓝牙、WiMax或任何形式的无线通信协议而进行操作。
尽管图6中所示的模块被示为计算系统600中的SiP设备内的独立块,但这些块中的一些所执行的功能可以集成于单个半导体电路内或者可以使用两个或更多个独立集成电路来实施。例如,尽管高速缓存存储器616被图示为处理器610内的独立块,但高速缓存存储器616(或616的选定方面) 可以被并入处理器内核612中。
在有用的情况下,计算系统600可以具有外壳,外壳是将要附接在本公开中所述的凸块阵列128处的若干连接盘侧板实施例的部分。在图1A中,板130被耦合到电凸块阵列128。在实施例中,外壳131是板130上的电绝缘结构,其还为SiP设备100提供物理保护。
现在可以理解,可以将板130实施例应用于每个所图示并描述的电凸块阵列128。
为了例示本文所公开的系统级封装设备实施例中的存储器-管芯堆叠存储器模块和方法,本文提供了示例的非限制性列表:
示例1是一种系统级封装设备,包括:固定于块体中的半导体桥,该半导体桥包括有源表面和背侧表面,并且该块体包括管芯侧和连接盘侧;从有源表面延伸的第一和第二多个互连柱;固定于块体中的互连封装,其中该互连封装从管芯侧连通到连接盘侧;在管芯侧处设置于互连封装上的第三多个互连柱;耦合到第一和第三多个互连柱的第一半导体管芯;耦合到第二多个互连柱的第二半导体管芯;并且其中第一和第二半导体管芯黏附在封盖材料中,并且其中封盖材料接触第二和第三多个互连柱。
在示例2中,示例1的主题任选地包括:其中互连封装为第一互连封装,还包括:固定于块体中的第二互连封装,其中第二互连封装从管芯侧连通到连接盘侧;在管芯侧处设置于第二互连封装上的第四多个互连柱,其中第二和第四多个互连柱耦合到第二半导体管芯,并且其中封盖材料接触第四多个互连柱。
在示例3中,示例1-2的任一个或多个的主题任选地包括在设置于第一和第二多个互连柱之间的第五多个互连柱处耦合到半导体桥的无源器件。
在示例4中,示例1-3的任一个或多个的主题任选地包括:其中互连封装为第一互连封装,还包括:固定于块体中的第二互连封装,其中第二互连封装从管芯侧连通到连接盘侧;在管芯侧设置于第二互连封装上的第四多个互连柱,其中第二和第四多个互连柱耦合到第二半导体管芯,并且其中封盖材料接触第四多个互连柱;其中第一半导体器件为处理器器件,并且其中第二半导体管芯是存储器件。
在示例5中,示例1-4的任一个或多个所述的主题任选地包括设置在连接盘侧上并耦合到互连封装的电凸块阵列。
在示例6中,示例1-5的任一个或多个所述的主题任选地包括:邻接若干多个互连柱的重新分布层,并且其中重新分布层在有源表面和管芯侧的层级接触半导体桥和互连封装。
在示例7中,示例6所述的主题任选地包括:其中互连封装为第一互连封装,还包括:固定于块体中的第二互连封装,其中第二互连封装从管芯侧连通到连接盘侧;在管芯侧上方的重新分布层处设置于第二互连封装上的第四多个互连柱,其中第二和第四多个互连柱通过重新分布层耦合到第二半导体管芯,并且其中封盖材料接触第四多个互连柱和重新分布层。
在示例8中,示例6-7的任一个或多个的主题任选地包括由设置于第一和第二多个互连柱之间的第五多个互连柱耦合到重新分布层的无源器件。
在示例9中,示例8所述的主题任选地包括其中无源器件是二极管。
在示例10中,示例1-9的任一个或多个所述的主题任选地包括其中背侧表面完全包围在块体中。
在示例11中,示例1-10的任一个或多个所述的主题任选地包括:其中半导体桥包括穿硅过孔,并且其中背侧表面从块体暴露,还包括:设置于连接盘侧上并耦合到互连封装的电凸块阵列;并且其中电凸块阵列包括背侧表面处的半导体桥上的电凸块,其中穿硅过孔耦合到电凸块。
在示例12中,示例11的主题任选地包括:其中互连封装为第一互连封装,还包括:固定于块体中的第二互连封装,其中第二互连封装从管芯侧向连接盘侧连通;在管芯侧设置于第二互连封装上的第四多个互连柱,其中第二和第四多个互连柱耦合到第二半导体管芯,并且其中封盖材料接触第四多个互连柱。
在示例13中,示例12所述的主题任选地包括在设置于第一和第二多个互连柱之间的第五多个互连柱处耦合到半导体桥的无源器件。
在示例14中,示例1-13的任一个或多个所述的主题任选地包括组装到互连封装的电凸块阵列;以及组装到电凸块阵列的板。
在示例15中,示例1-14的任一个或多个所述的主题任选地包括:其中互连封装为块体的管芯侧和连接盘侧之间的互连-和-迹线连接。
在示例16中,示例1-15的任一个或多个所述的主题任选地包括:其中互连封装为块体的管芯侧和连接盘侧之间的贯穿封装过孔结构连接。
在示例17中,示例1-16的任一个或多个所述的主题任选地包括:其中块体是热固化树脂,并且其中封盖材料是光学固化树脂。
示例18是一种系统级封装设备,包括:半导体桥,该半导体桥包括有源表面和背侧表面;从有源表面延伸的第一和第二多个互连柱;包括管芯侧和连接盘侧的互连封装,其中该互连封装从管芯侧连通到连接盘侧;在管芯侧设置于互连封装上的第三多个互连柱;耦合到第一和第三多个互连柱的第一半导体管芯;耦合到第二多个互连柱的第二半导体管芯;并且其中第一和第二半导体管芯附着在封盖材料中,并且其中封盖材料接触第二和第三多个互连柱。
在示例19中,示例18的主题任选地包括:其中互连封装为第一互连封装,还包括:包括管芯侧和连接盘侧的第二互连封装,管芯侧和连接盘侧与第一互连封装的管芯侧和连接盘侧基本共平面;在管芯侧设置于第二互连封装上的第四多个互连柱,其中第二和第四多个互连柱耦合到第二半导体管芯,并且其中封盖材料接触第四多个互连柱。
在示例20中,示例18-19的任一个或多个的主题任选地包括在设置于第一和第二多个互连柱之间的第五多个互连柱处耦合到半导体桥的无源器件。
示例21是一种组装包含桥的系统级封装(SiP)设备的方法,包括:将半导体桥和互连封装附接到释放层,其中半导体桥包括有源表面和背侧表面;将半导体桥和互连封装附着在块体中;去除释放层;将第一和第二多个互连柱组装到半导体桥;将第三多个互连柱组装到互连封装;将逻辑管芯耦合到第一和第三多个互连柱;以及将逻辑管芯和多个互连柱附着在封盖材料中,其中封盖材料接触半导体桥的有源表面。
在示例22中,示例21的主题任选地包括:其中互连封装为第一互连封装,还包括:将第二互连封装附接到释放层;将第二互连封装附着在块体中;将第四多个互连柱组装到第二互连封装;将存储器管芯耦合到第二和第四多个互连柱;以及将存储器管芯和多个互连柱附着在封盖材料中。
在示例23中,示例22的主题任选地包括:其中半导体桥为第一半导体桥,该方法还包括:将第三互连封装和第二半导体桥附接到释放层;将第三互连封装和第二半导体桥附着在块体中;将用户接口耦合到第三互连封装和第二半导体桥;以及将用户结构附着在封盖材料中。
在示例24中,示例23的主题任选地包括在连接盘侧将电凸块阵列组装到第一、第二和第三互连封装;以及将板组装到电凸块阵列。
在示例25中,示例21-24的任一个或多个所述的主题任选地包括:在连接盘侧将电凸块阵列组装到互连封装;以及将板组装到电凸块阵列。
示例26是包含系统级封装(SiP)设备的计算系统,包括:固定于块体中的半导体桥,该半导体桥包括有源表面和背侧表面,并且块体包括管芯侧和连接盘侧;第一和第二多个互连柱从有源表面延伸;固定于块体中的第一互连封装,其中第一互连封装从管芯侧连通到连接盘侧;在管芯侧设置于互连封装上的第三多个互连柱;固定于块体中的第二互连封装,其中第二互连封装从管芯侧连通到连接盘侧;在管芯侧设置于第二互连封装上的第四多个互连柱;耦合到第一和第三多个互连柱的第一半导体管芯;耦合到第二和第四多个互连柱的第二半导体管芯;其中第一和第二半导体管芯附着在封盖材料中,并且其中封盖材料接触第一、第二和第三多个互连柱;在连接盘侧耦合到第一和第二互连封装的电凸块阵列;以及耦合到电凸块阵列的板,其中板包括为SiP设备提供电绝缘的外壳。
在示例27中,示例26的主题任选地包括固定于块体中的第二半导体桥;固定于块体中的第三互连封装,其中第三互连封装在管芯侧和连接盘侧被暴露;以及耦合到第二半导体桥和第三互连封装的用户接口。
以上具体实施方式包括对附图的引用,附图形成具体实施方式的部分。附图通过例示的方式示出了可以实践本发明的具体实施例。本文中也将这些实施例称为“示例”。这样的示例可以包括除所示或所述那些之外的元件。然而,本发明还构想了仅提供所图示或描述的那些元件的示例。此外,本发明人还构想了使用针对特定示例(或其一个或多个方面)、或针对本文所示或所述的其它示例(或其一个或多个方面)所图示或描述的那些元件的任何组合或排列的示例(或其一个或多个方面)。
在本文和通过引用的方式并入的任何文献之间的用法不一致的情况下,以本文中的用法为主。
在本文中,如专利文献中常用的,使用术语“一”包括一个或超过一个,与“至少一个”或“一个或多个”的任何其它实例或使用无关。在本文中,使用术语“或”表示非排他性的或,使得“A或B”包括“A但无B”、“B但无A”以及“A和B”,除非另外指明。在本文中,术语“包括(including)”和“其中(in which)”被用作相应术语“包括(comprising)”和“其中(wherein)”的通俗英语等价词。而且,在以下权利要求书中,术语“包括”是开放式的,亦即,包括除了权利要求中在这样的术语之后所列的那些之外的元件的系统、装置、物品、组成、制剂或工艺仍然被认为落在该权利要求的范围内。此外,在以下权利要求书中,术语“第一”、“第二”和“第三”等仅仅被用作标记,并非旨在对其对象施加数值要求。
本文描述的方法示例可以至少部分由机器或计算机实施。一些示例可以包括利用指令编码的计算机器可读介质或机器可读介质,所述指令可操作用于配置电气装置以执行在以上示例中描述的方法。这种方法的一种实施方式可以包括代码,例如微码、汇编语言代码、高级语言代码等。这样的代码可以包括用于执行各种方法的计算机可读指令。代码可以形成计算机程序产品的部分。此外,在示例中,代码可以例如在执行期间或在其它时间有形地存储于一种或多种易失性、非暂态、或非易失性有形计算机可读介质上。这些有形计算机可读介质的示例可以包括但不限于硬盘、可移除磁盘、可移除光盘(例如,压缩盘和数字视频盘)、磁带、存储卡或存储棒、随机存取存储器(RAM)、只读存储器(ROM)等。
以上描述旨在是示例性的而非限制性的。例如,可彼以此结合地使用上述示例(或其一个或多个方面)。本领域的普通技术人员在研究以上描述之后,例如可以使用其它实施例。提供摘要以符合37C.F.R.§1.72(b),从而允许读者快速掌握技术公开的性质。在理解摘要将不会用于解释或限制权利要求的范围或含义的情况下提交摘要。而且,在以上具体实施方式中,可以将各种特征分组在一起,以简化本公开。这不应当被解释为旨在表示未主张权利的所公开特征对任何权利要求是必要的。相反,发明的主题可以在于少于特定所公开实施例的所有特征。于是,由此将以下权利要求并入具体实施方式作为示例或实施例,每个权利要求自身代表独立的实施例,并且可以设想,这样的实施例可以通过各种组合或排列而彼此组合。应当参考所附权利要求、连同为这样的权利要求赋予权利的等同物的完整范围来确定本发明的范围。
Claims (20)
1.一种系统级封装设备,包括:
模制化合物中的半导体桥,所述半导体桥具有顶表面、底表面、第一侧和第二侧,所述半导体桥包括多个穿硅过孔,并且所述半导体桥包括逻辑单元;
与所述半导体桥的所述第一侧横向相邻的第一多个互连;
与所述半导体桥的所述第二侧横向相邻的第二多个互连;
电耦合到所述半导体桥的所述顶表面的第一IC器件,并且所述第一IC器件电耦合到所述第一多个互连;
电耦合到所述半导体桥的所述顶表面的第二IC器件,并且所述第二IC器件电耦合到所述第二多个互连;以及
在所述第一IC器件和所述第二IC器件之间并与所述第一IC器件和所述第二IC器件接触的封盖材料。
2.根据权利要求1所述的系统级封装设备,其中,所述封盖材料进一步在所述第一IC器件和所述第二IC器件之上。
3.根据权利要求1所述的系统级封装设备,其中,所述封盖材料进一步沿着所述第一IC器件的最外侧和所述第二IC器件的最外侧。
4.根据权利要求1所述的系统级封装设备,其中,所述封盖材料进一步在所述第一IC器件和所述第二IC器件之上,并且其中,所述封盖材料进一步沿着所述第一IC器件的最外侧和所述第二IC器件的最外侧。
5.根据权利要求1所述的系统级封装设备,其中,所述第一多个互连在第一互连封装中,并且所述第二多个互连在第二互连封装中。
6.根据权利要求1所述的系统级封装设备,其中,所述第一多个互连是第一多个过孔条,并且所述第二多个互连是第二多个过孔条。
7.根据权利要求1所述的系统级封装设备,其中,所述模制化合物在所述半导体桥的所述底表面上。
8.根据权利要求1所述的系统级封装设备,还包括:
电耦合到所述半导体桥的所述顶表面的第三IC器件,其中,所述第三IC器件在所述第一IC器件和所述第二IC器件之间。
9.根据权利要求8所述的系统级封装设备,其中,所述第三IC是无源器件。
10.根据权利要求1所述的系统级封装设备,其中,所述第一IC器件通过第一多个柱电耦合到所述半导体桥的所述顶表面并电耦合到所述第一多个互连,并且其中,所述第二IC器件通过第二多个柱电耦合到所述半导体桥的所述顶表面并电耦合到所述第二多个互连。
11.一种系统级封装设备,包括:
半导体桥,其具有顶表面、底表面、第一侧和第二侧,所述第二侧与所述第一侧相对,并且所述半导体桥包括多个穿硅过孔;
与所述半导体桥横向相邻的模制化合物,所述模制化合物与所述半导体桥的所述第一侧和所述第二侧直接接触;
与所述半导体桥的所述第一侧横向相邻的第一多个互连;
与所述半导体桥的所述第二侧横向相邻的第二多个互连;
电耦合到所述半导体桥的所述顶表面的第一IC器件,并且所述第一IC器件电耦合到所述第一多个互连;
电耦合到所述半导体桥的所述顶表面的第二IC器件,并且所述第二IC器件电耦合到所述第二多个互连;以及
在所述第一IC器件和所述第二IC器件之间并与所述第一IC器件和所述第二IC器件接触的封盖材料。
12.根据权利要求11所述的系统级封装设备,其中,所述第一多个互连与所述半导体桥的所述第一侧横向相邻并与所述半导体桥的所述第一侧间隔开,并且通过第一材料与所述半导体桥的所述第一侧分开。
13.根据权利要求12所述的系统级封装设备,其中,所述第二多个互连与所述半导体桥的所述第二侧横向相邻并与所述半导体桥的所述第二侧间隔开,并且通过第二材料与所述半导体桥的所述第二侧分开。
14.根据权利要求11所述的系统级封装设备,其中,所述半导体电桥是智能桥。
15.根据权利要求11所述的系统级封装设备,其中,所述封盖材料是固化树脂。
16.根据权利要求11所述的系统级封装设备,其中,所述第一多个互连是穿过第一互连封装的第一多个过孔条,并且所述第二多个互连是穿过第二互连封装的第二多个过孔条。
17.根据权利要求11所述的系统级封装设备,其中,所述第一多个互连被包括在与所述模制化合物不同的第一互连封装中,并且所述第二多个互连被包括在与所述模制化合物不同的第二互连封装中。
18.根据权利要求11所述的系统级封装设备,其中,所述模制化合物在所述半导体桥的所述底表面上并与所述半导体桥的所述底表面接触。
19.根据权利要求11所述的系统级封装设备,还包括:
介于所述第一IC器件和所述第二IC器件之间的第三IC器件。
20.根据权利要求19所述的系统级封装设备,其中,所述第三IC包括平衡-不平衡转换器。
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