CN108630655B - 嵌入式桥衬底连接器及其组装方法 - Google Patents

嵌入式桥衬底连接器及其组装方法 Download PDF

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Publication number
CN108630655B
CN108630655B CN201810153109.7A CN201810153109A CN108630655B CN 108630655 B CN108630655 B CN 108630655B CN 201810153109 A CN201810153109 A CN 201810153109A CN 108630655 B CN108630655 B CN 108630655B
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reference layer
die
bond
side module
coupled
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CN108630655A (zh
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B·魏达斯
G·塞德曼
A·沃尔特
T·瓦格纳
S·施特克尔
L·米楼
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Intel Corp
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Intel Corp
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Abstract

嵌入式桥衬底连接器装置包括图案化参考层,第一模块和随后的模块与图案化参考层对准,且这两个模块在图案化参考层处配对。至少一个模块包括通过图案化参考层桥接到两个设备、到配对的模块的硅桥连接器。

Description

嵌入式桥衬底连接器及其组装方法
技术领域
本公开涉及用于制造系统级封装连接的嵌入式桥技术。
背景技术
封装小型化在实现较小的尺寸同时实现增加的连接需求之间产生紧张。
附图说明
所公开的实施例作为例子而不是作为限制在附图中示出,其中相似的附图标记可以指代相似的元件,其中:
图1A是根据实施例的在系统级封装装置中的嵌入式桥连接器的横截面立视图;
图1B是根据实施例的在进一步的处理之后的在图1A中示出的装置的横截面立视图;
图1C是根据实施例的在进一步的处理之后的在图1B中示出的装置的横截面立视图;
图1D是根据实施例的在进一步的处理之后的在图1C中示出的装置的横截面立视图;
图1E是根据实施例的在进一步的处理之后的在图1D中示出的装置的横截面立视图;
图1F是根据实施例的在进一步的处理之后的在图1E中示出的装置的横截面立视图;
图1G是根据实施例的在进一步的处理之后的在图1F中示出的装置的横截面立视图;
图1H是根据实施例的在进一步的处理之后的在图1G中示出的装置的横截面立视图;
图1I是根据实施例的在进一步的处理之后的在图1H中示出的装置的横截面立视图;
图1J是根据实施例的在进一步的处理之后的在图1I中示出的装置的横截面立视图;
图1K是根据实施例的从图1J截取的详细截面;
图2是根据实施例的嵌入式桥衬底装置的横截面立视图;
图3是示出根据实施例的嵌入式桥衬底连接器装置的组装的过程流程图;以及
图4被包括以示出所公开的实施例的较高级设备应用的例子。
具体实施方式
所公开的实施例包括在系统级封装装置的嵌入式桥连接器装置的组装期间的设备的自对准。实施例允许在封装管芯的桥接配置中的面对面管芯堆叠。在实施例中,第二层的每个管芯可以面对面地连接到在管芯封装的第一层中的至少一个管芯。层可被称为模块。由于封装组装过程实施例的自对准,面对面连接也在细间距应用中实现,封装组装过程实施例使用每个模块所配对的参考层。在组装期间提供参考层提高了X-Y容限。提供参考层还提高了Z容限,因为桥接配置与否则可能需要被多重地堆叠的结构交叠。
图1A是根据实施例的在系统级封装装置101中的嵌入式桥连接器的横截面立视图。导电箔110被组装到载体112,准备用于图案化参考层。在实施例中,载体112包括释放层114、厚铜载体箔116、预浸渍层118和例如用于印刷电路板组装的核心材料120。在实施例中,导电箔110是铜材料。
图1B是根据实施例的在进一步的处理之后的在图1A中示出的装置110的横截面立视图102。例如用于镀覆光致抗蚀剂的图案化掩模122布置在载体112之上的导电箔110上。可例如通过在光致抗蚀剂上旋涂、平面化和图案化来处理图案化掩模122以打开到导电箔110的通道。
图1C是根据实施例的在进一步的处理之后的在图1B中示出的装置102的横截面立视图103。通过使用导电箔110作为镀覆阴极来将参考层124穿过图案化掩模122镀覆到几个通道内。在实施例中,参考层124是通过电镀而被镀覆的铜材料。参考层124是分立的一组导电材料,但它被称为“参考层”124,因为构造的对称性(或非对称性)可从参考层124来确定。
图1D是根据实施例的在进一步的处理之后的在图1C中示出的装置103的横截面立视图104。在实施例中,通过湿法蚀刻移除了图案化掩模122(见图1C),湿法蚀刻使用针对留下参考层124和导电箔110而选择的湿法蚀刻化学试剂。在实施例中,通过等离子体灰化过程来移除图案化掩模122。现在可看到,参考层124是占据实质上相同的Z方向空间的分立的一组导电材料。在下文中,参考层124也可被称为图案化参考层124,但在任何情况下,它都被表示为占据相同的Z方向空间的分立的一系列导电材料。
图1E是根据实施例的在进一步的处理之后的在图1D中示出的装置104的横截面立视图105。一系列设备被组装到图案化参考层124。可看到,第一球栅阵列被组装到图案化参考层124,第一球栅阵列的一个焊球用附图标记126指示。看到在第一球栅阵列126中的每个焊球出现在载体112之上的Z方向上的实质上相同的高度处,如通过将第一球栅阵列126组装在参考层124上所确定的。在如图1D所示的实施例中,可看到,第一球栅阵列126具有不一定在整个装置105上是几何地对称的独特图案,但它被图案化以与各种设备连接。
各种设备被组装在第一球栅阵列126上。在实施例中,每个设备的Z高度是不同的。
在实施例中,第一设备128(例如基带处理器128)伴随有第二设备130。在实施例中,第二设备130是集成无源设备130,例如平衡-不平衡转换器(balun)130,且它在图案化参考层124上与第一设备128并排地组装在一起。在实施例中,第一设备128——虽然它具有内在(intrinsic)半导体设备应用——也具有半导体桥电路。在下文中,虽然设备在被指定的情况下既可具有内在半导体设备应用且它也用作半导体桥,它也将被称为具有“硅桥”功能,尽管其它半导体材料(例如III-V材料)也可用于实现半导体桥。
在实施例中,第三设备132具有硅桥功能,但它也承载例如存储器管芯132的有用半导体功能。在只有第一设备128和第三设备132存在的情况下,第三设备132可被称为相邻于第一设备128的设备132。
在实施例中,第四设备134同时具有硅桥功能和半导体逻辑功能,例如处理器134。在实施例中,提供随后的设备136,且虽然它没有硅桥功能(见图1H),但是它具有例如存储器管芯136的有用的半导体功能。
图1F是根据实施例的在进一步的处理之后的在图1E中示出的装置105的横截面立视图106。根据实施例,模制化合物138在几个设备128、130、132、134和136之上流动,且流动包括在图案化参考层124和球栅阵列126处的底部填充。根据实施例,在底部填充和覆盖在几个设备之下和之上的模制化合物138之后,处理包括平面化和修剪模制化合物138。在实施例中,模制化合物138被称为管芯侧包封体138。
图1G是根据实施例的在进一步的处理之后的在图1F中示出的装置106的横截面立视图107。在正X和负Z坐标中示出装置107,因为装置107被反转(与图1F相比较)以进行进一步的处理。在图1A中示出的释放层114被激活,使得载体112被移除。此外,在实施例中,也通过抛光过程来移除导电箔110,抛光过程是针对在图案化参考层124被暴露时停止而选择的。可使用其它移除技术。根据实施例,布置在模制化合物138中的包封设备可被称为管芯侧模块140。
图1H是根据实施例的在进一步的处理之后的在图1G中示出的装置107的横截面立视图108。也在正X和负Z坐标中示出装置108。
根据实施例,在自对准技术中,嵌在管芯侧模块140中的设备被通过参考层124接触。在实施例中,第一印刷线路板(PWB)142布置成与至少一个设备接触。在所示实施例中,第一PWB 142接触第一设备128和第二设备130。在实施例中,随后的PWB 144与至少一个设备接触。在所示实施例中,随后的PWB 144与第四设备134和随后的设备136接触。在实施例中,当在平面图中观察装置108时,第一PWB 142和随后的PWB 144是单个结构,例如“相框”矩形。相框这一名称也可被称为开放框,其中第一PWB 142和随后的PWB 144是开放框结构的整体部分。
硅桥接在管芯侧模块140中的设备和布置在被第一和随后的PWB 142和144占用的相同Z坐标区附近的设备之间实现。用附图标记146将这个区指示为焊接区侧(land-side)模块146。
在实施例中,第一焊接区侧设备148接触参考层124并充当在第一设备128和第三设备132之间的硅桥148。在实施例中,除了提供硅桥功能以外,第一焊接区侧设备148还提供内在逻辑功能,例如存储器控制器。
在实施例中,第二焊接区侧设备150接触参考层124并充当在第三设备132和第四设备134之间的硅桥150。在实施例中,除了提供硅桥功能以外,第二焊接区侧设备150还提供内在逻辑功能,例如专用集成电路(ASIC)。
在实施例中,随后的焊接区侧设备152接触参考层124并通过参考层124与在管芯侧模块140中的第四设备134直接通信。可看到,在管芯侧模块140中的第四设备134与随后的焊接区侧设备152交叠,并且第四设备134也充当硅桥,其桥接在第二焊接区侧设备150和随后的PWB 144之间并且桥接在第二焊接区侧设备150和随后的焊接区侧设备152之间。
每个焊接区侧设备通过在第二球栅阵列中的电气焊凸耦合到图案化参考层124,其中一个焊凸用附图标记154来指示。
图1I是根据实施例的在进一步的处理之后的在图1H中示出的装置108的横截面立视图109。也在正X和负Z坐标中示出装置109。完成另外的处理,其中焊接区侧包封体156靠着管芯侧包封体138流动。可看到,焊接区侧模块146包括焊接区侧包封体156,且本质上被包围在焊接区侧包封体156内。
图1J是根据实施例的在进一步的处理之后的在图1I中示出的装置109的横截面立视图100。装置100相对于图1I反转,以示出正X和正Z坐标。管芯侧模块140借助通过参考层124自对准来与焊接区侧模块146配对。
焊接区侧焊球阵列靠着第一PWB 142和随后的PWB 144而布置。如可看到的,焊接区侧模块146被凸块形成(be bumped)有焊接区侧焊球阵列,该焊接区焊球阵列中的一个焊球在第一PWB 142处用附图标记158来指示。类似地,焊接区侧焊球阵列被凸块形成在随后的PWB 144上,焊接区侧焊球阵列的一个焊球用附图标记160来指示。在相应的第一和随后的PWB 142和144是单一的、例如相框PWB的情况下,焊接区侧焊球阵列158和160是同一焊接区侧焊球阵列的部分。
现在可理解,“嵌入式桥”被定义为这样的半导体结构,其不仅提供在两个其它半导体设备之间的物理接触通信,而且嵌入式桥在至少三个表面上被嵌入材料(例如模制化合物138)接触。因此在图1J中,在第一设备128、第三设备132、第四设备134和随后的设备136中找到三个嵌入式桥实例。因此也如可在图2中看到的,虽然第三和第四设备132和134分别由结构132’和134’加衬背(be backed),这些设备仍然均在三个表面上被模制化合物138接触。
图1K是根据实施例的从图1J截取的详细截面XZ。当测量在参考层124的中心处开始的比较距离(comparative distance)时,存在一致的非对称比(asymmetry ratio)。使用平分参考层124的对称线162,取从对称线162到在管芯侧模块140中的接合焊盘164的管芯侧距离124E。类似地,使用对称线162,取从对称线162到在焊接区侧模块146中的接合焊盘166的焊接区侧距离124A。
现在可理解,一致的非对称比存在于跨对称线162的Z方向上。一致的非对称比存在于管芯侧模块140中的任何给定设备之间,所述设备是面对面的并与焊接区侧模块146中的焊接区侧设备耦合。该一致的非对称比存在于焊凸尺寸在相应的模块中可以不同的实施例中。各种距离124E和124A的测量在对称线162处开始并在相应的接合焊盘处结束,其中接合焊盘164和166是面对面的。
各种厚度的设备可排列在管芯侧模块140中。类似地,变化的厚度的设备和PWB可排列在焊接区侧模块146中。不考虑设备和PWB的变化的厚度,一致的非对称比存在于垂直地接近且跨对称线162交叠(面对面)的任两个设备之间。“垂直地接近和交叠”意指两个设备的至少部分是面对面的,并通过参考层124电气地耦合。一致的非对称比是在管芯侧模块140中的设备的任何有源表面和在焊接区侧模块146中面对面的焊接区侧设备的有源表面之间的比较距离。
例如,第三设备132布置成垂直地接近第二焊接区侧设备150(面对面),并且在它们的有源表面(在X方向上)交叠的情况下,存在从对称线162到第三设备132的有源表面(在接合焊盘164处示出)的管芯侧距离124E,并且存在从对称线162到第二焊接区侧设备150的有源表面(在接合焊盘166处示出)的焊接区侧距离124A。这两个距离提供在组装具有封装设备和可选地具有封装PWB的装置的参数内的可测量的比。这些参数包括在X-Y维度上和在Z维度上的参照容限(fiduciary tolerance)。
再次参考图1J。为了进一步示出一致的非对称比,第四设备134也布置成垂直地接近第二焊接区侧设备150(面对面),并且在它们的有源表面(在X方向上)交叠的情况下,存在从对称线162到第三设备132的有源表面(在接合焊盘168处示出)的管芯侧距离,并且存在从对称线162到第二焊接区侧设备150的有源表面(在接合焊盘170处示出)的焊接区侧距离。这两个距离也提供可测量的比。而且一致的非对称比可被理解为:在接合焊盘164和166之间的离对称线162的距离的比与在接合焊盘168和170之间的离对称线162的距离的比相同。
为了进一步说明,第四设备134也布置成垂直地接近第三焊接区侧设备152(面对面),并且在它们的有源表面(在X方向上)交叠的情况下,存在从对称线162到第四设备134的有源表面(在接合焊盘172处示出)的管芯侧距离,以及从对称线162到第三焊接区侧设备152的有源表面(在接合焊盘174处示出)的焊接区侧距离。这意味着在接合焊盘164和166之间的离对称线162的距离的比与在接合焊盘172和174之间的离对称线162的距离的比相同。同样,这意味着在接合焊盘168和170之间的距离的比与在接合焊盘172和174之间的距离的比相同。
再次参考图1K。现在可通过所公开的距离的比的定义来理解术语“一致地非对称”。为了说明,从对称线162到接合焊盘164的距离(管芯侧距离124E)可被定义为单位一,从对称线162到接合焊盘166的距离(焊接区侧距离124A)可被定义为单位一的两倍。因此,距离之比是0.5:1,且将在Z方向上垂直地接近(面对面)并且在X方向上交叠的任两个设备之间测量该一致的非对称性。
再次参考图1J。为了进一步说明,从对称线162到接合焊盘172的距离定义为单位一(因为它是从对称线162到接合焊盘164的相同距离),从对称线162到接合焊盘174的距离被测量为单位一的两倍(因为它是从对称线162到接合焊盘166的相同距离)。因此,距离之比也为0.5:1。
图2是根据实施例的嵌入式桥衬底装置200的横截面立视图。焊接区侧焊球阵列158和160接触板176,例如母板176。在实施例中,板176具有充当计算设备的外壳178的外表面178。
在实施例中,管芯侧模块140和焊接区侧模块146包括板178和电源180。在实施例中,电源180安装在焊接区侧模块146和板176之间。在实施例中,电源180安装在焊接区侧模块146和板176之间,但它部分地在板176中凹进(如图所示)。在实施例中,电源180安装在焊接区侧模块146和板176之间,但它部分地在焊接区侧包封体156中凹进。在实施例中,电源180安装在焊接区侧模块146和板176之间,但它部分地在板176中凹进(如图所示),并且它也部分地在焊接区侧包封体156中凹进。
在实施例中,用户接口182布置在管芯侧模块140的顶部上。在实施例中,用户接口182是触敏显示器182。用户接口182到电源的耦合可由接触板176的穿模具过孔184实现。
在实施例中,例如当第四设备134是处理器时,热管理由例如生热设备辅助,其中热沉134’给第四设备134加衬背,结构182的一部分充当热交换器。类似地,在实施例中,对例如设备132(例如存储器-控制器集线器132)的热管理由热沉132’辅助,热沉132’给第三设备132加衬背,结构182的一部分充当散热器。
图3是示出根据实施例的嵌入式桥衬底连接器装置的组装的过程流程图300。
在310,过程包括在由载体支撑的导电膜上图案化掩模。
在320,过程包括通过在图案化掩模中的通道形成参考层。导电膜用作阴极以镀覆参考层。
在322,过程包括移除图案化掩模。在实施例中,掩模可被保留为焊凸模板。
在330,过程包括将半导体设备在焊球阵列处附接到参考层。
在340,过程包括包封半导体设备,既包封在该设备之上,也对该设备进行底部填充。
在350,过程包括移除载体和导电箔。载体和箔的移除得到管芯侧模块。
在360,过程包括通过图案化参考层将焊接区侧设备附接到管芯侧模块。
在362,过程包括将至少一个印刷线路板附接到管芯侧模块。
在370,过程包括将焊接区侧设备和印刷线路板(如果存在的话)包封在焊接区侧包封体中。
在380,过程包括将焊接区侧模块和管芯侧模块组装到计算设备。
图4被包括以示出所公开的实施例的较高级设备应用的例子。可在计算系统的几个部分中找到自对准嵌入式桥衬底连接器实施例。在实施例中,计算系统400包括但不限于桌上型计算机。在实施例中,系统400包括但不限于膝上型计算机。在实施例中,系统400包括但不限于上网本。在实施例中,系统400包括但不限于平板计算机。在实施例中,系统400包括但不限于笔记本计算机。在实施例中,系统400包括但不限于个人数字助理(PDA)。在实施例中,系统400包括但不限于服务器。在实施例中,系统400包括但不限于工作站。在实施例中,系统400包括但不限于蜂窝电话。在实施例中,系统400包括但不限于移动计算设备。在实施例中,系统400包括但不限于智能电话。在实施例中,系统400包括但不限于互联网设备。其它类型的计算设备可配置有包括嵌入式桥衬底连接器装置实施例的微电子设备。
在实施例中,处理器410具有一个或多个处理核心412和412N,其中412N代表在处理器410内部的第N个处理器核心,其中N是正整数。在实施例中,电子设备系统400使用包括多个处理器(包括410和405)的嵌入式桥衬底连接器实施例,其中处理器405具有与处理器410的逻辑相似或相同的逻辑。在实施例中,处理核心412包括但不限于提取指令的预取逻辑、对指令解码的解码逻辑、执行指令的执行逻辑等。在实施例中,处理器410具有高速缓存存储器416以缓存系统400中的管芯上电源网装置(power mesh-on-die apparatus)的指令和数据中的至少一个。高速缓存存储器416可被组织成包括高速缓存存储器的一个或多个级的分级结构(hierarchal structure)。
在实施例中,处理器410包括存储器控制器414,其可操作来执行使处理器410能够访问存储器430并与存储器430通信的功能,存储器430包括易失性存储器432和非易失性存储器434中的至少一个。在实施例中,处理器410与存储器430和芯片组420耦合。处理器410也可耦合到无线天线478以与配置成进行下列操作中的至少一个的任何设备进行通信:传输无线信号以及接收无线信号。在实施例中,无线天线接口478根据——但不限于——IEEE802.11标准及其相关系列、家庭插电AV(HPAV)、超宽带(UWB)、蓝牙、WiMax或任何形式的无线通信协议来操作。
在实施例中,易失性存储器432包括但不限于同步动态随机存取存储器(SDRAM)、动态随机存取存储器(DRAM)、RAMBUS动态随机存取存储器(RDRAM)和/或任何其它类型的随机存取存储器设备。非易失性存储器434包括但不限于闪存、相变存储器(PCM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)或任何其它类型的非易失性存储器设备。
存储器430存储信息和指令以由处理器410执行。在实施例中,存储器430还可在处理器410执行指令时存储临时变量或其它中间信息。在所示实施例中,芯片组420经由点对点(PtP或P-P)接口417和422与处理器410连接。这些PtP实施例中的任一个可使用在本公开内容中所阐述的嵌入式桥衬底连接器装置实施例来实现。芯片组420使处理器410能够连接到系统400中的嵌入式桥衬底连接器装置中的其它元件。在实施例中,接口417和422根据PtP通信协议(例如QuickPath互连(QPI)等)来操作。在其它实施例中,可使用不同的互连。
在实施例中,芯片组420可操作来与处理器410、405N、显示设备440以及其它设备472、476、474、460、462、464、466、477等通信。芯片组420也可耦合到无线天线478以与配置成执行下列操作中的至少一个的任何设备进行通信:传输无线信号和接收无线信号。
芯片组420经由接口426连接到显示设备440。显示器440可以是例如液晶显示器(LCD)、等离子体显示器、阴极射线管(CRT)显示器或任何其它形式的视觉显示设备。在实施例中,处理器410和芯片组420合并到系统中的嵌入式桥衬底连接器装置内。此外,芯片组420连接到互连各种元件474、460、462、464和466的一个或多个总线450和455。总线450和455可经由总线桥472(例如至少一个嵌入式桥衬底连接器装置实施例)互连在一起。在实施例中,芯片组420经由接口424和474、智能TV 476和消费电子设备477等中的至少一个而与非易失性存储器460、大容量存储设备462、键盘/鼠标464和网络接口466耦合。
在实施例中,大容量存储设备462包括但不限于固态驱动器、硬盘驱动器、通用串行总线闪存驱动器或任何其它形式的计算机数据存储介质。在一个实施例中,网络接口466由任何类型的公知网络接口标准——包括但不限于以太网接口、通用串行总线(USB)接口、外设部件互连(PCI)Express接口、无线接口和/或任何其它适当类型的接口来实现。在一个实施例中,无线接口根据——但不限于——IEEE 802.11标准及其相关系列、家庭插电AV(HPAV)、超宽带(UWB)、蓝牙、WiMax或任何形式的无线通信协议来操作。
虽然图4所示的模块被示出为在计算系统400中的嵌入式桥衬底连接器装置实施例中的单独块,但是由这些块中的一些执行的功能可集成在单个半导体电路内或可使用两个或更多个单独的集成电路来实现。例如,虽然高速缓存存储器416被示出为在处理器410内的单独块,高速缓存存储器416(或416的选定方面)可合并到处理器核心412内。
在有用的情况下,计算系统400可具有外壳,例如在图2中示出的外壳164。在实施例中,外壳是也提供对嵌入式桥衬底连接器装置实施例的物理保护的电绝缘结构。
为了说明在本文公开的嵌入式桥衬底连接器装置实施例和方法,在本文提供了例子的非限制性列表:
例子1是嵌入式桥衬底连接器装置,其包括:图案化参考层,其耦合到管芯侧模块,管芯侧模块包括第一设备和被包封在管芯侧模块中的随后的设备,其中第一设备和随后的设备中的每个电气地耦合到图案化参考层;耦合到管芯侧模块的焊接区侧模块,其包括被包封在焊接区侧模块中的焊接区侧设备,并且其中焊接区侧设备通过参考层电气地耦合到第一设备;并且其中第一设备和第一焊接区侧设备中的一个是用于通过图案化参考层在管芯侧模块和焊接区侧模块中的一个或另一个中的相邻设备之间电气地通信的硅桥。
在例子2中,例子1的主题可选地包括相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理地和通信地桥接在第一设备和第三设备之间。
在例子3中,例子1-2中的任一个或多个的主题可选地包括相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理地和通信地桥接在第一设备和第三设备之间;以及与第三设备相对(opposite)并相邻于第一设备的第二设备,其中第二设备通过参考层电气地耦合到在焊接区侧模块中的第一印刷线路板。
在例子4中,例子1-3中的任一个或多个的主题可选地包括相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理地和通信地桥接在第一设备和第三设备之间;与第三设备相对并相邻于第一设备的第二设备,其中第二设备通过参考层电气地耦合到在焊接区侧模块中的第一印刷线路板;并且其中随后的设备通过参考层耦合到在焊接区侧模块中的随后的印刷线路板。
在例子5中,例子1-4中的任一个或多个的主题可选地包括相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理地和通信地桥接在第一设备和第三设备之间;与第三设备相对并相邻于第一设备的第二设备,其中第二设备通过参考层电气地耦合到在焊接区侧模块中的第一印刷线路板;其中随后的设备通过参考层耦合到在焊接区侧模块中的随后的印刷线路板;以及通过焊接区侧焊球阵列耦合到第一印刷线路板的板。
在例子6中,例子1-5中的任一个或多个的主题可选地包括相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理地和通信地桥接在第一设备和第三设备之间;与第三设备相对并相邻于第一设备的第二设备,其中第二设备通过参考层电气地耦合到在焊接区侧模块中的第一印刷线路板;其中随后的设备通过参考层耦合到在焊接区侧模块中的随后的印刷线路板;通过焊接区侧焊球阵列耦合到第一印刷线路板的板;以及耦合到管芯侧模块并由穿模具过孔电气地耦合到板的用户接口。
在例子7中,例子6的主题可选地包括,其中第一印刷线路板和随后的印刷线路板是开放框架结构的整体部分。
在例子8中,例子2-7中的任一个或多个的主题可选地包括相邻于第一设备的第二设备,其中第二设备通过参考层耦合到在焊接区侧模块中的第一印刷线路板;以及在焊接区侧模块中的第二焊接区侧设备,其中第二焊接区侧设备通过图案化参考层耦合到管芯侧模块。
在例子9中,例子2-8中的任一个或多个的主题可选地包括相邻于第一设备的第二设备,其中第二设备通过参考层耦合到在焊接区侧模块中的第一印刷线路板;相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理和通信地桥接在第一设备和第三设备之间;以及在焊接区侧模块中的第二焊接区侧设备,其中第二焊接区侧设备通过图案化参考层耦合到第三设备。
在例子10中,例子2-9中的任一个或多个的主题可选地包括相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理和通信地桥接在第一设备和第三设备之间;相邻于第三设备的第四设备,其中第四设备电气地耦合到参考层;以及在焊接区侧模块中的第二焊接区侧设备,其中第二焊接区侧设备通过图案化参考层耦合到第三设备和第四设备。
在例子11中,例子2-10中的任一个或多个的主题可选地包括相邻于第一设备的第三设备,其中第三设备电气地耦合到参考层,并且其中第一焊接区侧设备物理和通信地桥接在第一设备和第三设备之间;相邻于第三设备的第四设备,其中第四设备电气地耦合到参考层;在焊接区侧模块中的第二焊接区侧设备,其中第二焊接区侧设备通过图案化参考层耦合到第三设备和第四设备;以及布置在焊接区侧模块中并通过图案化参考层耦合到第四设备的第三焊接区侧设备,其中第四设备与第三焊接区侧设备交叠。
例子12是组装嵌入式桥衬底连接器装置的方法,其包括:将掩模图案化到安装在载体上的导电箔上;通过在掩模中的通道并在导电箔上镀覆参考层;将第一半导体设备在焊球阵列处附接到参考层;包封第一半导体设备,既包封在设备之上也在焊球阵列和参考层处对设备进行底部填充,以实现管芯侧模块;将焊接区侧第一设备附接到在管芯侧模块中的第一设备;以及包封第一焊接区侧设备以实现焊接区侧模块。
在例子13中,例子12的主题可选地包括在附接第一半导体设备之前移除掩模。
在例子14中,例子12-13中的任一个或多个的主题可选地包括移除掩模;附接第一设备;以及将随后的设备附接到参考层。
在例子15中,例子12-14中的任一个或多个的主题可选地包括移除掩模;附接第一设备;将随后的设备附接到参考层;以及将第三设备附接到参考层,其中第一焊接区侧设备物理和通信地桥接在第一设备和第三设备之间。
在例子16中,例子12-15中的任一个或多个的主题可选地包括通过耦合到第一设备来将第一印刷线路板附接到管芯侧模块。
在例子17中,例子12-16中的任一个或多个的主题可选地包括通过耦合到第一设备来将第一印刷线路板附接到管芯侧模块;以及通过耦合到随后的设备来将随后的印刷线路板附接到管芯侧模块。
在例子18中,例子12-17中的任一个或多个的主题可选地包括通过耦合到第一设备来将第一印刷线路板附接到管芯侧模块;以及通过焊接区侧焊球阵列来将焊接区侧模块附接到板。
例子19是包含嵌入式桥衬底连接器装置的计算系统,嵌入式桥衬底连接器装置包括:图案化参考层,其耦合到管芯侧模块,管芯侧模块包括第一设备和被包封在管芯侧模块中的随后的设备,其中第一设备和随后的设备中的每个电气地耦合到图案化参考层;耦合到管芯侧模块的焊接区侧模块,其包括被包封在焊接区侧模块中的焊接区侧设备的,并且其中焊接区侧设备通过参考层电气地耦合到第一设备;其中第一设备和第一焊接区侧设备中的一个是用于通过图案化参考层在管芯侧模块和焊接区侧模块中的一个或另一个中的相邻设备之间电气地通信的硅桥;以及耦合到焊接区侧模块的板,其中板包括用于计算系统的电绝缘外壳。
在例子20中,例子19的主题可选地包括用户接口,其包括触敏显示器。
上面的具体实施方式包括对附图的引用,附图形成具体实施方式的一部分。附图作为例证示出本发明可被实践的具体实施例。这些实施例也在本文被称为“例子”。这样的例子可包括除了所示或所述的元件以外的元件。然而,本发明的发明人还设想其中只提供了所示或所述的那些元件的例子。而且,本发明的发明人还设想关于特定的例子(或其一个或多个方面)或关于在本文所示或所述的其它例子(或其一个或多个方面),使用所示或所述的那些元件的任何组合或置换的例子(或其一个或多个方面)。
在本文件和通过引用被这样并入的任何文件之间的不一致使用的情况下,以本文件中的使用为准。
在这个文件中,如在专利文件中常见的,使用术语“一(a)”或“一个(an)”以包括一个或多于一个,独立于“至少一个”或“一个或多个”的任何其它实例或使用。在这个文件中,术语“或”用于指非排他的或,使得“A或B”包括“A但不是B”、“B但不是A”以及“A和B”,除非另外表明。在这个文件中,术语“包括(including)”和“其中(in which)”分别用作相应的术语“包括(comprising)”和“其中(wherein)”的简明英语等效形式。而且在下面的权利要求中,术语“包括(including)”和“包括(comprising)”是开放的,也就是说,在权利要求中包括除了在这样的术语之后列出的那些元件以外的元件的系统、设备、物品、组成、配方或过程仍然被认为落在那个权利要求的范围内。而且,在下面的权利要求中,术语“第一”、“第二”、“第三”等仅用作标记,且并不打算将数字要求强加在它们的对象上。
本文所述的方法例子可以至少部分地是机器或计算机实现的。一些例子可包括计算机可读介质或机器可读介质,其被通过可操作来配置电气设备以执行如在上面的例子中所述的方法的指令来编码。这样的方法的实施方式可包括代码,例如微代码、汇编语言代码、高级语言代码等。这样的代码可包括用于执行各种方法的计算机可读指令。代码可形成计算机程序产品的部分。此外,在例子中,代码可例如在执行期间或在其它时间有形地存储在一个或多个易失性、非临时或非易失性有形计算机可读介质上。这些有形计算机可读介质的例子可包括但不限于硬盘、可移动磁盘、可移动光盘(例如紧致盘和数字通用盘)、磁带、存储卡或记忆棒、随机存取存储器(RAM)、只读存储器(ROM)等。
上面的描述意图是例证性的而不是限制性的。例如,上面所述的例子(或其一个或多个方面)可彼此组合地使用。其它实施例可例如由本领域中的普通技术人员在审阅上面的描述后使用。提供摘要以符合37C.F.R.§1.72(b),以允许读者快速确定技术公开内容的性质。基于摘要将不用于解释或限制权利要求的范围或含义的理解而提交摘要。此外,在上面的具体实施方式中,各种特征可被分组在一起以使本公开内容简单化。这不应被解释为目的在于未主张的所公开的特征对任何权利要求而言是必不可少的。更确切地,创造性主题可体现在特定的所公开的实施例的少于全部的特征。因此,下面的权利要求特此被并入具体实施方式中作为例子或实施例,每个权利要求独立地作为单独的实施例,且设想这样的实施例可在各种组合或置换中彼此组合。应参考所附权利要求连同这样的权利要求被赋予权利的等效形式的整个范围来确定本发明的范围。

Claims (20)

1.一种嵌入式桥衬底连接器装置,包括:
图案化参考层,其包括管芯侧和焊接区侧,其中,所述图案化参考层被嵌入管芯侧包封体并且所述图案化参考层的各部分均从所述管芯侧包封体暴露出来,其中,所述图案化参考层耦合到管芯侧模块,所述管芯侧模块包括第一设备和被包封在所述管芯侧包封体中的随后的设备,其中所述第一设备和所述随后的设备中的每个设备电气地耦合到所述图案化参考层;
耦合到所述管芯侧模块的焊接区侧模块,其包括被包封在焊接区侧包封体中的第一焊接区侧设备,并且其中,所述第一焊接区侧设备通过所述图案化参考层电气地耦合到所述第一设备,其中,所述图案化参考层由所述管芯侧的电气焊凸和所述焊接区侧的电气焊凸接触,其中,所述电气焊凸中的第一电气焊凸接触所述图案化参考层和所述第一设备,并且其中,所述电气焊凸中的第二电气焊凸接触所述图案化参考层和所述第一焊接区侧设备;并且
其中,所述第一设备和第一焊接区侧设备之一是硅桥,用于通过所述图案化参考层在所述管芯侧模块和所述焊接区侧模块中的一个或另一个中的相邻设备之间电气地通信。
2.如权利要求1所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间。
3.如权利要求1所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间;以及
与所述第三设备相对并相邻于所述第一设备的第二设备,其中所述第二设备通过所述参考层电气地耦合到在所述焊接区侧模块中的第一印刷线路板。
4.如权利要求1所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间;
与所述第三设备相对并相邻于所述第一设备的第二设备,其中所述第二设备通过所述参考层电气地耦合到在所述焊接区侧模块中的第一印刷线路板;并且
其中所述随后的设备通过所述参考层耦合到在所述焊接区侧模块中的随后的印刷线路板。
5.如权利要求1所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间;
与所述第三设备相对并相邻于所述第一设备的第二设备,其中所述第二设备通过所述参考层电气地耦合到在所述焊接区侧模块中的第一印刷线路板;
其中所述随后的设备通过所述参考层耦合到在所述焊接区侧模块中的随后的印刷线路板;以及
通过焊接区侧焊球阵列耦合到所述第一印刷线路板的板。
6.如权利要求1所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间;
与所述第三设备相对并相邻于所述第一设备的第二设备,其中所述第二设备通过所述参考层电气地耦合到在所述焊接区侧模块中的第一印刷线路板;
其中所述随后的设备通过所述参考层耦合到在所述焊接区侧模块中的随后的印刷线路板;
通过焊接区侧焊球阵列耦合到所述第一印刷线路板的板;以及
耦合到所述管芯侧模块并由穿模具过孔电气地耦合到所述板的用户接口。
7.如权利要求6所述的嵌入式桥衬底连接器装置,其中所述第一印刷线路板和所述随后的印刷线路板是开放框架结构的整体部分。
8.如权利要求2所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第二设备,其中所述第二设备通过所述参考层耦合到在所述焊接区侧模块中的第一印刷线路板;以及
在所述焊接区侧模块中的第二焊接区侧设备,其中所述第二焊接区侧设备通过所述图案化参考层耦合到所述管芯侧模块。
9.如权利要求2所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第二设备,其中所述第二设备通过所述参考层耦合到在所述焊接区侧模块中的第一印刷线路板;
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间;以及
在所述焊接区侧模块中的第二焊接区侧设备,其中所述第二焊接区侧设备通过所述图案化参考层耦合到所述第三设备。
10.如权利要求2所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间;
相邻于所述第三设备的第四设备,其中所述第四设备电气地耦合到所述参考层;以及
在所述焊接区侧模块中的第二焊接区侧设备,其中所述第二焊接区侧设备通过所述图案化参考层耦合到所述第三设备和所述第四设备。
11.如权利要求2所述的嵌入式桥衬底连接器装置,还包括:
相邻于所述第一设备的第三设备,其中所述第三设备电气地耦合到所述参考层,并且其中所述第一焊接区侧设备物理和通信地桥接在所述第一设备和所述第三设备之间;
相邻于所述第三设备的第四设备,其中所述第四设备电气地耦合到所述参考层;
在所述焊接区侧模块中的第二焊接区侧设备,其中所述第二焊接区侧设备通过所述图案化参考层耦合到所述第三设备和所述第四设备;以及
布置在所述焊接区侧模块中并通过所述图案化参考层耦合到所述第四设备的第三焊接区侧设备,其中所述第四设备与所述第三焊接区侧设备交叠。
12.一种组装嵌入式桥衬底连接器装置的方法,包括:
将掩模图案化到安装在载体上的导电箔上;
通过在所述掩模中的通道并且在所述导电箔上镀覆参考层;
将第一设备在焊球阵列处附接到所述参考层;
包封所述第一设备,既包封在所述第一设备之上,也在所述焊球阵列和所述参考层处对所述第一设备进行底部填充,使得所述参考层的各部分均从管芯侧包封体暴露出来,以实现管芯侧模块;
通过电气焊凸将第一焊接区侧设备附接到在所述管芯侧模块中的所述第一设备,使得所述第一焊接区侧设备通过所述参考层电气地耦合到所述第一设备;以及
包封所述第一焊接区侧设备以实现焊接区侧模块。
13.如权利要求12所述的方法,还包括在附接所述第一设备之前移除所述掩模。
14.如权利要求12所述的方法,还包括:
移除所述掩模;
附接所述第一设备;以及
将随后的设备附接到所述参考层。
15.如权利要求12所述的方法,还包括:
移除所述掩模;
附接所述第一设备;
将随后的设备附接到所述参考层;以及
将第三设备附接到所述参考层,其中所述第一焊接区侧设备物理地和通信地桥接在所述第一设备和所述第三设备之间。
16.如权利要求12所述的方法,还包括通过耦合到所述第一设备来将第一印刷线路板附接到所述管芯侧模块。
17.如权利要求12所述的方法,还包括:
通过耦合到所述第一设备来将第一印刷线路板附接到所述管芯侧模块;以及
通过耦合到随后的设备来将随后的印刷线路板附接到所述管芯侧模块。
18.如权利要求12所述的方法,还包括:
通过耦合到所述第一设备来将第一印刷线路板附接到所述管芯侧模块;以及
通过焊接区侧焊球阵列来将所述焊接区侧模块附接到板。
19.一种包含嵌入式桥衬底连接器装置的计算系统,包括:
图案化参考层,其包括管芯侧和焊接区侧,其中,所述图案化参考层被嵌入管芯侧包封体并且所述图案化参考层的各部分均从所述管芯侧包封体暴露出来,其中,所述图案化参考层耦合到管芯侧模块,所述管芯侧模块包括被包封在所述管芯侧包封体中的第一设备和随后的设备,其中所述第一设备和所述随后的设备中的每个设备电气地耦合到所述图案化参考层;
耦合到管芯侧模块的焊接区侧模块,所述焊接区侧模块包括被包封在焊接区侧包封体中的第一焊接区侧设备,并且其中,所述第一焊接区侧设备通过所述图案化参考层电气地耦合到所述第一设备,其中,所述图案化参考层由所述管芯侧的电气焊凸和所述焊接区侧的电气焊凸接触,其中,所述电气焊凸中的第一电气焊凸接触所述图案化参考层和所述第一设备,并且其中,所述电气焊凸中的第二电气焊凸接触所述图案化参考层和所述第一焊接区侧设备;并且
其中,所述第一设备和所述第一焊接区侧设备之一是硅桥,所述硅桥用于通过所述图案化参考层而在所述管芯侧模块和所述焊接区侧模块中的一个或另一个中的相邻设备之间电气地通信;以及
耦合到所述焊接区侧模块的板,其中所述板包括用于所述计算系统的电绝缘外壳。
20.如权利要求19所述的计算系统,还包括用户接口,所述用户接口包括触敏显示器。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10431563B1 (en) 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US10515929B2 (en) * 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory
CN109345963B (zh) * 2018-10-12 2020-12-18 芯光科技新加坡有限公司 一种显示装置及其封装方法
US11721657B2 (en) * 2019-06-14 2023-08-08 Stmicroelectronics Pte Ltd Wafer level chip scale package having varying thicknesses
US10861766B1 (en) * 2019-09-18 2020-12-08 Delta Electronics, Inc. Package structures
US11393759B2 (en) 2019-10-04 2022-07-19 International Business Machines Corporation Alignment carrier for interconnect bridge assembly
US20220230991A1 (en) * 2021-01-21 2022-07-21 Monolithic Power Systems, Inc. Multi-die package structure and multi-die co-packing method
US11217551B1 (en) * 2021-03-23 2022-01-04 Chung W. Ho Chip package structure and manufacturing method thereof
CN114937658B (zh) * 2022-07-21 2022-10-25 湖北三维半导体集成创新中心有限责任公司 芯片系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105938802A (zh) * 2015-03-05 2016-09-14 精工半导体有限公司 树脂密封型半导体装置及其制造方法
US9549468B1 (en) * 2015-07-13 2017-01-17 Advanced Semiconductor Engineering, Inc. Semiconductor substrate, semiconductor module and method for manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5971734A (en) * 1996-09-21 1999-10-26 Anam Semiconductor Inc. Mold for ball grid array semiconductor package
US8102663B2 (en) * 2007-09-28 2012-01-24 Oracle America, Inc. Proximity communication package for processor, cache and memory
CN102460693A (zh) * 2009-06-19 2012-05-16 株式会社安川电机 电力变换装置
US8872349B2 (en) * 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US9425178B2 (en) * 2014-07-08 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. RDL-first packaging process
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9508684B2 (en) * 2015-03-05 2016-11-29 Sii Semiconductor Corporation Resin-encapsulated semiconductor device and method of manufacturing the same
JP6752553B2 (ja) * 2015-04-28 2020-09-09 新光電気工業株式会社 配線基板
US9595494B2 (en) * 2015-05-04 2017-03-14 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
JP2017092094A (ja) * 2015-11-04 2017-05-25 富士通株式会社 電子装置、電子装置の製造方法及び電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105938802A (zh) * 2015-03-05 2016-09-14 精工半导体有限公司 树脂密封型半导体装置及其制造方法
US9549468B1 (en) * 2015-07-13 2017-01-17 Advanced Semiconductor Engineering, Inc. Semiconductor substrate, semiconductor module and method for manufacturing the same

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