TWI412085B - 一浮動閘極記憶胞之程式化及清除的結構及其製造方法 - Google Patents

一浮動閘極記憶胞之程式化及清除的結構及其製造方法 Download PDF

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Publication number
TWI412085B
TWI412085B TW094129708A TW94129708A TWI412085B TW I412085 B TWI412085 B TW I412085B TW 094129708 A TW094129708 A TW 094129708A TW 94129708 A TW94129708 A TW 94129708A TW I412085 B TWI412085 B TW I412085B
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TW
Taiwan
Prior art keywords
layer
floating gate
etch stop
gate
dielectric
Prior art date
Application number
TW094129708A
Other languages
English (en)
Chinese (zh)
Other versions
TW200623275A (en
Inventor
Gowrishankar L Chindalore
Craig T Swift
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200623275A publication Critical patent/TW200623275A/zh
Application granted granted Critical
Publication of TWI412085B publication Critical patent/TWI412085B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW094129708A 2004-09-17 2005-08-30 一浮動閘極記憶胞之程式化及清除的結構及其製造方法 TWI412085B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/944,244 US7183161B2 (en) 2004-09-17 2004-09-17 Programming and erasing structure for a floating gate memory cell and method of making

Publications (2)

Publication Number Publication Date
TW200623275A TW200623275A (en) 2006-07-01
TWI412085B true TWI412085B (zh) 2013-10-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW094129708A TWI412085B (zh) 2004-09-17 2005-08-30 一浮動閘極記憶胞之程式化及清除的結構及其製造方法

Country Status (7)

Country Link
US (2) US7183161B2 (enExample)
EP (1) EP1792336A2 (enExample)
JP (1) JP5103182B2 (enExample)
KR (1) KR20070048247A (enExample)
CN (1) CN101432858B (enExample)
TW (1) TWI412085B (enExample)
WO (1) WO2006036334A2 (enExample)

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US7615445B2 (en) * 2006-09-21 2009-11-10 Sandisk Corporation Methods of reducing coupling between floating gates in nonvolatile memory
US8076229B2 (en) * 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
WO2010086067A1 (en) * 2009-01-29 2010-08-05 International Business Machines Corporation Memory transistor with a non-planar floating gate and manufacturing method thereof
US8415217B2 (en) * 2011-03-31 2013-04-09 Freescale Semiconductor, Inc. Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor

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US20040252576A1 (en) * 2001-09-19 2004-12-16 Infineon Technologies Ag Semiconductor memory element arrangement
KR20040032530A (ko) * 2002-10-10 2004-04-17 삼성전자주식회사 비휘발성 기억소자의 형성방법

Also Published As

Publication number Publication date
JP5103182B2 (ja) 2012-12-19
KR20070048247A (ko) 2007-05-08
CN101432858A (zh) 2009-05-13
US7745870B2 (en) 2010-06-29
EP1792336A2 (en) 2007-06-06
JP2008513999A (ja) 2008-05-01
WO2006036334A2 (en) 2006-04-06
TW200623275A (en) 2006-07-01
WO2006036334A3 (en) 2009-04-02
CN101432858B (zh) 2012-06-27
US20070117319A1 (en) 2007-05-24
US20060063328A1 (en) 2006-03-23
US7183161B2 (en) 2007-02-27

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