TWI404188B - 半導體元件用基板之製造方法及半導體裝置 - Google Patents
半導體元件用基板之製造方法及半導體裝置 Download PDFInfo
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Description
本發明係關於用以安裝半導體元件的半導體元件用基板。尤其是在構造面上兼備類似導線架(lead frame)特徵之基板的製造方法及使用它的半導體裝置。
以晶圓製程所製造之各種記憶體、CMOS、CPU等半導體元件具有電性連接用的端子。該電性連接用端子的間距(pitch)、及裝著半導體元件之印刷基板側的間距,其規模(scale)的差異為從數倍到數百倍左右。因此,在欲將半導體元件與印刷基板連接的情況下,可使用被稱作內插板(interposer)之用於變換間距的仲介用基板(半導體元件安裝用基板)。
將半導體元件安裝在該內插板之一方的面,在他方的面或基板周邊作成與印刷基板連接。內插板在內部或表面具有金屬導線架,利用導線架來迴繞電性連接路徑,將進行與印刷基板連接的外部連接端子的間距擴張。
第2A圖~第2C圖為先前技術之內插板的一例,示意地顯示使用QFN(Quad Flat Non-lead)式導線架之內插板構造的圖。
如第2A圖所示,將搭載半導體元件22的導線架的平坦部分21設置在由鋁或銅所構成之導線架的中央部。將寬間距的導線23配設在導線架的外周部。對於導線23與半導體元件22之電性連接用端子的連接,係藉由使用金線等金屬配線(metal wire)24的配線接合法(wire bonding method)來進行。如第2B圖所示,最終以成型用樹脂25將整體加以成型而一體化。
又,第2A圖、第2B圖中的支撐材27,係支撐導線架者,如第2C圖所示在利用成型用樹脂25成型後會被除去。但是,在第2A圖~第2C圖的內插板,由於只能在半導體元件的外周部及導線架的外周部進行電性連接,所以可說是不適用於端子數多的半導體元件。
在半導體元件端子數少的情況下,印刷基板與內插板的連接,係將金屬針(metal pin)裝著在內插板外周部的導出電極26來進行。又,在半導體元件端子數多的情況下,已知有將焊球(solder ball)以陣列狀配置在內插板的外周部的外部連接端子BGA(Ball Grid Array,球柵格陣列)。
針對面積窄、端子數多的半導體元件,在配線層為只有一層的內插板,變換間距是困難的。因此,通常採用將內插板的配線層多層化、積層的手法。
在面積窄、端子數多的半導體元件的情況下,半導體元件的連接端子大多是形成為以陣列狀配置在半導體元件的底面。因此,採用覆晶(flip chip)連接方式,其將內插板側的外部連接端子作成與半導體元件的連接端子相同的陣列狀配置,將微少的焊球使用於內插板與印刷基板的連接。內插板內的配線,係從上部在垂直方向上以鑽孔機或雷射進行穿孔,在孔內進行金屬鍍覆,藉以獲得上下的電性導通。
在由該方式所產生的內插板,由於能將外部連接端子的間距微細化至約150~200μm左右,所以能增加連接端子數。但是,接合的可靠性及穩定性降低,不能適用於要求高可靠性的車載用途等。
如此作成的內插板係藉由所使用的材料及構造,支撐導線架部分之部分的構造為陶瓷者,或是如P-BGA(Plastic Ball Grid Array,塑膠球柵格陣列)、CSP(Chip Size Package,晶片尺寸封裝)、LGA(Land Grid Array,墊柵格陣列),基材有有機物者等數種類,來根據目的用途而予以分開使用。
上述任一種內插板,亦正對應於半導體元件的小型化、多針化、高速化,而進行內插板之與半導體元件的連接部分之精細間距(fine pitch)化及高速訊號對應。一旦考慮微細化的進展,則內插板端子部分的間距必須是80~100μm。
然而,也稱為導通部兼支撐構件的導線架係蝕刻薄金屬而形成,但為了穩定地蝕刻處理及之後加工中的處置(handling),較佳地金屬板具有120μm左右的厚度。又,為了在配線接合之際獲得充分的接合強度,一定程度的金屬層厚度及墊面積是必要的。
考慮上述條件,作為金屬板厚度,100~120μm左右可說是最低必要的。在該情況下,若從金屬板兩側進行蝕刻,則導線的間距為120μm、導線線寬為60μm的精細化可說已是極限。
進一步地作為其他的問題,有由於使得在製造內插板的製程中廢棄支撐材,而產生成本增加之情事。使用第2A圖~第2C圖就此點加以說明。
導線架係貼附在由聚醯亞胺帶(polyimide tape)所構成的保持材27,以固定用樹脂或固定用帶28來將半導體元件22固定至導線架的平坦部分21。之後,進行配線接合,以成型用樹脂25利用移轉成型法(transfer mold method)將複數個晶片,即半導體元件22批次成型。最後,施加外裝加工,以使內插板成為1個1個的方式裁切而完成。
在導線架的背面29成為與印刷基板的連接面的情況,必須在成型時不會使成型用樹脂25向導線架的背面29的連接端子面滲入而附著在連接端子上。因此,在內插板的製造製程中,保持材27是必要的。但是,由於最終不要保持材27,所以在進行成型加工後,必須將保持材27取走拋棄,造成成本增加。
又,此種先前技術之一例記載於專利文獻1。即,在專利文獻1中揭露有以絕緣樹脂來支撐貫穿基板的導體柱,導體柱的部分自樹脂突出之構造。
作為解決該等問題,提供能形成超精細間距的配線(即間距極小的配線),可以穩定地配線接合加工,且在經濟性上優異類型的半導體元件用基板之方法,例如,以預成型樹脂作為配線支撐體構造的半導體元件用基板係記載於專利文獻2。
以下就記載於專利文獻2之導線架狀的半導體元件用基板的製造法加以敘述。將用以形成連接用柱的阻劑圖案形成在金屬板的第1面,將用以形成配線圖案的阻劑圖案形成在第2面,從第1面之上,將銅蝕刻至所須厚度後,將預成型用樹脂塗布在第1面,形成預成型層,之後,進行第2面的蝕刻,形成配線,最後將兩面的阻劑剝離。
在依此所製造之導線架狀的半導體元件用基板中,即使將金屬厚度縮小至可以精細蝕刻(fine etching)的水準,但由於預成型樹脂成為支撐體,所以可穩定地蝕刻。又,由於超音波能量的擴散小,所以配線接合性也優異。進一步地,由於不使用聚醯亞胺帶等之保持材,所以能藉此抑制成本增加。
[專利文獻1]特開平8-340069號公報
[專利文獻2]特開平10-223828號公報
然而,針對專利文獻2的技術有構造上的問題點。在專利文獻2的技術上,所填充的預成型用樹脂的厚度必須對於提供導線架必要的剛性是充分的程度,尚且,連接用柱的底面應完全露出。
作為如此控制厚度而塗附的方法,例如,可舉出:使用注射器(syringe),從塗附面底的一點或複數點流入預成型用樹脂,等待其潤濕擴展至整個塗布面。在該情況下,預成型用樹脂,在必須維持讓連接用柱底面露出的狀態之關係上,在預成型用樹脂的高度到達連接用柱底面之前,便必須結束預成型用樹脂的填充。結果,使得預成型用樹脂的高度變得比連接用柱還低。
在保持該狀態下,完成半導體元件用基板的情況下,連接用柱會成為從周圍的預成型用樹脂層突出的狀態,在此例如,在欲搭載焊球的情況下,會有由於搭載位置的小偏移,而球可能從連接用柱脫落,導致良率降低的問題。
有鑑於前述先前技術所存在的問題,本發明係提供一種半導體元件用基板之製造方法及半導體裝置,其能在製造附有預成型的導線架狀之半導體元件用基板的過程中,在搭載焊球時球不會從墊(land)脫落,而高良率地搭載焊球。
本發明的第1態樣為一種半導體元件用基板之製造方法,其包含:(1)將第1感光性樹脂層設置在金屬板的第1面;將第2感光性樹脂層設置在前述金屬板之與前述第1面不同的第2面;藉由根據第1圖案對前述第1感光性樹脂層進行選擇性曝光顯影,來將由已顯影之前述第1感光性樹脂層所構成且用以形成連接用柱的第1蝕刻用遮罩形成在前述金屬板之前述第1面;藉由根據第2圖案對前述第2感光性樹脂層進行選擇性曝光顯影,來將由已顯影之前述第2感光性樹脂層所構成且用以形成配線圖案的第2蝕刻用遮罩形成在前述金屬板之前述第2面;在形成前述第1蝕刻用遮罩及前述第2蝕刻用遮罩之後,(2)藉由進行自前述第1面至前述金屬板中途的蝕刻來形成前述連接用柱;將預成型用樹脂填充在前述第1面之前述連接用柱不存在的部分;將前述第1面之前述連接用柱加工以使其高度比周圍的前述預成型用樹脂還低;及進行前述第2面的蝕刻而形成前述配線圖案。
本發明之第2態樣為如本發明之第1態樣所記載之半導體元件用基板之製造方法,其中將前述預成型用樹脂填充在前述第1面之前述連接用柱不存在的部分,係包含:藉由前述預成型用樹脂來使整個前述第1面埋沒;及在前述埋沒之後,以讓前述連接用柱的底面露出的方式在厚度方向上將前述預成型用樹脂均勻地除去。
本發明之第3態樣為如本發明之第1態樣或本發明之第2態樣之任一態樣所記載之半導體元件用基板的製造方法,其中將前述第1面之前述連接用柱加工以使其高度比周圍的前述預成型樹脂還低,係藉由半蝕刻來進行。
本發明之第4態樣為一種半導體基板,其特徵為將半導體元件安裝在依本發明之第1態樣至本發明之第3態樣之任一態樣所記載之半導體元件用基板的製造方法所製得之半導體元件用基板,前述半導體元件用基板與前述半導體元件之間係藉由配線接合來電性連接。
依照本發明的話,便能在製造附預成型的半導體元件用基板之際,將連接用墊的底面高度加工成比周圍的預成型用樹脂還低。藉此,連接用墊周邊的預成型用樹脂能發揮牆壁的功能,當搭載焊球時球不會從墊脫落,能夠高良率地搭載焊球。
以下,作為依本發明之半導體元件用基板之製造方法之一實施例,以BGA型半導體元件用基板為例,使用第1A圖~第1K圖加以說明。
所製造之各個單位的BGA尺寸為10 mm見方,作成具有168針之平面視圖呈陣列狀的外部連接部者。將該BGA排版(impose)在基板上,經歷以下製造製程後進行切斷、裁切,製得各個BGA型半導體元件用基板。
首先,如第1A圖所示,準備寬度150 mm、厚度150μm之長形帶狀的銅基板1。接著,如第1B圖所示,利用輥塗布機(roll coater)以成為5μm厚度之方式將感光性阻劑2(東京應化(股)製,OFPR4000)塗布在銅基板1的兩面,然後在90℃進行預烘烤。
接著,隔著具有所須圖案之圖案曝光用光罩,從兩面進行圖案曝光,之後以1%氫氧化鈉溶液進行顯影處理後,進行水洗及後烘烤,如第1C圖所示製得第1阻劑圖案3及第2阻劑圖案7。
又,在銅基板1之一方的面側(與搭載半導體元件10的面相反側的面,以下記為第1面側),形成用以形成連接用柱5的第1阻劑圖案3。又,在銅基板1之他方的面側(搭載半導體元件10的面,以下記為第2面側),形成用以形成配線圖案的第2阻劑圖案7。
又,將半導體元件10搭載在基板中央部的導線架上面。關於本實施例的配線圖案,係將配線接合用墊(wire bonding land)4形成在半導體元件10之外周附近的導線架的外周上面。以金細線8連接半導體元件10的外周與墊4。在導線架的背面,將用於把來自上部配線的電性訊號傳導至背面的連接用柱5配置成例如平面視圖中呈陣列狀。
又,必須使墊4當中的數個墊電性連接至連接用柱5。因此,將分別與墊4當中的數個墊連接的配線圖案6從基板的外周向中心方向形成為例如放射狀(未圖示),以便與連接用柱連接。
接著,在利用背板(back sheet)覆蓋銅基板的第2面側而加以保護之後,使用氯化亞鐵溶液,由銅基材的第1面側進行第1次蝕刻處理,如第1D圖所示,使從第1面側之阻劑圖案露出的銅基板部位的厚度減薄至30μm為止。氯化亞鐵溶液的比重定為1.38,液溫定為50℃。在第1次蝕刻之際,不會對已形成有用以形成連接用柱5之第1阻劑圖案3的部位之銅基板1進行蝕刻處理。因此,能形成貫穿銅基材1內外而存在之連接用柱5。
又,在第1次蝕刻中,不會以蝕刻處理完全溶解除去進行蝕刻處理部位的銅基板1,而是以在成為了既定厚度之銅基板1的階段便結束蝕刻處理的方式來進行至中途為止的蝕刻處理。
接著,如第1E圖所示,關於第1面,利用20%氫氧化鈉水溶液進行阻劑圖案3的剝離,剝離液的溫度定為100℃。
接著,如第1F圖所示,使用膜狀的熱可塑性樹脂(新日鐵化學製,NEX-130C),以加壓加工形成預成型用樹脂層11。針對膜厚,係以使樹脂填充至比連接用柱的底面高出20μm的位置的方式調整,定為130μm。
在上述加壓加工之際,使用真空加壓式積層裝置。利用加壓部的溫度為100℃,真空室內的真空度為0.2torr,加壓時間為30秒來進行膜狀的熱可塑性樹脂的加壓加工。
如此,作為預成型用樹脂,就簡便地加工方面來看使用膜狀者是有效的。
又,進行在真空室內的加壓加工,有解消產生在樹脂內的空隙的效果,能抑制樹脂內空洞(void)的發生。
然後,在將膜狀樹脂加壓加工後,進行後烘烤,以180℃加熱60分鐘。
在預成型用樹脂的後烘烤之後,如第1G圖所示,將覆蓋第1面的樹脂研磨除去至連接用柱的底面露出為止。作為裝置,使用拋光輥旋轉式研磨裝置(buff roll rotary polishing device),拋光輥的號數是使用相當於800號。
接著,如第1H圖所示,進行第1面的半蝕刻。使用硫酸及過氧化氫的混合液作為半蝕刻液,蝕刻量係以使連接用墊的高度成為只比加工前低10μm方式來計算。
接著,以背板覆蓋第1面來保護,除去第2面的背板後,進行第2面的蝕刻。使用氯化亞鐵溶液作為蝕刻液,液的比重定為1.32,液溫定為50℃。蝕刻的目的是將配線圖案形成在第2面,將從第2面上的第2阻劑圖案7露出的銅溶解除去。
之後,將第1面的背板除去,接著,如第1I圖所示,進行第2面之第2阻劑圖案7的剝離,製得本發明的BGA。
接著,對所露出的第1面的金屬面,實施由無電解鍍鎳/鈀/金形成法所產生之表面處理,形成鍍覆層12。
對導線架形成鍍覆層12可適用電解鍍覆法。但是,要利用電解鍍覆法,便必須形成用於供給鍍覆電流的鍍覆電極,形成鍍覆電極的部分會使配線區域變窄,使配線的迴繞變得困難。因此,在本實施例,採用不須供給用電極的無電解鍍鎳/鈀/金形成法。
即,藉由酸性脫脂、軟蝕刻、酸洗淨、鈀觸媒活性處理、預浸漬(pre-dip)、無電解鍍白金、無電解鍍金來將鍍覆層12形成在金屬面。鍍覆厚度是:鎳定為3μm、鈀定為0.2μm、金定為0.03μm。使用的鍍覆液是:鎳為Emplate-NI(Meltex公司製)、鈀為Paurobon-EP(羅門哈斯公司製)、金為Paurobon-IG(羅門哈斯公司製)。
接著,在以固定用接著劑或固定用帶13將半導體元件10接著、搭載在導線架上之後,使用金細線8將半導體元件10的電性連接用端子、及位於配線圖案6之既定部位之配線接合用墊4進行配線接合。之後,以披覆導線架及半導體元件10的方式進行成型(molding)。接著,對已排版的半導體基板進行裁切,製得各個半導體基板。
最後地,如第1K圖所示,在各個半導體基板的端子部塗布熔接劑(flux)後,搭載焊球16,進行迴焊(reflow)處理,藉以形成焊料凸塊,製得所須的半導體裝置。
本實施例的半導體元件用基板的製造方法及半導體裝置,係能在製造附有預成型的半導體元件用基板之際,將連接用墊底面的高度加工成比周圍的預成型用樹脂還低。藉此,連接用墊周邊的樹脂發揮牆壁的功能,當搭載焊球時球不會自墊脫落。結果,能高良率地搭載焊球。
以上,雖然就本發明之適當的實施例加以說明並舉例証明,但該等實施例只是發明的例示而已不應被視為用於限定本發明,可在不脫離本發明範圍的範圍內進行各種追加、削除、置換及其他變更。即,本發明不受限於前述實施例,而是依申請專利範圍來限定。
根據本發明的話,便能在製造附有預成型的半導體元件用基板之際,將連接用墊底面的高度加工成比周圍的預成型用樹脂還低。藉此,連接用墊周邊的預成型用樹脂發揮牆壁的功能,當搭載焊球時球不會自墊脫落,能高良率地搭載焊球。
1...銅基板
2...感光性阻劑
3...第1阻劑圖案
4...配線接合用墊
5...連接用柱
6...配線圖案
7...第2阻劑圖案
8...金細線
10...半導體元件
11...預成型樹脂層
12...鍍覆層
13...固定用接著劑或固定用帶
16...焊球
21...導線架的平坦部分
22...半導體元件
23...導線
24...金屬配線
25...預成型用樹脂
26...導出電極
27...保持材
28...固定用樹脂或固定用帶
29...導線架的背面
第1A圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1B圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1C圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1D圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1E圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1F圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1G圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1H圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1I圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1J圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第1K圖係示意地顯示本發明之導線架狀的半導體元件用基板之製造製程的說明圖。
第2A圖係示意地顯示習知基板之構造的說明圖。
第2B圖係示意地顯示習知基板之構造的說明圖。
第2C圖係示意地顯示習知基板之構造的說明圖。
4...配線接合用墊
8...金細線
10...半導體元件
11...預成型樹脂層
12...鍍覆層
13...固定用接著劑或固定用帶
16...焊球
Claims (9)
- 一種半導體元件用基板之製造方法,其包含:將第1感光性樹脂層設置在金屬板的第1面;將第2感光性樹脂層設置在該金屬板之與該第1面不同的第2面;藉由根據第1圖案對該第1感光性樹脂層進行選擇性曝光顯影,來將由已顯影之該第1感光性樹脂層所構成且用以形成連接用柱的第1蝕刻用遮罩形成在該金屬板之該第1面;藉由根據第2圖案對該第2感光性樹脂層進行選擇性曝光顯影,來將由已顯影之該第2感光性樹脂層所構成且用以形成配線圖案的第2蝕刻用遮罩形成在該金屬板之該第2面;在形成該第1蝕刻用遮罩及該第2蝕刻用遮罩之後,藉由進行自該第1面至該金屬板中途的蝕刻來形成該連接用柱;在埋設自該第1面突出的該連接用柱的狀態下填充預成型用樹脂;將該第1面之該連接用柱加工以使其高度比周圍的該預成型用樹脂還低;及進行該第2面的蝕刻而形成該配線圖案。
- 如申請專利範圍第1項之半導體元件用基板之製造方法,其中在埋設自該第1面突出的該連接用柱的狀態下填充該預成型用樹脂,係包含:藉由該預成型用樹脂來使整個該第1面埋沒;及在埋沒之後,以讓該連接用柱的底面露出的方式在厚度方向上將該預成型用樹脂均勻地除去。
- 如申請專利範圍第1或2項之半導體元件用基板之製造方法,其中將該第1面之該連接用柱加工以使其高度比周圍的該預成型樹脂還低,係藉由半蝕刻(half-etching)來進行。
- 一種半導體元件用基板,其係藉由如申請專利範圍第1項之半導體元件用基板之製造方法來製造。
- 一種半導體基板,係將半導體元件安裝在如申請專利範圍第4項之半導體元件用基板,該半導體元件用基板與該半導體元件之間係藉由配線接合(wire bonding)來電性連接。
- 一種半導體元件用基板,其係藉由如申請專利範圍第2項之半導體元件用基板之製造方法來製造。
- 一種半導體基板,係將半導體元件安裝在如申請專利範圍第6項之半導體元件用基板,該半導體元件用基板與該半導體元件之間係藉由配線接合來電性連接。
- 一種半導體元件用基板,其係藉由如申請專利範圍第3項之半導體元件用基板之製造方法來製造。
- 一種半導體基板,係將半導體元件安裝在如申請專利範圍第8項之半導體元件用基板,該半導體元件用基板與該半導體元件之間係藉由配線接合來電性連接。
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KR (1) | KR101609016B1 (zh) |
CN (1) | CN102365736A (zh) |
SG (1) | SG175042A1 (zh) |
TW (1) | TWI404188B (zh) |
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JP2012244063A (ja) * | 2011-05-23 | 2012-12-10 | Richtek Technology Corp | 集積回路チップパッケージおよびその製作方法 |
ES2660212T3 (es) * | 2011-06-06 | 2018-03-21 | Toppan Printing Co., Ltd. | Laminado con patrón de hoja metálica y un módulo solar |
TWI455269B (zh) * | 2011-07-20 | 2014-10-01 | Chipmos Technologies Inc | 晶片封裝結構及其製作方法 |
JP5966275B2 (ja) * | 2011-08-10 | 2016-08-10 | 三菱マテリアル株式会社 | パワーモジュール用基板の製造方法 |
JP2016009746A (ja) * | 2014-06-24 | 2016-01-18 | 凸版印刷株式会社 | 樹脂付リードフレーム基板及びその製造方法 |
CN105280597A (zh) * | 2014-07-23 | 2016-01-27 | 华天科技(西安)有限公司 | 一种采用研磨工艺减小引线宽度的封装件及其制作工艺 |
DE102014111930A1 (de) * | 2014-08-20 | 2016-02-25 | Rupprecht Gabriel | Thermisch gut leitendes, elektrisch isolierendes Gehäuse mit elektronischen Bauelementen und Herstellverfahren |
CN104269359A (zh) * | 2014-09-05 | 2015-01-07 | 江苏长电科技股份有限公司 | 一种新型四面无引脚封装工艺方法 |
CN105720036A (zh) * | 2014-12-03 | 2016-06-29 | 恒劲科技股份有限公司 | 封装结构及其制法 |
JP6537144B2 (ja) * | 2016-03-16 | 2019-07-03 | 大口マテリアル株式会社 | 多列型リードフレーム及びその製造方法 |
KR20200087137A (ko) * | 2017-11-16 | 2020-07-20 | 미츠비시 가스 가가쿠 가부시키가이샤 | 패터닝된 금속박 부착 적층체의 제조 방법 및 패터닝된 금속박 부착 적층체 |
US11244881B2 (en) * | 2019-09-30 | 2022-02-08 | Texas Instruments Incorporated | Package terminal cavities |
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- 2010-03-17 CN CN2010800142271A patent/CN102365736A/zh active Pending
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- 2010-03-17 WO PCT/JP2010/001897 patent/WO2010116622A1/ja active Application Filing
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JP2010238693A (ja) | 2010-10-21 |
US8466547B2 (en) | 2013-06-18 |
TW201044533A (en) | 2010-12-16 |
SG175042A1 (en) | 2011-11-28 |
KR101609016B1 (ko) | 2016-04-04 |
US20120018860A1 (en) | 2012-01-26 |
CN102365736A (zh) | 2012-02-29 |
KR20120005446A (ko) | 2012-01-16 |
WO2010116622A1 (ja) | 2010-10-14 |
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