TWI393254B - 具有降低米勒電容之金屬氧化物半導體（ｍｏｓ）閘控的電晶體 - Google Patents

具有降低米勒電容之金屬氧化物半導體（ｍｏｓ）閘控的電晶體 Download PDF

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TWI393254B
TWI393254B TW094135172A TW94135172A TWI393254B TW I393254 B TWI393254 B TW I393254B TW 094135172 A TW094135172 A TW 094135172A TW 94135172 A TW94135172 A TW 94135172A TW I393254 B TWI393254 B TW I393254B
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trench
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Praveen Muraleedharan Shenoy
Christopher Boguslaw Kocon
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Fairchild Semiconductor
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Description

具有降低米勒電容之金屬氧化物半導體(MOS)閘控的電晶體 發明領域
本發明一般關於半導體電力元件，且特別關於具有降低米勒電容之一種溝槽型MOS(金屬氧化物半導體)閘控電晶體。
 發明背景
第1圖顯示一傳統的垂直溝槽閘型(trenched－gate)MOSFET 100之一簡化剖面圖。n－型傳導性類型的一磊晶層(epitaxial layer)104在形成汲極接觸區的n－型基底102上延伸。p－型傳導性類型的阱區(well region)106形成於磊晶層104的一上部裏。閘溝槽(gate trench)109延伸穿過阱區106且正好終止於磊晶層104和阱區106間的交界面下。閘溝槽109順著其側壁和底部與一介電層(dielectric layer)112排成一行，且被填充形成電晶體閘的多晶矽材料110。源區(source region)108位於溝槽109的各側，且沿垂直方向交疊閘(gate)110。在導通態(on－state)，電流從汲極接點(drain terminal)114垂直流動，經過基底102、磊晶層104、阱區106裏沿溝槽109外壁的通道區、以及最後的源區108，流向源極接點(source terminal)116。
磊晶層104和基底102一起形成汲極區。可從圖中看出，閘110沿溝槽109底部交疊汲極區。需要最小化閘極－汲極交疊，以提升電晶體切換速度。閘極－汲極電荷Qg d 與交疊面積成正比，而與沿溝槽109底部的介電層厚度成反比例。幾種減少Qg d 的方法已被提出，包括減少溝槽寬度、沿溝槽底部使用較厚介電質、消除沿溝槽平底的閘極部分、以及將p－型阱區延長至略微深於溝槽處等。以上每種技術均有其各自的優點和缺點。一些需要一種更複雜的製程技術，而其餘的在減少Qg d 且不負面影響其餘元件特徵方面，並不太有效。
因此，一種具有改良特徵的MOS－閘控電晶體，其包括一實質降低的米勒電容(miller capacitance)且製造簡單，是令人期待的。
 發明概要
依據本發明一實施例，一溝槽型MOS－閘控電晶體包括形成一第一傳導性類型的一第一區，其與一第二傳導性類型的一阱區形成一pn接面。該阱區具有一平底部分和比該平底部分更深度延伸之一部分。一閘溝槽延伸進該阱區。通道區沿該閘溝槽的外壁延伸進該阱區內。該閘溝槽具有終止於該第一區內的第一底部和終止於該阱區更深部分內的第二部分，使得在該電晶體處於導通態時，該阱區的該更深部分阻止電流流過直接定位於該阱區的該更深部分上之該等通道區。
依據本發明之再一實施例，一溝槽型MOS－閘控電晶體包括位於一矽基底上的一第一傳導性類型之一矽層。一第二傳導性類型的一阱區形成於該矽層的一上部內。一閘溝槽延伸穿過該阱區且終止於該矽層內。該第一傳導性類型的源區位於該閘溝槽的各側面。該閘溝槽被填充一多晶矽材料，至少直到且部分交疊該源區。該第二傳導性類型的一矽區沿該溝槽的一底部延伸，使得一間隙形成於該矽區和該阱區之間，當該電晶體處於一導通態時，電流流過其間隙。
依據本發明又一實施例，一溝槽型MOS－閘控電晶體如下形成。提供一第一傳導性類型之一第一區。接著一第二傳導性類型的一阱區形成於該第一區的一上部裏。一溝槽形成，其延伸穿過該阱區且終止於該第一區裏。該第二傳導性類型的摻質沿該溝槽底部的預定部分而被植入，以形成沿該溝槽底部且鄰近該阱區之區，使得在該電晶體處於導通態時，該阱區的較深部分阻止電流流過直接定位於該阱區該較深部分上之該等通道區間部分。
依據本發明之另一實施例，一溝槽型MOS－閘控電晶體如下形成。一第一傳導性類型的一磊晶層形成於一基底上。一第二傳導性類型的一阱區形成於該磊晶層的一上部內。一溝槽形成，其延伸穿過該阱區且終止於該磊晶層裏。該第二傳導性類型的摻質沿該溝槽的底部被植入，以形成沿該溝槽底部延伸之該第二傳導性類型的一區，以使一間隙形成於該第二傳導性類型的該區和該阱區之間，在該電晶體處於導通態時，一電流流過其間隙。
參看隨附附圖和後述揭示內容，將對本發明的該等和其餘實施例進行陳述。
圖式簡單說明
第1圖顯示一傳統垂直溝槽式閘型(trenched gate)MOSFET之一簡化剖面圖；第2A圖顯示依據本發明的一垂直溝槽式(trenched－gate)閘型MOSFET之一簡化剖面圖；第2B圖顯示第2A圖的垂直溝槽式閘型MOSFET之一簡化頂部佈局圖；第3圖顯示依據本發明另一實施例的一垂直溝槽式閘型MOSFET之一簡化剖面圖；第4圖顯示本發明另一實施例之一簡化頂部佈局圖，其中第2A圖和第3圖裏的原胞結構被結合；第5圖顯示第2A圖的MOSFET實施例之電流和電壓波形與習知技藝第1圖的MOSFET之電流和電壓波形的比較；第6圖顯示第3圖的MOSFET之電流和電壓波形與習知技藝第1圖的MOSFET之電流和電壓波形的比較。
 較佳實施例之詳細說明
依據本發明的一實施例，藉使用位於溝槽式閘下面的一植入區，MOSFET的閘極－汲極電容被降低，其中該植入區鄰近MOSFET的阱區。植入區成為溝槽範圍，在其下植入區被形成非活性的，因為它阻礙電晶體通道對應部分裏的傳導。該實施例的一合適用途為高電壓元件，其中通道電阻(channel resistance)在導通電阻(resistance Rdson)方面對電晶體的貢獻較低。在另一實施例中，位於閘溝槽下的一植入區被形成，使得一間隙存在於植入區和阱區之間，通道電流可流過其中。在該實施例中，植入區在導通電阻方面的影響被最小化，因此該實施例的一合適用途將會為低電壓元件。該等兩個實施例在要求一緊密溝槽原胞(cell)節距(pitch)的設計中，例如一超接面(superjunction)元件或低導通電阻的緊密交替pn柱(pn pillar)節距，尤其有用。該等兩個實施例可在一單獨的MOSFET中被結合到一起。另外，當需要時，該等兩個實施例之一者可和第1圖所示的習知技藝結構相結合。
第2A圖顯示依據本發明一實施例的一垂直溝槽閘型MOSFET 200之一簡化剖面圖。n－型傳導性類型的一磊晶層204延伸越過形成汲極接觸區的n－型基底202。p－型傳導性類型的阱區206形成於磊晶層204的一上部裏。閘溝槽209延伸穿過阱區206。直接位於溝槽209下之阱區206的一部分206a比阱區206的其餘部分更深度延伸進磊晶層204，以使閘溝槽209終止於部分206a內。閘溝槽209沿著其側壁和底面與一介電層212排成一行。溝槽209被填充形成電晶體閘的多晶矽材料210。源區208位於溝槽209的各側面，且沿垂直方向交疊閘210。在另一實施例中，溝槽209被部分填充多晶矽材料，且介電質材料位於多晶矽頂上。注意一個或更多個基底202、磊晶層204、包括部分206a的阱區206、以及源區208可由晶體矽(Si)、碳化矽(SiC)、氮化鎵(GaN)、或鍺化矽(SiGe)形成。
在第2A圖中，因為閘210不交疊磊晶層204，所以在導通態時沒有通道形成於部分206a上。在第2A圖實施例的一變型中，溝槽式閘原胞為第2B圖裏簡化頂部佈局圖所示之帶狀(即，被佈置成一開放原胞組態)。帶狀溝槽式閘210垂直延伸，且源區208位於溝槽式閘型電極210的各側。如圖示，較深延伸阱部分206a沿帶狀溝槽式閘電極210的長度而週期性形成。在部分206a沒有形成之處(例如，沿虛線1－1)，原胞剖面相似於第1圖的(即，閘溝槽210暢通地延伸穿過阱區206且終止於磊晶層204內，使得閘溝槽沿垂直方向交疊磊晶層204)。透過這種方式，在導通態裏，電流流動被確立(以相似於以上參看第1圖所述之一方式)沿著溝槽側壁部分，在其下較深的延伸阱部分206a並沒有形成。但是，在更深度延伸阱部分206a於閘下形成之處，電流流動被阻礙。因此，閘極－汲極交疊被對應部分206a的一總量所減少。進言之，既然總阱區206在尺寸上被增加，則閘極到源極的電容或Qg s (閘源電荷)增加。因此，Qg d /Qg s (閘汲電荷/閘源電荷)之比被進一步有利增加。故該MOSFET的切換特徵被實質改良。
在一實施例中，第2A圖的結構被如下形成。採用傳統技術將磊晶層204形成於基底202上。採用習知技術藉植入和驅動p－型摻質(dopants)的方式，阱區206形成於磊晶層204的一上部裏。接著採用傳統矽蝕刻技術藉蝕刻矽而使溝槽209形成。採用一罩層(masking layer)，然後用p－型摻質選擇性植入溝槽209的底部從而形成區206a。在一實施例中，使用1×101 3 －1×101 4 cm－ 3 範圍內的一植入劑量和40－120KeV範圍內一植入能量。在另一實施例中，區206a在其最深點處的厚度處於0.2－0.4μm範圍內。介電層212、填充溝槽209的摻入多晶矽210、以及源區208都是採用傳統方法而形成。
第3圖顯示依據本發明另一實施例的一垂直溝槽式閘型MOSFET 300之一簡化剖面圖。除了替換更深度延伸阱部分206a，p－型區307直接形成於溝槽309下之外，MOSFET 300的剖面圖相似於第2A圖的。如第3圖所示，區307形成使得一間隙存在於阱區306和區307之間，位於溝槽309各底部拐角處。在導通態期間，電流流過這些間隙。因此，藉使用如圖示之具有間隙的區間307，閘極－汲極交疊被顯著減少且沒有阻礙電流流動。在一實施例中，藉由採用30－80KeV範圍內的一植入能量來實施一淺的硼植入穿過溝槽的底部而形成區307。在一實施例中，區307具有0.1－0.3μm範圍內的一厚度，且區307和阱區306之間的間隙處於0.1－0.3μm範圍內。如第2A圖實施例所示，一個或更多個基底302、磊晶層304、阱區306、區307、以及源區308可由晶體矽(Si)、碳化矽(SiC)、氮化鎵(GaN)、或鍺化矽(SiGe)形成。
在一帶狀原胞佈局實施例中，區307可連續沿著帶狀溝槽閘的長度而延伸。區307可沿帶狀溝槽閘而向上延伸到其端部或其餘位置，以電接觸阱區306。作為選擇，區307不進行偏壓，且因此被容許電漂浮(electrically float)。在另一實施例中，相似於第2B圖所示佈局，多個區307沿帶的長度而被週期性形成，使得沿帶的部分之原胞結構(例如，在虛線1－1處)相似於習知技藝第1圖中所示之。作為選擇，第2A圖和第3圖實施例可被結合為第4圖佈局圖所示之。在第4圖裏，區206a對應第2A圖裏的區206a，而區307對應第3圖裏的區307。如兩個箭頭所示，無電流傳導產生於區206a形成處，但是電流可流過區307形成處以及區206a和307之間。區307和206a的特別佈置並不受限於第4圖所示之。許多其他佈置也是可能。在另一實施例中，區206a和307之間的區被消除，使得沿帶之任何地方都不是相似於習知技藝第1圖裏所形成之所示原胞結構。
在本發明之一實施例中，第2A圖裏位於閘溝槽下之阱區206和區206a，以及第3圖裏位於閘溝槽下之阱區306和區307可如下形成。p－型摻質的一淺覆層植入(在活性區裏)磊晶層之步驟被實施。接著採用一罩層，使p－型摻質的一深度植入磊晶層選定區之步驟被實施。該等兩個植入步驟可按相反順序被實施。然後一溫度循環被實施以驅動該等兩種植入摻質更深入磊晶層。結果，對應淺覆層植入的一阱區和對應深度植入的預定矽區形成於磊晶層裏，使得預定矽區的最深部分深於阱區的底面。為獲得第2A圖裏的結構，上述兩個植入步驟和溫度循環需要被設計，以使驅動進摻質後，矽區鄰近阱區。作為選擇，為形成第3圖裏的結構，上述兩個植入步驟和溫度循環需要被設計，以使摻質被驅動進和閘溝槽被形成之後，一間隙形成於各矽區和阱區之間。鑒於該揭示內容，本技藝熟練人員將會瞭解怎樣設計該等兩個步驟和溫度循環，從而獲得第2A圖和3所示之結構。
在形成第2A圖裏位於閘溝槽下的阱區206和區206a，以及第3圖裏位於閘溝槽下的阱區306和區307之另一方法中，採用一罩層使p－型摻質的一淺植入磊晶層所選定區之步驟被首先實施。然後一溫度循環被進行以驅動植入摻質更深入磊晶層。接著，p－型摻質的一覆層植入(blanket implant)(在活性區裏)第一矽區被實施。一第二溫度循環再被實施以驅動植入摻質從覆層植入步驟更深入磊晶層內和驅動摻質從淺植入步驟甚至更加深入磊晶層內。結果，對應覆層植入的一阱區和對應淺植入的矽區被形成，使得矽區的最深部分深於阱區的底面。為獲得第2A圖裏的結構，上述兩個植入步驟和兩個溫度循環需要被設計，以使驅動進摻質後，矽區鄰近阱區。作為選擇，為形成第3圖裏的結構，該等兩個植入步驟和兩個溫度循環需要被設計，以使摻質被驅動進和閘溝槽被形成之後，一間隙形成於各矽區和阱區之間。和前述實施例一樣，鑒於該揭示內容，本技藝熟練人員將會瞭解怎樣設計該等兩個步驟和兩個溫度循環，從而獲得第2A圖和3所示之結構。
下列表格顯示習知技藝第1圖裏的MOSFET 100、第2A圖裏的MOSFET 200、和第3圖裏的MOSFET 300之各個Qg s 、Qg d 、和Qg d /Qg s 之比的模擬結果。貝有一6μm節距和0.6μm溝槽寬度之一600V超接面MOSFET被用於該模擬。
可以看出，MOSFET 200和300兩個均有低於習知技藝MOSFET 100的Qg d ，且兩個均有高於習知技藝MOSFET 100的Qg s 。因此比MOSFET 100的較低一Qg d /Qg s 之比也為MOSFET 200和300所獲的。第5圖和第6圖裏的模擬波形也顯示相似結果。第5圖顯示第2A圖MOSFET和習知技藝第1圖MOSFET的I汲 (汲極電流)、V汲 (汲極電壓)、以及V閘 (閘極電壓)，而第6圖顯示第3圖MOSFET和習知技藝第1圖MOSFET的相同參數。
不同實施例的剖面圖和頂部佈局圖或許沒按比例繪出，且同樣也無意限制對應結構佈局設計裏的可能變型。多種電晶體也可形成於包括六角形或正方形成型電晶體原胞在內之細胞架構(cellular architecture)裏。
雖然以上顯示和陳述多個具體實施例，但是本發明並不受限於此。舉例而言，可理解地是，在不脫離本發明範圍下，所示和所述結構的摻雜極性可被顛倒，及/或多種元素的摻雜濃度可被改變。同樣舉另一示例，以上所述之多種例示性垂直電晶體具有終止於漂流區內之溝槽，但是它們也可終止於更深的摻入基底內。同樣另舉一示例，本發明被顯示和陳述於垂直MOSFET實施例的內容中，但是第2A圖裏的區206a和第3圖裏的區307可被相似形成於其他溝槽式閘型結構裏，例如溝槽式閘型IGBT(絕緣閘雙極電晶體)和側向溝槽式閘型MOSFET。
因此，本發明範圍不應該參看上述描述而被決定，相反，而是應該參看所呈申請專利範圍及其等全部等效範圍而決定。
100．．．MOSFET(金屬氧化物半導體場效應管)
102．．．基底
104．．．磊晶層
106．．．阱區
108．．．源區
109．．．閘溝槽
110．．．多晶矽材料/閘極
112．．．介電層
114．．．汲極接點
116．．．源極接點
118．．．閘極接點
200．．．溝槽閘型MOSFET
202．．．基底
204．．．磊晶層
206．．．阱區
206a．．．部分/區
208．．．源區
209．．．閘溝槽
210．．．多晶矽材料/閘極
212．．．介電層
214．．．汲極接點
216．．．源極接點
218．．．閘極接點
300．．．MOSFET
302．．．基底
304．．．磊晶層
306．．．阱區
307．．．P－型區
308．．．源區
309．．．溝槽
310．．．多晶矽材料/閘極
312．．．介電層
314．．．汲極接點
316．．．源極接點
318．．．閘極接點
第1圖顯示一傳統垂直溝槽式閘型(trenched gate)MOSFET之一簡化剖面圖；第2A圖顯示依據本發明的一垂直溝槽式(trenched－gate)閘型MOSFET之一簡化剖面圖；第2B圖顯示第2A圖的垂直溝槽式閘型MOSFET之一簡化頂部佈局圖；第3圖顯示依據本發明另一實施例的一垂直溝槽式閘型MOSFET之一簡化剖面圖；第4圖顯示本發明另一實施例之一簡化頂部佈局圖，其中第2A圖和第3圖裏的原胞結構被結合；第5圖顯示第2A圖的MOSFET實施例之電流和電壓波形與習知技藝第1圖的MOSFET之電流和電壓波形的比較；第6圖顯示第3圖的MOSFET之電流和電壓波形與習知技藝第1圖的MOSFET之電流和電壓波形的比較。
202．．．基底
204．．．磊晶層
206．．．阱區
206a．．．部分
208．．．源區
209．．．閘溝槽
210．．．多晶矽材料/閘極
212．．．介電層
214．．．汲極接點
216．．．源極接點
218．．．閘極接點

Claims (16)

  1. 一種溝槽型MOS-閘控電晶體，其包含：一第一傳導性類型的一第一區；和該第一區形成一pn接面之一第二傳導性類型的一阱區，該阱區具有一平底部分和比該平底部分更深度延伸的一部分；延伸進該阱區的一閘溝槽；沿該閘溝槽的外壁之該阱區裏的通道區；該第一區裏的該第二傳導類型的一第二區；該閘溝槽的一第一底部係終止於該第二區內，該第二區係與該阱區的該平底部分隔開以於其間形成一間隙，使得在該電晶體處於一導通態時，一電流流過該間隙；該閘溝槽的一第二底部係終止於該阱區的該更深部分內，使得在該電晶體處於一導通態時，該阱區的該更深部分阻止一電流流過直接定位於該阱區的該更深部分上之該等通道區部分；以及該閘溝槽的一第三底部係終止於該第一區內。
  2. 如申請專利範圍第1項之溝槽型MOS-閘控電晶體，其進一步包含：該第一傳導性類型的一基底，該第一區係為在該基底上延伸之一磊晶層。
  3. 如申請專利範圍第1項之溝槽型MOS-閘控電晶體，其進一步包含： 位於該阱區裏之該第一傳導性類型的一源區，該源區位於該閘溝槽的一側面。
  4. 如申請專利範圍第1項之溝槽型MOS-閘控電晶體，其中該閘溝槽包括與該閘溝槽的一側壁和一底部排成一行之一介電層，且該閘溝槽係至少被部分地填充多晶矽。
  5. 如申請專利範圍第1項之溝槽型MOS-閘控電晶體，其中該阱區的該更深部分比該阱區的該平底部分約深0.2-0.4μm。
  6. 如申請專利範圍第1項之溝槽型MOS-閘控電晶體，其中該第一區和該阱區中之至少一者是由晶體矽(Si)、碳化矽(SiC)、氮化鎵(GaN)、及鍺化矽(SiGe)中之至少一者所形成。
  7. 一種溝槽型MOS-閘控電晶體，其包含：一基底；延伸橫越並接觸該基底之一第一傳導性類型的一磊晶層；形成於該磊晶層之一上部內之一第二傳導性類型的一阱區；延伸進該阱區裏的一閘溝槽，該閘溝槽具有一第一底部及一第二底部，該第一底部係終止於該磊晶層內；以及包圍該閘溝槽之該第二底部之該第二傳導性類型的一矽材料區，使得一間隙形成於該矽材料區與該阱區之間，在該電晶體處於一導通態時，一電流可流過該間 隙。
  8. 如申請專利範圍第7項之溝槽型MOS-閘控電晶體，其中該矽材料區具有約為約為0.1-0.3μm之一厚度。
  9. 如申請專利範圍第7項之溝槽型MOS-閘控電晶體，其中該閘溝槽包括與該閘溝槽的一側壁和一底部排成一行之一介電層，且該閘溝槽係至少被部分地填充多晶矽。
  10. 如申請專利範圍第7項之溝槽型MOS-閘控電晶體，其中該基底、該磊晶層及該阱區中之至少一者是由晶體矽(Si)、碳化矽(SiC)、氮化鎵(GaN)、及鍺化矽(SiGe)中之至少一者所形成。
  11. 一種溝槽型MOS-閘控電晶體，其包含：一矽材料基底；位於該基底上之一第一傳導性類型的一矽材料層；形成於該矽材料層之一上部內之一第二傳導性類型的一阱區；延伸進該阱區裏的一閘溝槽，該閘溝槽具有一第一底部及一第二底部，該第二底部係終止於該矽材料層內；該第一傳導性類型的一源區，其位於該閘溝槽之各側面，從而在該阱區內沿該閘溝槽外壁形成通道區，該閘溝槽係被填充一多晶矽材料至少直到且部分交疊該源區；以及該第二傳導性類型的一矽材料區，其包圍該閘溝槽的該第一底部，使得一間隙形成於該矽材料區和該阱區 之間，在該電晶體處於一導通態時，一電流流過其間隙。
  12. 如申請專利範圍第11項之溝槽型MOS-閘控電晶體，其中該矽材料層係為延伸於該基底上之一磊晶層。
  13. 如申請專利範圍第11項之溝槽型MOS-閘控電晶體，其中該矽材料區具有約為0.1-0.3μm的一厚度。
  14. 如申請專利範圍第11項之溝槽型MOS-閘控電晶體，其中該閘溝槽閘係為帶狀，且該矽材料區係沿該閘溝槽的一長度而部分地延伸。
  15. 如申請專利範圍第11項之溝槽型MOS-閘控電晶體，其中該阱區具有一平底部分和比該平底部分更深度延伸之一部分，使得該閘溝槽部分終止於該阱區的該更深部分內。
  16. 一種溝槽型MOS-閘控電晶體，其包含：一矽材料基底；位在該基底上的一第一傳導性類型的一矽材料層；形成該矽材料層內的一pn接面的一第二傳導性類型的一阱區；延伸進該阱區裏之一閘溝槽；位於該閘溝槽之各側面之該第一傳導性類型的一源區，以沿該閘溝槽之外壁之該阱區內形成通道區，該閘溝槽包括一至少至該源區且部份地與該源區交疊之閘電極；以及該第二傳導性類型的一矽材料區，其包圍該閘溝槽 之一底部，使得一間隙形成於該矽材料區與該阱區之間，在該電晶體處於一導通態時，一電流流過該間隙，該閘溝槽係為帶狀且該矽材料區係沿該帶狀閘溝槽之全部長度延伸，且該矽材料區係電氣連接於該阱區。
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US7265415B2 (en) 2007-09-04
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US20070264782A1 (en) 2007-11-15
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US20060076617A1 (en) 2006-04-13
US7534683B2 (en) 2009-05-19
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