TWI374498B - Post treatment of low k dielectric films - Google Patents

Post treatment of low k dielectric films Download PDF

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TWI374498B
TWI374498B TW094103444A TW94103444A TWI374498B TW I374498 B TWI374498 B TW I374498B TW 094103444 A TW094103444 A TW 094103444A TW 94103444 A TW94103444 A TW 94103444A TW I374498 B TWI374498 B TW I374498B
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dielectric constant
low dielectric
constant film
post
film
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TW200536018A (en
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Zhenjiang Cui
Josephine J Chang
Alexander T Demos
Reza Arghavani
Derek R Witty
Helen R Armer
Girish A Dixit
Saad Hichem M
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Applied Materials Inc
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
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Description

1374498 I · * 玖、發明說明: 【發明所屬之技術領域】 本發明之該等實施例係關於積體電路之製造。更明確 而言，本發明該等實施例係與用於沉積及後處理低介電常 數薄膜有關。 【先前技術】
從數十年前半導體元件首次提出以來，半導體元件幾 何結構在尺寸上已顯著地降低。從當時起，積體電路大致 依循著兩年/尺寸減半的準則（常稱為莫爾定律），其表示每 過兩年晶月上的元件數目便會倍數增加。現今製造設備可 固定地生產具0.13必m甚至0 · 1 3必m特徵尺寸的元件，而未 來設備很快將可生產出幾何結構更為小的元件。
為進一步縮小積體電路上之元件尺寸，現已需要使用 低電阻之導電材料以及低介電常數（k)之絕緣體以降低鄰 近金屬線間的電容耦合。近來在低介電常數絕緣薄膜的發 展已將重心擺在將矽（Si)、碳（C)及氧（0)原子混入薄膜中。 此領域的一大挑戰係發展出含S i、C及Ο原子之薄膜，使 之具低k值並展現所欲之熱及機械特性。通常含Si、C及 Ο原子且具有所欲介電常數之薄膜之機械強度較差，且於 隨後製程期間易受蝕刻化學物及電漿暴露而受損，使積體 電路裂化。 熱及電漿退火製程已發展可改善低介電常數薄膜之特 性。熱及電漿退火製程通常係實施在約低於 400 °C之溫 3
1374498 I · > · 度，以避免損傷基材或元件上沉積有低介電常 他部件。現已發現熱及電漿退火製程可密化 Si、C及0原子之低介電常數薄膜。然而，前 通常係實施約3 0分鐘至2小時，且因此會明顯 程時間。同樣的，業界仍持續期待可改善低介 之機械及介電特性。 因此，業界對於低介電常數薄膜之後處理 求，以期能改善低介電常數薄膜之特性。 【發明内容】 本發明之該等實施例係提出一種處理一基 其至少包含在RF電源下於一基材上沉積一包 低介電常數薄臈，並藉一製程後處理該經沉積 數薄膜，該製程包含以至少約1 0 °C /秒的速率 常數薄膜加熱到至少約 6 0 0 °C之所欲溫度，其 常數薄膜係維持在該所欲溫度約5秒或更少， 少約1 0 °C /秒的速率冷卻該低介電常數薄膜。 中，該低介電常數薄膜係在約〇. 5分至約5分 内進行加熱及冷卻。 於一實施例中，該低介電常數薄膜係由乡 2 5 0 °C間之溫度加熱至約 6 0 0 °C及約 1 〇 〇 〇 °C間 度，其中該低介電常數薄膜係於該所欲溫度下 或更少，並接著由該所欲溫度冷卻，其中該低 膜係在約0.5分至約5分之一時間段内進行加1 數薄膜之其 (densify)含 述退火製程 增加基材製 電常數薄膜 方法存有需 材之方法， 含矽及碳之 之低介電常 將該低介電 中該低介電 且接著以至 於一實施例 之一時間段 ]2 5 °C至約 之一所欲溫 加熱約5秒 介電常數薄 办及冷卻。 4 1374498 I . · 本發明之另一實施例包括藉由至少約 1 o °c /秒之速率 將該低介電常數薄膜加熱至一所欲溫度以後處理一低介電 常數薄膜，其中該低介電常數薄膜係維持在該所欲溫度約 5秒或更少，並以至少約1 0°C /秒之速率冷卻該低介電常數 薄膜，並以一或多種選自一電子束處理及UV輻射處理所 組成群組之製程中處理該低介電常數薄膜。 【實施方式】
本發明之一或多値實施例係提供一種方法，其包含沉 積低介電常數薄膜於一基材上及藉一至少包含快速加熱該 低介電常數薄膜至一所欲高溫（例如介約 600°c至約 1000 °C)之製程對該低介電常數薄膜進行後處理，並接著快速冷 卻該低介電常數薄膜使之暴露於該所欲高溫約 5秒或更 少。較佳而言，該低介電常數薄膜係暴露於該所欲高溫約 1秒或更少。於一實施態樣中，該快速加熱及快速冷卻該 低介電常數薄膜的製程係一 spike退火製程。 沉精低介電當數薄膜
該低介電常數薄膜之介電常數約小於4，且至少包含 矽及碳，較佳則包含氧。該低介電常數薄膜係於RF電源 下由一至少包含一或多種有機矽化物之混合物所沉積。該 一或多種用於沉積低介電層之有機矽化物可為有機矽烷 (organosilane)、有機石夕氧化物（organosiloxanes)或其結合 物。此處所用之名詞 「有機石夕化物（organosilicon ⑧ 1374498 I I 1 · compound)」意指為有機基團中含有破原子之化合物，且 其可為環狀或鏈狀。有機基團可包括炫基、稀基、環已稀、 以及除其功能性衍生物外之芳香族羥基。較佳而言，該有 機梦化物包括一或多個接於發原子之碳原子，以使破原子 不會在適當製程條件下的氧化而快速移除。該有機發化物 較佳也包括一或多個氧原子。
合適之環狀有機矽化物包括一具有三個（或以上）之碎 原子的環狀結構，及選擇性的包括一或多個氧原子。市面 上所販售之環狀有機矽化物包括數個矽及氧原子交替之 環，其中該矽原子與一或兩個烷基相鍵結。一些例示性的 環狀有機矽化物包括： 2,4,6-矽代環己烷 -(-SiH2CH2-)3- (環狀） 1，3,5,7-四曱基環四矽氧烷（TMCTS) -(-SiHCH3-0-)4- (環狀） 八曱基環四矽氧烷（OMCTS) -(-Si(CH3)2-0-)4- (環狀） 1,3,5,7,9-五T基環五矽氧烷 -(-SiHCH3-0-)5- (環狀） 1，3,5,7-梦代-2,6-氧代環辛烷 -(-SiH2CH2-SiH2-0-)2- (環狀） 六甲基環三矽氧烷 -(-Si(CH3)2_0-)3- (環狀）
合適之直鏈有機矽化物包括具有直鏈或分支結構（具 一或多個矽原子及一或多個碳原子）的脂肪族有機矽化 物。該有機矽化物更可包含一或多個氧原子。若干例示性 之直鏈有機矽化物包括： 1374498.
甲基矽烷 CH3-SiH3 二甲基矽烷 (CH3)2-SiH2 三甲基矽烷 (CH3)3-SiH 乙基矽烷 CH3-CH2-S1H3 二矽炫基曱烷 SiH3-CH2-SiH3 二(曱基矽烷基)甲烷 CH3-SiH2-CH2-SiH2-CH3 1，2-二梦烷基乙烷 SiH3-CH2-CH2-SiH3 1,2-雙(甲基梦烷基)乙烷 CH3-SiH2-CH2-CH2-SiH2-CH3 2,2-雙矽烷基丙烷 SiH3-C(CH3)2-SiH3 二乙基矽烷 ((C2H5)2SiH2) 丙基矽烷 (C3H7SiH3) 乙烯基甲基梦烷 (CH2=CH)-SiH2-CH3 1，1，2,2-四曱基二發烷 (CH3)2-SiH-SiH-(CH3)2 六甲基二矽烷 CH3)3Si-Si-(CH3)3 1，1，2,2,3,3-六曱基三砍燒 (CH3)2-SiH-Si(CH3)2-SiH-(CH3)2 U，2,3,3-五甲基三矽烷 (CH3)2-SiH-SiH(CH3)-SiH-(CH3)2 I，3·雙(曱基矽烷基)丙烷 CH3-SiH2-(CH2)3-SiH2-CH3 U-雙(二曱基矽烷基)乙烷 (CH3)2-SiH-CH2)2-SiH-CH3)2 1，3_雙(二曱基矽烷基)丙烷 (CH3)rSiH-(CH2)rSiH-CH3)2 二乙氧曱基矽烷基（DEMS) CH3-SiH-(0-CH2-CH3)2 i，3·二甲基二矽氧烷 CH3- S1H2-O- S1H2-CH3 1，1，3,3-四甲基二矽氧烷（TMDS0) (CH3)2-SiH-0-SiH-(CH3)2 六甲基二矽氧烷（HMDS) (CH3)3-Si-0-Si-(CH3)3 i，3_雙(石夕烷基曱樓)二石夕氳烷 (SiH3-CH2-SiH2-)2-0 ⑧ 1374498 雙(1-甲基二碎氧烷基)曱烷 (CH3- SiH2-0- SiH2-)2-CH2 2,2-雙(1-甲基二矽氧烷基)丙烷 (CHr SiH2-0- SiH2-)2-C(CH3)2 二曱基二甲氧基矽烷（DMDMOS) (CH3)2-Si-(OCH3)2 苯基二甲氧基硅烷 C6H5-SiH-(0-CH3)2 二苯基甲基矽烷 (C6H5)2-SiH-CH3 二曱基苯矽烷 (CH3)2-SiH-C6H5 二甲氧基甲基乙烯基矽烷 (CH30)2-Si(CH3)0CH3)2
於一實施例中，該低介電常數薄膜係於RF電源下由 一包含一或多種有機石夕化物及一或多種氧化氣體之混合物 中所沉積。可使用之氧化氣體包括氧氣（〇2)、臭氧（〇3)、 一氧化二氮（N20)、一氧化碳（C0)、二氧化碳（co2)、水 (112〇)、二甲基代乙二路（2,3-1>1^3116(11〇1^)或其結合物。當 使用臭氧作為氧化氣體時，臭氧產生器可將一氣體源中重 量6%至2 0%(—般約15%)之氧氣轉換為臭氧，而剩餘仍為 氧氣。然而，臭氧濃度可依據所欲臭氧的量、以及所用臭 氧產生設備的種類作增加或減少。氧氣或含氧化合物的解 離可在進入沉積室前於微波處理室内進行，以降低含矽化 合物的過量解離。較佳而言，可施加射頻（RF)電源至反應 區以增加解離量。 亦可選擇的是，除該一或多種有機矽化物及該選擇性 的一或多種氧化氣體外，混合物中也可包括一或多種碳氫 化合物以沉積低介電常數薄膜。可使用之碳氫化合物包括 具有介約1至20個鄰接碳原子之脂肪族碳氫化合物。該碳 8 1374498 •· · ·
氫化合物可包括數個藉由單鍵、雙鍵及三鍵任一結合 結之鄰接碳原子。例如，有機化合物可包括具有兩個 20個碳原子之烯屬烴及烯烴基，例如乙烯、丙烯、乙 丁二烯。 也可使用一或多種具有環狀團之碳氫化合物。此 用之名詞「環狀團（cyclic group)」意指為環形結構。 形結構可包含僅三個原子。該等原子可包括，例如碳、 氮、氧、氟及其結合物。該環狀團可包括一或多個單 • · · · · 雙鍵、三鍵及其任一結合。例如，一環狀團可包括一 個芳香族、芳香族羥基、苯基、環已烷、環己二烯、 二烯、及其結合物。該環狀團可為雙環或三環。此外 環狀團較佳係鍵結至一直鏈或分支官能基團。該直鏈 支官能基團較佳包含一烷基或烷基乙烯基團，且具有 個至20個碳原子。該直鏈或分支官能基團也可包括 子，例如酮、醚及酯類。一些具有至少一個環狀團之 性破氫化合物包括松油稀（alpha-terpinene，ATP)、乙 環已胺（vinylcycl〇hexane，VCH)及 已酸笨 (phenylacetate) ° 亦可選擇的是，該混合物中也可包括一或多種用 積低介電常數薄膜之載氣。可使用之載氣包括氬、說 氧化碳及其結合物。 該薄膜也可利用任何化學氣相沉積製程室進行沉 第1圖係說明一可使用之平行扳式CVD製程處理室 截面圖。該處理室10包括一高真空區15及一氣體散 而鍵 至約 炔及 處所 該環 矽、 鍵、 或多 環庚 ，該 或分 約 1 氧原 例示 烯基 酯 於沉 、 二 積。 1 0的 流歧 1374498.. 管11，該氣體散流歧管丨丨具有數個穿孔用以散佈製程氣 體至基材（未不出）。該基材置於一基材支撐板或晶座12 上。該轉座12安裝於一支撐桿13上，而該支撐桿13係連 接該轉座12及一升舉馬達14。該升舉馬達14可將該轉座 12升舉及降低於一製程位置及一較低之基材裝載位置，以 使轉座12(及該支撐於轉座12上表面上的基材）可控制地 移動於一較低之裝載/卸載位置及一較高之製程位置（相當 接近該歧管u)。當該轉座12及該基材位於一較高製程位 置時，絕緣體17係環繞該轉座丨2及該基材。 引入歧管11之氣體係均勻地徑向分佈於基材表面。一 具有節流閥之真空幫浦32可經由歧管24控制來自該處理 室1 0之氣體排氣速率。若需要時，沉積物及載氣可流經氣 趙線18進入一混合系統19並接著至該歧管n。一般而 言’各製程氣體供應線18包括⑴安全關閉閥（未示出），可 用以自動或手動地關閉流進處理室之製程氣體，以及（ii) 質流控制器（亦未示出），用以測量流經氣體供應線1 8之氣 體。當製程中使用有毒氣體時，習知配置中係於各氣體供 應線1 8上放置數個安全關閉閥。 於一實施態樣中，一有機矽化物係以一用於200或 3〇〇mm基材之流率（約lOOsccm至約lOOOOsccm)弓丨入該混 合系統1 9。該選擇性碳氫化合物係以一約丨〇〇sccm至約 lOOOsccm之流率引入該混合系統19。該選擇性使用之氧 化劑流率約為1 〇 〇 s c c m至約6 0 0 0 s c c m β該載氣流率約為 lOOsccm至約5000sccm。於一較佳實施例中，該有機矽化
10 物為八甲基環四矽氧烷（〇MCTS)，而該碳氫化合物為乙烯。 該沉積製程較佳為一電漿增強型製程。於一電漿增強 型製程中’ 一經控制電漿一般係藉施加（利用RF電源供應 器25)至氣體散流歧管Η之Rjj能量形成於該基材鄰近 處。或者’ RF電源可提供至轉座12。至該沉積處理室的 RF電源可為遇期式或脈衝式，以降低基材受熱並促進沉積 薄膜之多孔性。用於2〇〇mm或300mm基材之電漿電源密 度介約0.03W/cm2以及約3.2W/cm2之間，該值係與用於 200mm基材時約1 〇瓦至約.1 000瓦的RF電源位準相對應， 並與用於300mm基材時約20瓦至約2250瓦的RF電源位 準相對應。較佳來說’用於3〇〇mm基材之rf電源彳立準約 為200瓦至約1700瓦。 RF電源供應器25可提供一介約〇 〇1 mHz及300 MHz 間之單一頻率RF電源。較佳而言，該RF電源可利用混合、 同步頻率作傳送以增加引入高真空區域15之反應物種的 分解。於一實施態樣中，該混合頻率係一約1 2kHz之低頻 及一約13.56mHz之高頻的馮合頻率。於另一實施態樣中， 該低頻範圍介約300Hz至約i〇〇〇kHz間，而該高頻範圍介 約5mHz及約50mHz間。較佳而言，該低頻電源位準約為 1 50瓦’而該高頻電源位準以介約2〇〇瓦至約75〇瓦為佳， 且更佳者係介約2〇〇瓦至約4〇〇瓦。 於沉積期間’該基材係維持在約_ 2 〇及約5 〇 〇 °C間之 恤度，並以約1 〇〇 C至約45〇°c間為佳。該沉積壓力一般介 約1 Torr及約20 Torr ’並以介約4 τ〇ΓΓ至約7 τ〇ΓΓ間為 1374498 佳。下文將詳述依據此處所述實施例中可用於沉積一低介 電常數層之例示性處理室。 當欲遠端分解氧化氣體時，一可選擇使用之微波處理 室28便可在該氡體進入製程處理室10之前先將介約50 瓦至約6000瓦間的電源輸予該氧化氣體。該額外的微波電 源可避免該有機矽化物在與氧化氣體反應之前發生過量分 解。在微波電源加至氧化氣體時，以使用一具有個別用於
有機妙化物及氧化氣體之通道的氣體散流板（未示出）為 佳。 一般而言，該處理室内襯、散流歧管11、轉座12及 各種其他反應器硬體之任一或全部係以諸如鋁或電鍍鋁的 材料所製造。上述CVD反應器之一範例係描述於頒予 Wang等人並受讓予美商應用材料公司（本發明之受讓人） 的美國專利案第5,000,1 1 3號，標題為「A Themal CVD/PECVD Reactor and Use for Thermal Chemical Vapor Deposition of Silicon Dioxide and Multi-step Planarized Process」中，其全文與
本發明範圍相符部分係合併於此以供參考。 系統控制器3 4可控制馬連1 4、氣體混合系統1 9及高 頻電源供應器2 5，其等係藉控制線3 6相連接。系統控制 器34可控制該CVD反應器之作動且一般包括一硬碟機、 一軟碟機及一卡架（card rack)。該卡架包含一單板式電腦 (single board computer, SBC)、類比及數位輸入/輸出板、 介面板以及步進馬達控制板。系統控制器34符合總線模組 歐式卡（Versa Modular Europeans，VME)標準，該標準可界
12 1374498 • · · 定基板、卡盒（card cage)以及連接器尺寸及類型。該VME 標準也界定具有16位元數據及24位元位址匯流排之匯流 排結構。系统控制器3 4係操作於電腦程式（儲存於硬碟機 中38)的控制下。 此處所述之該低介電常數薄膜可利用電腦儲存媒體的 控制進行沉積，而該電腦儲存媒體包含一軟體常式，在執 行時，可使一通用電腦控制沉積處理室。該軟體常式可包 含數個指令，用以依據此處所述實施例之任一者沉積任一 薄膜。 後處理低介電常數薄膜
在該低介電常數薄膜沉積後，該低介電常數薄膜會以 一製程作後處理，該製程包括將該低介電常數薄膜快速加 熱致一所欲高溫，並接著將之快速冷卻。該所欲高溫可介 約600°C致約1〇〇〇°C，例如約800°C。較佳而言，該低介 電常數薄膜係由一介約2 5 °C至約2 5 0 °C之溫度，以至少約 1 0 °C /秒的速率加熱至該所欲高溫。例如，該低介電常數薄 膜可以約10°C /秒至約 300°C /秒的速率加熱。較佳而言， 該低介電常數薄膜係以一介約1〇〇°C /秒至約300°C /秒的速 率（例如約250°C /秒）作加熱。在該低介電常數薄膜達該所 欲高溫後，使關閉該用於加熱該低介電常數薄膜之熱源 (群），並以至少約1 0°C /秒（例如一介約1 〇°C /秒至約1 〇〇°C /秒之速率）冷卻該低介電常數薄膜。該低介電常數薄膜之 冷卻可藉由在該後處理製程室中設一反射板的方式提升。 較佳而言，該冷卻速率可藉該後處理製程室中之反射板、 ⑧ 13 1374498. 及藉將該基材（其上沉積有該低介電常數薄膜）背側暴露於 惰性氣趙（如氦氣）流等兩種方式予以提升，例如，該基材 背側可暴露於流率介約lOsccm至約500sccm之氦氣。由 於該低介電常數薄膜係作快速加熱及快速冷卻，該加熱低 介電常數薄膜之起始至冷卻該低介電常數薄膜之終了的時 間長度一般介約0.5分至約5分鐘》 一般而言’該低介電常數薄膜係於處理室氛圍下進行 加熱及冷卻該氛圍可能包括氬氣（Ar)、氮氣（n2)、氦氣 (He)、氧氣（〇2)、氫氣（H2)、水蒸氣（H20)、一氧化二氮（N20) 或其結合物。該處理室壓力可介約丨〇〇 Τ〇Γ1:及約760 T〇rr »該處理室壓力可經調整以改變該低介電常數薄膜的 冷卻速率。 於一實施例令，該低介電常數薄膜係於一氬氣環境下 作加熱及冷卻。於一實施例中，氬氣係以一介約l〇sccm 至約lOOsccm之速率引入該處理室中。 一可以約5秒或更少的時間（較佳為1秒或更少）將 低η電常數薄骐快速加熱至一所欲高溫、並接著將之快 速冷部的處理室均可用以後處理該低介電常數薄膜。依據 此處所述可用於後處理-低介電常數薄膜之-例示性處理 室將詳述如下。 種可使用之處理室為RadianceTMRTP處理室，其係 由加州聖 i °兄拉拉應用材料公司所上市。第2圖係說明一 處理至200，其為該RadianceTMRTP處理室之—實施例。 第2辱所不之處理t 200包括-由側壁214及底壁215圍 ⑧ 14 1374498 « · · 住之處理區213。該處理室2 00之側壁214上部係藉0形 環216密封至一窗口 248。
基材或晶圓261係藉一支撐環262(—般由碳化矽製成） 支撐於其邊緣内側區213。支撐環262係安裝於一可轉式 石英柱263上。藉由可轉式石英柱263，支撐環262及晶 圓261可因而旋轉。也可使用額外的碳化矽轉接環以讓不 同尺寸的晶圓（例如150mm、200mm及300mm)可作處理。 支撐環2 6 2外緣較佳係由晶圓2 6 1.外徑延伸不超過2英 吋。對300mm系統而言，處理室200容積大約為9公升。 處理室200包括一穿設側壁214之氣體入口 269，用 以將製程氣體注入區域213内以使不同製程步驟可於内實 施。位於氣體入口 2 6 9對側上（即側壁2 1 4處）者為一氣體 出口 268。氣體出口 268係耦接至一真空源286(例如幫 浦），以將製程氣體排出處理室200並降低處理室200中的 壓力。於製程期間該真空源2 8 6係維持在一所欲壓力，同 時將製程氣體餵進該處理室中。
輻射能組件2 1 8係位於該窗口 248之上。該輻射能組 件218包括數個鹵鎢燈219(例如Sylvania EYT燈），其各 安裝至一光導管221中且光導管可為不鏽鋼、金、铜、鋁 或其他金屬。包括一纏繞成為線圈之燈組219，其軸係平 行於該燈套（lamp envelope)之軸。絕大多數的光線會垂直 於該軸發散至周圍光導管221之壁。該光導管長度係經選 擇以至少與相關之燈組等長。該光導管22 1可較長以使觸 及基材之能量不會因增加的反射而實質減弱。該燈組219 ⑧ 15
1374498 * _ I
係以六角形陣列或蜂巢形方式設置。燈組2 1 9係經定 適當覆蓋基材 261及支撐環 2 62的整個表面積。 219(其可能為上百個之譜）係聚集於一區中，以可獨立 提供相當均勻或不均勻的晶圓261力d熱，如依據本發 程所欲求者。 該輻射能源2 1 8至少包含數個光導管2 2 1及相關 219，以使薄石英窗248可提供一光埠口，加熱該排真 製程處理室内的基材。該窗口 24 8的主要目的係將製 境與燈組219隔絕，避免燈組過熱而與製程氣體反應 導管2 2 1可藉流動一冷卻劑（例如水）於不同熱導管間 式予以冷卻。 雖然前述之輻射能源2 1 8包括數個鹵鎢燈2 1 9， 另一實施例中，該輻射能源2 1 8包括紫外光燈。 處理室200之底壁215包括一上表面211，用以 晶圓2 6 1背側上之能量。此外，處理室2 0 0包括數個 溫度探針2 70，穿設於處理室2 0 0底壁2 1 5以偵測晶圓 表面數個位置之溫度。石夕晶圓261及反射表面211間 射會形成一黑體腔（blackbody cavity) ’使溫度偵測不 圓背側發散影響，並提供正確溫度測量能力。 於一實施例中，該反射表面 2 11係呈吸收反射 式，其係以0.7至0.96nm波長反射，並以該輻射能 218發散之另一波長反射。該反射板之吸收特性可提 介電常數薄膜之冷卻速率。該低介電常數薄膜之冷卻 可藉由將該基材（其上沉積有該低介電薄膜）背側暴露 位以 燈組 控制 明製 燈組 空之 程環 。光 的方 然於 反射 光學 261 的反 受晶 板形 組件 升低 速率 於惰 ⑧ 16 1374498 .· · 氣流的方式進一步提升，例如藉由將惰性氣體引至該反射 板邊緣周圍或通過孔洞（設於反射板中）而至基材背側。
處理室200之態樣係由一控制系統（未示出）所操作。 該控制系統可包括任何數量的控制器、處理器及輸入/輪出 裝置。於一實施例_，該控制系統為一封閉迴路反饋系统 之元件，其可監控該製程處理室2〇〇内之各種參數，同時 處理一基材’並接著送出一或多個控制訊號以依據各種設 定值作必要調整。一般而言，被監控的參數包括溫度、壓 力及氣流速率。 於又一實施例中，後處理該低介電常數薄膜的步驟包 括將該低介電常數薄膜快速加熱至一所欲高溫，並由該所 欲高溫將該低介電常數薄膜作快速冷卻，並以一電子束處 理處理該低介電常數薄膜。該低介電常數薄膜可在該快速 加熱及快速冷卻前或後以一電子束處理進行處理。
該電子束（e-beam)處理一般劑量在約1至2〇千伏（KeV) 下係介於每平方公分50至約2000微庫倫（pc/cm2)。該電 子束電流一般介約1 mA至約40mA，且較佳約為i至約2〇 微米。該電子束電流一般介於約1mA至約4〇mA，而以約 1 mA至約20mA為佳。該電子束處理一般係操作在約室溫 至約45 0°C間之溫度下約10秒至約15分鐘。於_實施银 樣中，該電子束處理條件包括6kV、10-l8mA及5(^c/cm2 以35〇°C處理約15至約30秒，以處理厚度約i微米之薄 膜。於另一實施態樣中，該電子束處理條件包括4 5kv、 l〇-18mA 及 50μο/(：ιη2 以 350°C 處理約 15 至的,Λ . 之β 3 ϋ秒，以處 ⑧ 17 1374498 * · %
理厚度約5000A之薄瞪执—〜 Q 4膜。於該電子束處理期間可使用氬氣 及氫氣。雖然可使用 仕種電子束裝置，但一例示性裝置 為EBK處理室，其仫士 圹I 、“由應用材料公司所上市。在低介電常 數溥膜沉積後，以— €千末處理該低介電常數薄臈會揮發 該薄膜中至少若干右地 有機團’並因此於薄膜中形成孔洞。 第3圖係說明—仿诚 依據本發明之一實施例的電子束處理 器300。該電子束處理哭—』 爽理器300包括—真空處理室32〇、一大 面積陰極322、一位於 广w 证於一無％區（fleld free)338中之靶材面 30以及柵極陽極326 (設於該靶材面及該大面積陰 極322間）該電子束處理室3 00更包括一高壓絕緣體324 及一加速場區336(其可將該柵極陽極326由大面積陰極 322隔絕出）、一陰極覆蓋絕緣體328(位於該真空室Μ。 内） 可變簧片閥332(用以控制該真空室320内之壓 力）可變问壓電源供應器329(連接至該大面積陰極322) 以及一可變低壓電源供應器33〗（連接至該栅極陽極326)。
於操作中’該其上具有欲暴露於電子束之低介電常數 薄膜的基材（未示出）係置於該靶材面33〇上。該真空室32〇 係由大氣壓力抽吸至範圍約ImTorr至約 200mTorr之壓 力。該確切壓力係由可變速率簧片閥332所控制，其可將 壓力控制至約0. ImTorr。該電子束一般係於一足夠高壓下 產生，並藉高壓電源供應器329施加至大面積陰極322。 電壓範圍介約500伏特至約30000伏特或更高。該高壓電 源供應器329可為紐約州Bertan of Hickville公司所製造 之Bertan Model#105-30R電源供應器、或紐約州Spellman ⑤ 18 1374498 1 t * ·
High Voltage Electronics Corp” of Hauppauge 公司所製造 之 Spellman Model#SL30N-l 200X 258 電源供應器。該可變 低壓電源供應器331可施加一電壓至該柵極陽極326，其 相對於施加至該大面積陰極3 22之電壓為正值（p0sitive)。 此電壓係用以控制自該大面積陰極322的電子發散。該可 變低壓電源供應器331可為Acopian of Easton, Pa公司所 上市之Acopian Model#150PT12電源供應器。
該電子束處理室 3 00之其他細節則描述於授予 William R. Lives ay等人之美國專利案第5,003,1 78號，標 題為「Large-Area Uniform Electron Source」，其受讓予 Electron Vision Corporation公司（目前由本發明之受讓人 所擁有）且其全文與本發明相符部分係合併於此以供參考。 於另一實施例中，後處理該低介電常數薄膜之步驟包 括將該低介電常數薄膜快速加熱至一所欲高溫、將該低介 電常數薄膜由該所欲高溫快速冷卻及以紫外線（UV)輻射 處理該低介電常數薄膜。較佳而言，該低介電常數薄膜係 以UV輻射處理，同時對該低介電常數薄膜施予至少一部 份快速加熱及/或冷卻處理》然而，該低介電常數薄膜也可 在快速加熱及冷卻該低介電常數薄膜之前或之後以UV輻 射作處理。較佳而言，在快速加熱及冷卻低介電常數薄膜 之前或之後以UV輻射處理低介電常數薄膜之該等實施例 中，於UV輻射期間該低介電常數薄膜係以一介約200°C 至約600 °C間之溫度加熱。例如，該低介電常數薄膜可暴 露於一處理室中之UV輻射下，例如具有一 UV源之高溫 ⑧ 19 1374498 « · » 爐中。於uv輻射處理期間，該處理室可為真空或大氣壓 力氛圍。 該低介電常數薄膜可暴露於一或多種UV輻射波長 中 處理至之一範例及一可將該低介電常數薄膜暴露於 UV輕射下之方法係揭示於美國專利案第6,614，181號，其 係共同受讓予本案受讓人且全文合併於此以供參考。
於另一實施例中’該低介電常數薄膜係藉一方法進行 後處理包括將該低介電常數薄膜快速加熱及冷卻、以UV 輻射處理該低介電常數薄膜及以一電子束處理該低介電常 數。該後處理製程可以任何順序進行《然而，較佳者係依 據此處所述本發明之實施例將該低介電常數薄膜以快速加 熱及冷卻方式進行後處理，並同步UV輻射該低介電常數 薄膜，且接著以一電子束處理該低介電常數薄膜。
現已相信一包含快速加熱及快速冷卻低介電常數薄膜 並UV輻射及/或以電子束處理該低介電常數薄膜的後處理 可提升低介電常數薄膜的特性。例如’現已相信一包括快 速加熱及快速冷卻及uv賴射的後處理會降低該沉積薄膜 之介電常數，並增加薄膜硬度及模數（modulus)。於前述任 —實施例中’該低介電常數薄膜可於一集成製程系統（例如 美商應用材料公司所上市之Centura®4 Producer®機台）内 作沉積及後處理。因此’該低介電常數薄膜可在無需暴露 至大氣壓下的方式進行沉積及後處理。於實施超過—種後 處理製程之實施例中，該低介電常數薄膜於不同後處理製 程間可受保護免受大氣影響。例如’在另一處理室中快速 20 1374498 • I ' 加熱及冷卻及選擇性實施之uv輻射後，該低介電常數薄 膜可送至一電子束處理室，而無需在快速加熱及快速冷卻 與電子束處理之間暴露於大氣下。 下文範例將說明處理其上沉積有低介電常數薄膳沉積 之基材的方法。該薄膜係利用美商應用材料公司所上市之 Producer®CVD處理室沉積於300mm基材上。 比較例 1 9 一包含矽、碳及氧的低介電常數薄膜係由一包含八甲 基環四矽氧烷（OMCTS)、三甲基矽烷以及乙烯之氣體混合 物沉積於一基材上。該OMCTS係以約520sccm之流率引 入處理室中，該三甲基矽氧烷係以300sccm引入該處理室 中，且該乙烯係以約2200sccm的流率引入該處理室。氦 氣係以約1000seem之流率引入處理室中，而氧氣係以約 lOOOsccm 之流率引入處理室。該薄膜利用頻率為 13.56MHz之800瓦RF電源於400ΐ、5.7 Torr之壓力下 沉積約 20秒。當沉積時，該低介電常數薄膜厚度為 5 04 3A，介電常數（k)為2.77，且硬度為0.59gPa。 比較例2 比較例1中係描述將低介電常數薄膜沉積於一基材 上。該低介電常數薄膜係於800°C之溫度下進行熱退火處 理1分鐘的方式作後處理。當沉積時，該低介電常數薄膜 厚度為5085A。在該後處理後，該低介電常數薄膜厚度為 ⑧ 21 1374498 4463 A(收縮率為1 2.2%) °在該後處理後，該低介電常數薄 膜之介電常數（k)為3.35，且硬度為1.82 gPa。 比較例 3
比較例1中係描述將低介電常數薄膜沉積於一基材 上。該低介電常數薄膜係於溫度800°C、加速電壓4.5kV 下以3mA且劑量為1 00pc/cm2之電流的電子束處理進行後 處理。當沉積時，該低介電常數薄膜厚度為507 4人。在該 後處理後，該低介電常數薄膜厚度為 47 63 A(收縮率為 6.1 %)。在該後處理後，該低介電常數薄膜之介電常數（k) 為2.74，且硬度為1 · 14 gPa。 範例1
比較例1中係描述將低介電常數薄膜沉積於一基材 上。該低介電常數薄膜係於RadianceTM RTP處理室中由室 溫快速加熱至8 0 0 °C並接著快速冷卻至1 2 0 °C，以使該低介 電常數薄膜在3 0秒内被加熱及冷卻的方式進行後處理。當 沉積時，該低介電常數薄膜厚度為5036人。在該後處理後’ 該低介電常數薄膜厚度為5021A(收縮率為0.3%)。在該後 處理後，該低介電常數薄膜之介電常數（k)為2.53，且硬度 為 0.62 gPa。 範例2 比較例1中係描述將低介電常數薄膜沉積於一基材 ⑧ 22 1374498 • · ·
上。該低介電常數薄膜係於RadianceTM RTp處理室 溫快速加熱至8 0 〇 t並接著快速冷卻至1 2 0 °c，以使 電常數薄膜在30秒内被加熱及冷卻的方式進行後處 沉積時’該低介電常數薄膜厚度為5011A。在該後處 該低介電常數薄膜厚度為49 9 6 A(收縮率為0.3%)。 處理後，該低介電常數薄膜之介電常數（k)為2.44。 範例1及範例2均說明了在依據此處所述實施 速加熱及快速冷卻該低介電常數薄膜的方式後處理 電常數薄膜會使薄膜之介電常數較未作後處理之薄 以電子束處理或習知退火處理作後處理之薄膜者為 人相信以此處所述之後處理處置的薄膜將可藉由對 後處理’使孔化劑（ρ 〇 r 〇 g e n s，例如有機團）由低介 薄膜釋出的方式達到低介電常數。 範例1更說明了依據此處所述實施例快速加熱 該低介電常數薄膜並不會對沉積薄膜的硬度造成影 等範例也說明了依據此處所述實施例所進行的低介 薄膳後處理’其相較於其他後處理製程所導致的收 低。 因此，本發明之該等實施例係提供一種低介電 膜之後處理方法，以在不降低該薄膜硬度的情況下 介電常數，並使因後處理造成的收縮減至最小。本 等實施例中快速加熱及冷卻後處理的其他優點包括 速的後處理製程而使基材產量較高’並降低依據本 施例處理之基材的熱預算。 中由室 該低介 L理》當 理後， 在該後 例以快 該低介 膜、或 低。吾 其進行 電常數 及冷卻 響〃該 電常數 縮率更 常數薄 降低其 發明該 可因快 發明實 23 ⑧ 1374498 • · 雖然前文所述係與本發明之該等實施例有關，然而本 發明之其他及進一步的實施例應可在不悖離本發明基本範 圍的情況下作潤飾，而本發明範圍係由下文之申請專利範 圍所決定。 【圖式簡單說明】 本發明前述該等特徵可藉本發明簡述於上之詳細、明 確的敘述並參照實施例及附加圖示之說明而得以領會。然 而應注意的是，鵁等附加圖示僅為本發明之一般實施例， 因此不應視為其範圍之限制，本發明範圍亦應涵蓋其他等 效實施例。 第1圖係一例示性CVD反應器之截面圖，其係經配置 以依據本文所述實施例來使用。 第 2圖係依據本發明一實施例之快速熱製程（RTP)處 理室之一部份的垂直截面概要圖。 第3圖係依據本發明實施例之一電子束處理室。
【主要元件符號說明】 10 製 程 處理室 11 氣 體 散 流 歧管 12 轉 座 13 支 撐 桿 14 升 舉 馬達 15 高 真 空 區 域 17 絕 緣 體 18 氣 體 供 應 線 19 混 合 系統 24 歧 管 25 RF電源供應器 28 微 波 處 理 室 24 ⑧ 1374498 « « ·
32 真空幫浦 34 系統控制器 36 控制線 38 硬碟機 200 處理室 211 表面 213 區域 214 側壁 2 15 底壁 216 0形環 218 能源組件 219 鹵鎢燈 221 光導管 248 窗口 261 晶圓 262 支撐環 263 石英柱 268 氣體出口 269 氣體入口 270 溫度探針 286 真空源 300 電子束處理室 320 真空處理室 322 大面積陰極 324 高壓絕緣體 326 柵極陽極 328 覆蓋絕緣體 329 南壓電源供應β 330 靶材面 33 1 低壓電源供應器 332 可變速率簧月閥 336 加速場區 338 無場區
25

Claims (1)

1374498 第f%。八作號萌这/%年~月glk _ t · ㈣年^月，曰修(更)正本 拾、申請專利範圍：--——- 1. 一種處理一基材之方法，其包含下列步驟： 於RF電源下沉積一包含矽及碳之低介電常數薄膜於 一基材上；以及 以一製程對該沉積之低介電常數薄膜進行後處理，該 製程包含：
將該低介電常數薄膜以至少1 〇°C /秒的速率加熱至 一至少 600°C之所欲溫度，其中該低介電常數薄膜維持在 該所欲溫度5秒或更少；且接著 以至少1 0 °C /秒的速率冷卻該低介電常數薄膜。 2.如申請專利範圍第1項所述之方法，其中該後處理係於 足以降低該低介電常數薄膜之介電常數的條件下實施。
3.如申請專利範圍第1項所述之方法’其中該低介電常數 薄膜係以一介於1 〇 °C /秒至3 0 0 °C /秒的速率加熱，並以 一介於1 0 °C /秒至1 〇 〇 °C /秒的速率冷卻。 4.如申請專利範圍第1項所述之方法’其中該後處理更包 括以紫外光（UV)輻射處理該低介電常數薄膜。 5.如申請專利範圍第4項所述之方法，其中該包含加熱及 冷卻該低介電常數薄膜的製程係與以紫外光輻射處理 26 1374498 該低介電常數薄膜同時進行。 6.如申請專利範圍第5項所述之方法，其中該後處理更包 括以一電子束處理該低介電常數薄膜。
7.如申請專利範圍第6項所述之方法，其中該低介電常數 薄膜係於一集成製程系統中進行後處理，以使該低介電 常數薄膜在加熱及以一電子束處理該低介電常數薄膜 之間不會暴露於大氣下。 8.如申請專利範圍第4項所述之方法，其中該包括加熱及 冷卻該低介電常數薄膜之製程以及以紫外光輻射處理 該低介電常數薄膜係相繼進行。
9.如申請專利範圍第1項所述之方法，其中該後處理更包 括以一電子束處理該低介電常數薄膜。 10.如申請專利範圍第9項所述之方法，其中該低介電常數 薄膜係於一集成製程系統中進行後處理，以使該低介電 常數薄膜在加熱及以一電子束處理該低介電常數薄膜 之間不會暴露於大氣下。 11.如申請專利範圍第1項所述之方法，其中該低介電常數 27 1374498 薄膜更包含氧。 12. —種處理一基材之方法，其包含下列步驟： 於RF電源下沉積一包含矽及碳之低介電常數薄膜於 一基材上：以及 以一製程對該沉積之低介電常數薄膜進行後處理，該 製程包含：
將該低介電常數薄膜由一介於2 5 °C至 2 5 0 °C之溫 度加熱至一介於600 °C至1000 °C之溫度，其中該低介電常 數薄膜係於該介於600°C至l〇〇〇°C之溫度加熱 5秒或更 少；且接著 將該低介電常數薄膜由一介於600°C至 l〇〇〇°C之 溫度冷卻，其中該低介電常數薄膜係於〇. 5分鐘至5分鐘 的一時間範圍内作加熱及冷卻。
13.如申請專利範圍第12項所述之方法，其中該低介電常 數薄膜係以一介於1 0 °C /秒至3 0 0 °C /秒的速率加熱，並 以一介於1 0 °C /秒至1 0 0 °C /秒的速率冷卻。 14.如申請專利範圍第12項所述之方法，其中該後處理更 包括以紫外光輻射處理該低介電常數薄膜。 15.如申請專利範圍第12項所述之方法，其中該後處理更 28 1374498 包括以一電子束處理該低介電常數薄膜。 16_如申請專利範圍第12項所述之方法，其中該冷卻該低 介電常數薄膜的步驟包括將該基材暴露於背側氣體。 17. —種處理一基材之方法，其包含下列步驟：
於RF電源下沉積一包含矽及碳之低介電常數薄膜於 一基材上；以及 以一製程對該沉積之低介電常數薄膜進行後處理，該 製程包含： 將該低介電常數薄膜以一至少1 〇 °c /秒的速率加熱 至一所欲溫度，其中該低介電常數薄膜係維持在該所欲溫 度5秒或更少；且接著
將該低介電常數薄膜以一至少 1 0 °C /秒的速率冷 卻，其中該低介電常數薄膜係於〇. 5分鐘至5分鐘的一時 間範圍内作加熱及冷卻。 18.如申請專利範圍第17項所述之方法，其中該低介電常 數薄膜係由一介於2 5 °C至2 5 0 °C的溫度作加熱，而該所 欲溫度介於800°C至900°C。 19.如申請專利範圍第17項所述之方法，其中該後處理更 包括以紫外光輻射處理該低介電常數薄膜。 29 1374498 20.如申請專利範圍第17項所述之方法，其中該後處理更 包括以一電子束處理該低介電常數薄膜。
30
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