TWI358750B - Mask structure for manufacture of trench type semi - Google Patents

Mask structure for manufacture of trench type semi Download PDF

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TWI358750B
TWI358750B TW096114602A TW96114602A TWI358750B TW I358750 B TWI358750 B TW I358750B TW 096114602 A TW096114602 A TW 096114602A TW 96114602 A TW96114602 A TW 96114602A TW I358750 B TWI358750 B TW I358750B
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trench
metal layer
layer
wafer
semiconductor device
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TW096114602A
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TW200746260A (en
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Luigi Merlin
Giovanni Richieri
Rossano Carta
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Siliconix Technology C V
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    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
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    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology

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Description

1358750 九、發明說明： C發明所屬之技術領域3 發明領域 本申請案主張提出申請於2006年4月26曰之美國暫時 5 性專利申請案第60/795,026號之優先權，該申請案之整份 文件内容被併入此處作為參考。 本發明關於一種用於製造溝槽型半導體裝置的方法， 更特別地，關於用於該方法的光罩結構。
【先前技術3 10 發明背景
光罩結構通常用於控制矽溝槽的蝕刻及用於控制將雜 質植入此種結構中。此種光罩結構係複雜的且常常不能用 於例如碳化矽（SiC)等某些基材材料，因為此種材料需要長 時間與高溫的處理步驟。所以需要有一種可以用於碳化矽 15 基材（包括4H碳化矽）以及其他基材（諸如矽或相似物） 的光罩製程，其中單一的光罩結構可被用於溝槽蝕刻製程 或同時用於溝槽蝕刻與植入製程兩者。 發明概要 20 依據本發明，一光罩藉由光阻硬質光罩形成在一薄金 屬層（例如5000A的鋁）上，該薄金屬層覆蓋基材上的氧化 物層（1微米LTO)。於使用一 SiC基材且想要形成例如一 JFET的地方，需要的溝槽約2微米深及1-3微米寬，且相鄰 的溝槽被平台分隔約1.5-2.0微米寬。一光阻（PR)光罩層 5 較正極PR’且在顯影後將容許窗的打開及被暴露之 下，，屬與氧化物的電聚姓刻進入基材内以及相隔之溝槽 的接續電漿·進入基材内。該光罩可對抗長期的飯· 程且可成為接受下一個離子植入製程的光罩。 、本發明的硬質光罩可用於兩個獨立的製程步 驟；溝槽閘極形成（用於—肿T)與—離子植人摻雜之自 我對準光罩。 硬質光罩材料的選擇應該考慮與植入離子種類及能量 相關的電聚姓刻選擇性與離子停止或阻擒範圍大小。光罩 10的厚度依基材材料而調整。 雖然本發明於下述例子中被應用於Sic JFET，本發明
可應用於任何的溝槽半導錄置（諸如MOSFETs、IGBTS 及相似物）’也可應用於不是Sic的其他基材材料。 更且，於某些應用中可能會除去金屬層下方的氧化緩 15 衝層。 圖式簡單說明 第1圖顯示起始晶圓10之一小部分的橫切面， 第2圖顯示第-製程步驟，其包括在晶圓上方形成氧化 物， 20 第3圖顯示—光阻層形成在金屬層21上方且被遮罩及 顯影而在金屬層上方形成間隔的蝕刻窗， 第4圖顯示被蝕刻窗暴露的金屬層及氧化物層部分被 電漿钱刻至晶圓的SiC表面， 第5圖顯示執行乾式電漿蝕刻以蝕刻間隔的溝槽進入
SiC飄移層13 ^ C :¾'式 j 較佳實施例之詳細說明 第1圖顯示起始晶圓10之一小部分的橫切面。第1圖的 晶圓10是碳化矽（Si(:)，雜其他材料也可以。所要製造 的70件是JFET，起始晶圓有一厚度約35〇微米且濃度約 1.8E18的N基材汲極體u。一 N'緩衝層12在汲極區丨丨上 方’-N型飄移區13在緩衝層12上方，_N+源㈣14在飄移 區13上方。 第2圖顯示第-製程步驟’其包括在晶圓1()上方形成氧 化物層20 (例如LTO)。氧化物層2〇的厚度約為〇 8微米。然 後在氧化物層20上方沉積鋁層21至厚度為約〇 5微米。 其他可減少整個光罩厚度之層2〇及21的選擇為例 如，0.1-10微米的氧化物層及〇_M〇微米的鋁層或其他適合 的金屬。 在一些案例中，氧化物層20會被完全移除。 然後，一光阻（PR)層30(第3圖）形成在金屬層21 上方且被遮罩及顯影而在金屬層21上方形成間隔的蝕刻窗 40 〇 光阻層30較佳為正極pr且其被用於本發明之新穎硬質 光罩結構中以執行後續的溝槽/植入步驟》 然後，如第4圖所示，被蝕刻窗40暴露的金屬層21及氧 化物層20部分被電漿蝕刻至晶圓的sic表面。 最後，如第5圖所示，執行乾式電漿蝕刻以蝕刻間隔的 1358750 溝槽進入SiC飄移層13。 光阻層30可被移除而剩下的硬質光罩20/21被留在原 為以繼續離子植入溝槽50之溝槽壁中的步驟。 溝槽50之溝槽壁可為垂直的或可與晶圓表面呈（垂直 5 的）80-90度角，亦即溝槽壁可與通過溝槽中心之垂直線最 多呈10度角且垂直晶圓平面。
雖然本發明已經隨著特定實施例而被描述，但對於習 於此藝者而言許多的變化與修飾及其他用途仍將變得更為 顯明。因此，本發明較佳地不被上述該等特定的揭露内容 10 所限制。 【圖式簡單說明3 第1圖顯示起始晶圓10之一小部分的橫切面， 第2圖顯示第一製程步驟，其包括在晶圓上方形成氧化 物， 15 第3圖顯示一光阻層形成在金屬層21上方且被遮罩及 顯影而在金屬層上方形成間隔的蝕刻窗， 第4圖顯示被蝕刻窗暴露的金屬層及氧化物層部分被 電漿蝕刻至晶圓的SiC表面， 第5圖顯示執行乾式電漿蝕刻以蝕刻間隔的溝槽進入 20 SiC飄移層13。 【主要元件符號說明】 10.··晶圓 13...飄移層 11...>及^區 14...源 區 12···、緩衝層 20...氧化物層 8 1358750 21.. .金屬/銘層 30.. .光阻層 40.. .蝕刻窗 50.. .溝槽

Claims (1)

  1. 第96114602號申請案申請專利範圍修正頁 100.09.19. 十、申請專利範圍： 1. 一種溝槽型半導體裝置，包含： 一半導體晶圓； 一設置於該晶圓上方之硬質光阻光罩，其中該硬質 光阻光罩包含一金屬層，且其中該硬質光阻光罩之一第 一部份可阻擋一蝕刻處理，且其中該硬質光阻光罩包含 一氧化物層，其中該氧化物層係介於該金屬層與該晶圓 之間；以及 一延伸通過該硬質光阻光罩之一第二部份之溝槽 閘極，其中該溝槽閘極係使用該硬質光阻光罩之該第一 部份而離子植入。 2. 如申請專利範圍第1項之溝槽型半導體裝置，其中該晶 圓係為碳化矽。 3. 如申請專利範圍第1項之溝槽型半導體裝置，其中該溝 槽閘極延伸通過該硬質光阻光罩之該第二部份及該晶 圓之一部份。 4. 如申請專利範圍第3項之溝槽型半導體裝置，其中該晶 圓係為破化石夕。 5. 如申請專利範圍第3項之溝槽型半導體裝置，其中該溝 槽閘極之該等壁與通過經形成之該溝槽閘極之一垂直 線呈0-10度的一角度，該垂直線係與該晶圓的該平面垂 直。 6. 如申請專利範圍第1項之溝槽型半導體裝置，其中該金 屬層係具有一約為0.1-1微米的厚度的鋁。 1358750 第96114602號申請案申請專利範圍修正頁 100.09.19. 5
    10 15
    20 7. 如申請專利範圍第1項之溝槽型半導體裝置，其中該氧 化物層具有一約為0.1-1.0微米的厚度。 8. 如申請專利範圍第6項之溝槽型半導體裝置，其中該氧 化物層具有一約為0.1-1.0微米的厚度。 9. 如申請專利範圍第1項之溝槽型半導體裝置，其中該金 屬層係選自由鋁、鎳、嫣及组組成之群組且具有一約為 0.1-1.0微米的厚度。 10. 申請專利範圍第1項之溝槽型半導體裝置，更包含： 一形成於該金屬層之一部份上方之光阻層，該光阻 層形成至少一開口，其中該金屬層係被暴露。 11. 申請專利範圍第10項之溝槽型半導體裝置，更包含： 位於該一開口之一電漿蝕刻部份，其中該電漿蝕刻 部份延伸至該半導體晶圓之一表面。 12. —種用以於半導體晶圓形成溝槽之方法，該方法包含下 列步驟： 於該晶圓之表面上方沉積一氧化物層； 於該氧化物之表面上方沉積一金屬層； 於該金屬層上方沉積一光阻； 於該光阻上方施加一圖案化光罩； 光微影蝕刻地顯影該光阻以形成一含有對應於該 光罩之該圖案之窗的硬質光阻光罩； 移除該金屬層之通過該等窗暴露之部份； 於該晶圓之該頂部表面内形成一於該金屬層之該 等部份移除後暴露的溝槽，其中該硬質光阻光罩之一部 11 1358750 第96114602號申請案申請專利範圍修正頁 100.09.19. 份阻擋與該形成有關之蝕刻；以及 使用該硬質光阻光罩之該部份植入一經控制的雜 質於該溝槽之溝槽壁内。 13. 如申請專利範圍第12項之方法，更包含： 5 在形成該溝槽前，移除在該金屬層之對應區域移除 後暴露的該氧化物層的該等區域，其中該氧化物層係直 接地位於該晶圓上方且係直接地位於該金屬層下方。 14. 如申請專利範圍第12項之方法，其中該金屬層係為具有 一約為0.1-1.0微米的厚度的鋁。 10 15.如申請專利範圍第13項之方法，其中該氧化物層具有一 約為0.1-1.0微米的厚度。 16.如申請專利範圍第12項之方法，更包含： 遮罩該晶圓之該表面以抵擋藉由以該金屬層組成 之該硬質光阻光罩的該部份的該植入。 15 17.如申請專利範圍第13項之方法，更包含： 遮罩該晶圓之該表面以抵擋藉由以該金屬層組成 之該硬質光阻光罩的該部份的該植入。 18. 如申請專利範圍第12項之方法，其中該金屬層係選自由 鋁、鎳、鎢及钽組成之群組且具有一約為0.1-1.0微米的 20 厚度。 19. 如申請專利範圍第12項之方法，更包含： 移除該金屬層上方之該光阻。 12 1358750 第96114602號申請案圖式修正頁 修正曰期：100.09.19.
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