TWI329351B - Silicided recessed silicon - Google Patents

Silicided recessed silicon Download PDF

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Publication number
TWI329351B
TWI329351B TW095132096A TW95132096A TWI329351B TW I329351 B TWI329351 B TW I329351B TW 095132096 A TW095132096 A TW 095132096A TW 95132096 A TW95132096 A TW 95132096A TW I329351 B TWI329351 B TW I329351B
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Taiwan
Prior art keywords
metal
recess
trench
layer
memory device
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TW095132096A
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English (en)
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TW200721391A (en
Inventor
Hasan Nejad
Gordon A Haller
John Mark Meldrim
Thomas A Figura
Ravi Iyer
Justin Harnish
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Micron Technology Inc
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H10B12/05—Making the transistor
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    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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Description

1329351 九、發明說明： 【發明所屬之技術領域】 本發明大體而言係關於矽化物化反應及其產物，且更詳 吕之係關於凹座内矽之完全矽化物化。 【先前技術】 積體電路設計在不斷地成比例縮小以降低功率消耗且增 加速度。隨著每次更新換代，裝置傾向於變得更小且更緻 密封裝，從而產生多種關於積體化之問題。積體化問題之 一為提供給導電元件的體積較小。為達成可接受之電路速 度’重要的為此等元件具有極高之傳導率。 其他問題與加襯或填充高縱橫比溝槽或通道中之困難相 關。舉例而言，伸長之溝槽係用於波紋金屬化，隔離電洞 或通道係用於形成垂直接觸，基板上之堆疊溝槽及基板内 之深溝槽係用於記憶體單元電容器之形成等等。隨著每次 更新換代，由於較高之縱橫比此等通道内之沈積變得更具 挑戰。在沈積或隨後的處理過程中，可易於形成空隙，從 而導致較低的裝置良率。 【發明内容】 根據本發明之一態樣，提供一種用於在積體電路内形成 金屬矽化物結構之方法。該方法包括於部分製成之積體電 路内提供一凹座。將矽沈積於該凹座中。將金屬混合物尤 積於該凹座上且與矽接觸，其中金屬混合物包括至少兩種 相對於矽具有相反擴散性之金屬。金屬混合物與碎於該凹 座内反應以於該凹座内形成金屬矽化物。 n4280.doc • .6 - 1329351 根據本發明之另一態樣，提供一種用於形成積體電路之 内嵌存取裝置之方法。該方法包括於半導體結構中蝕刻溝 • 槽。將該溝槽以介電層加襯且以矽至少部分填充該經加襯 之溝槽。將金屬層沈積於溝槽上且與矽接觸。使溝槽中之 石夕在石夕化物化反應中與金屬層完全反應。 根據本發明之另一態樣，提供一積體電路，其包括金屬 石夕化物結構。金屬矽化物無空隙填充凹座之至少一下部部 • 分。該金屬矽化物包括至少一第一金屬之混合物，該第一 金屬於矽中之擴散性高於矽於該第一金屬中之擴散性。該 孟屬矽化物亦包括第二金屬，該第二金屬於矽中之擴散性 低於矽於該第二金屬中之擴散性。 根據本發明之另一態樣，提供一記憶體裝置。該記憶體 裝置包括記憶體陣列中之内嵌存取裝置，該記憶體裝置包 括一半導體基板内之-凹座，一使該凹座加觀之薄介電層 及無空隙填充該溝槽之至少一下部部分之金屬石夕化物。 • 【實施方式】 儘管本發明之較佳實施例係結合間距加倍技術進行說 明，但應瞭解此等較佳實施例之電路設計可併入任何積體 電路中。特定言之，其可有利用於形成具有電裝置陣列之 任何裝置’包括邏輯或閘極陣列及揮發或非揮發性記憶體 裝置’諸如DRAM、RAM或快閃記憶體。由本文描述之方 法形成之積體電路可併入許多較大系統中之任何系統，諸 如主機板、桌上型電腦及膝上型電腦、數位相機、個人數 位助理或任何記憶體適用之許多裝置中之任何裝置。 114280.doc 1329351 ▲根擄本發明之—實施例佈置之_記憶體裝置⑽颜的設 計及運作於圖中說明且在下文更詳細地描述。 請示記憶體裝置1〇一部分之示圖。此示意性佈置說 明形成記憶體裝置Π)之各種電裝置及其他組件。當缺，此 等組件中之許多在純直觀表示中係不可區分的，且人為將 -些圖1中展示之組件與其他組件相區分以強調其功能。 記憶體裝置1〇係於基㈣之上及其令構建，該基板形成電 裝置於其中形成之半導體材料之最低水平面。基板u一般 包含石夕。當然’如熟習此項技術者所熟知，亦可使用其他 合適材料（例如其他m_v族元素）。當描述其他組件時，如 最佳於圖2中可見參考基板11之頂面可最容易瞭解其深度 或高度。 圖1中亦展示沿記憶體裝置10延伸之4條伸長字㈣^ m、12c、12d。在一較佳實施例中，此等字線12係使用 間距加倍技術形成。註士 取砰5之，此荨字線12較佳係藉由將參 考圖3·9更詳細討論之方法形成。使用此技術’所得特徵 :間距可小於由光微影技術界定之最小間距。例如，在一 實施例巾’所得特徵之間距可等於由光微料術界定之最 小間距之一半。 取 般而。，如熟習此項技術者所熟識，間距加倍可藉 以下步驟順序執行。首先’可使用光微影在覆於一層可消 =料及基板上之光阻層中形成線圖案。此 相鄰之-線之間達成一間距’如上文所揭示，該間距= 徵限制。在一實施例中，F在60至刚⑽之 114280.doc 1329351 範圍内。此範圍對於用以界定特徵之 影技術而言係典型的。乂 一丄 展尺十之先檨 在光微影系統中，；F等於大約 ，而在另一系統中，F等於大約78細。 • 二熟習此項技術者所熟識，通常將光微影界定之各線之 寬度亦定義為F。接荽叮—丄 卜夂爻谷踝之 將圖牵接者可錯由蝕刻步驟（較佳為各向異性） ==可消耗材料之下層，藉此於下層中形成占位 =。接者可將光阻線去除，且可將心抽各向同性㈣ #離自F增加至二間:;離。刚^ ，，收縮”或，，修整”_接1可在抗鞋水平丁執行各向同性 、 蝕刻。接者可將間隔材料之等形層沈積於 。此材料層同時覆蓋心軸之水平及垂直表面。因 料，：,由以定向間隔蝕刻優先蝕刻來自水平表面之間隔材 料 轴之側形成間隔’即自另一材料之側壁延仲之材 扣 將剩餘之心軸選擇性移除，僅留下間隔，里可- 界…於圖索化之遮罩。因此，在既定間距2F先前包括 ·==徵及-個間隙之圖案處，現在相同之寬度包括 ^疋之兩個特徵及兩個間隙。因此’有效降低以既 2微影技術可達成之最小特徵尺寸。此間❹倍方法將 文中參考圖3_9於更詳細地討論，其可重複用於進一 步降低特徵尺寸。 :然’如此項技術中所熟知’收縮/修整姓刻之範圍及 明^之厚度可改變以達成多種特徵及間距尺寸。在說 之·^例中，儘管光微影技術可解析2f之間距，但特徵 J中之子線12)具有間距F。字線12由約F/2之寬度 H4280.doc 1329351 界定’且相鄰之字線12a、1沘或12c、l2d係以相同寬度 F/2分離。同時，作為間距加倍技術之附帶結果，間隔分 離字線12b、12c之間之距離為3F/2。在一較佳實施例中， 將隔離溝槽係以絕緣體填充且其位於此等字線l2b、i2c2 間之此距離内；然而，在其他實施例中，不需要存在此隔 離溝槽。 對於每一 3F之距離而言，存在兩條字線，從而產生可稱 作3F/2有效間距之間距。更一般而言，字線較佳具有} 25F 與1.9F之間之有效間距。當然，用以界定字線之特定間距 僅為一實例。在其他實施例中，可藉由更習知之技術製造 字線且不需要使用間距加倍β舉例而言，在一實施例中， 字線可各自具有F之寬度且可以F、2F、3F或一些其他寬度 分離。在其他實施例中，字線亦不需要成對形成。舉例而 言’在一實施例中’僅需要一條字線穿過各有效區。 子線12之全長於圖1中不可見，但在一典型實施例中， 各字線12可延伸穿過數百、數千或數百萬之電晶體。如熟 習此項技術者所熟知’在字線12之邊緣，字線12一般電耦 合至諸如電源之裝置，該裝置可提供穿過字線12之電流。 通常’用於字線12之電源經由記憶體控制器間接耦合至 CPU。 在一實施例中，字線12包含p型半導體，諸如摻雜硼之 矽。在其他實施例中，如熟習此項技術者所熟知，字線12 可包含η型半導體、金屬矽化物、鎢或其他類似作用之材 料。在一些實施例中，字線12可包含層化、混合或化學結 114280.doc 1329351 合組態之多種材料。 圖1可見之水平線係由數位線14a、i4b形成。在一示範 • 性實施例中，圖1中以DL說明之此等數位線各自之寬度等 於F °形成此等示範性數位線14中未使用單距加倍。在一 較佳實施例中，相鄰數位線14a、14b由圖1中以s說明之等 於2F之距離分離。數位線之間距較佳大於2.5F，且較佳小 於4F。未使用間距加倍技術，當然由用以形成數位線之光 • 微影技術施加較低限制。另一方面，在此範圍之上端附 近’光Μ影較不精確且因此較為便宜，但記憶體自身開始 生長過大。在一更佳實施例中，數位線之間距介於2.7 5 ρ 與3.25F之間。此範圍代表製造簡易性與晶片尺寸之間合 乎需要的平衡。在說明之實施例中，數位線14具有3F之間 距。S然’在其他實施例中，不同寬度及間距係可能的。 如同子線12，數位線14之全長於圖1中亦不可見，且數 位線14通常延伸穿過許多電晶體。如熟習此項技術者所熟 • 知，在數位線14之邊緣，數位線Μ通常電耦合至電流感應 放大器，且藉此耦合至電源或電壓源。通常，用於數位線 14之電源亦經由記憶體控制器間接耦合至cpu。由於數位 線14之間更放寬之間距，感應放大器可彼此間隔更遠，從 而放寬其製造公差且降低相鄰數位信號電容搞合 月 t* 性。 在一實施例中，數位線14包含導電金屬，諸如鎢、鋼或 銀。在其他實施例中，如熟習此項技術者所熟知，可使用 其他導體或半導體。 114280.doc 1329351 圖1中可見之其他特徵為經說明處於曲線矩形中之有效 區16’其形成相對於數位線之軸b成角度之軸a。此等矩 形代表基板11内之摻雜區或井；然而，在其他實施例中， 此等矩形不需要代表記憶體裝置1〇及基板u之内或之上的 物理結構或材料。有效區16界定含有場效電晶體且通常由 場隔離元件（例如淺溝槽隔離（STI))圍繞之記憶體裝置1〇之 彼等部分。在一較佳實施例中’此等有效區各自包含兩個 汲極18及一個源極2〇。如熟習此項技術者所熟知，源極及 汲極可大於或小於圖丨所說明者。其亦可以熟習此項技術 者所熟知之許多方式中之任何方式來製造。 在另一實施例中，有效區可包含一個源極及一個汲極， 其中源極係於數位線附近形成，且汲極係經字線與源極分 離。在此實施例中，記憶體裝置可類似於圖丨中之記憶體 裝置10配置，但僅需要一條字線穿過各有效區。當然，在 另一實施例中，有效區可包含一個源極及_個汲極，且記 憶體裝置可進一步包含於有效區附近延伸之兩條字線，其 類似於圖！中所展示之成對字線12c、12d配置。在此實施 例中，兩條字線皆可於源極與汲極之間延伸，且提供電晶 體之冗餘控制。 如所說明，數位線丨4鄰近位於數位線列中之各源極汕且 較佳在其上延伸（參見圖2)。同時，各源極2〇之各側經字線 !2與其相鄰之極汲18分離。在—實施例中，源極2〇及汲極 18包含η型半導體材料，諸如以摻雜磷或銻之矽。在並他 實施例中’如熟習此項技術者所熟知，源㈣及極㈣可 114280.doc 1329351 包含p型半導體’或其可由其他材料製造。事實上，源極 2〇及沒極18不需要由相同化合物製造。 參考展示有效區16中之一之截面圖的圖2簡單討論記憶 體裝置U)之運作。對於DRAM作用之基本方式之進一㈣ 論，頒予Seely等人之美國專利第3,731，287號更詳細地討 論了 DRAM,其全文以引用的方式併入本文。 如圖2所示，汲極18及源極2〇可包含自基板w相對平 矛面之大起。在一較佳實施例中，將源極2〇及汲極 18與基板U製造成整體且藉由㈣單體晶圓或基板而使其 牙；基板11之表面凸起，在另一配置中，使用熟習此項 技術者所熟知之技術藉由選擇性磊晶沈積來形成源 極突起。 在實施例中’ i少一部分數位線14b位於源極20之上 表面之上。如圖2所說明’源極2()經數位線插塞22電耗合 至數位線Ub(如所展^)，該插塞可於多㈣段或單一階段 =成同時，源極20經字線12a、12b與兩個汲極18分離。 12b^佳嵌埋於基板丨i中，其自表面向下延伸。 此认„十之電aB體通常稱作内嵌存取裝置或RAD ”及極η又 經=觸插塞28“合至儲存電容㈣且尤其心合至儲存 電夺益24之下電極26。在一較佳實施例中，儲存電容器24 ^ 3匕介電材料32與參考電極3q分離之下電極％。在此組 〜中此等堆登儲存電容器24以熟習此項技術者所熟知之 式作用如所說明，儘管溝槽電容器可用於其他配置， 但儲存電容器24較佳位於基板u之平面之上。 114280.doc ^29351 在一實施例中，每—儲存電容器24之-側形成-參考電 極3〇，而下電極26電耦合至相關汲極18。字線12a、I2b充 田其穿過之場效電晶體中之閘極，而數位線丨4b充當其電 搞合之源極之信號。因此，字線m較佳藉由容許或 防止數位線14b载運之信號（代表邏輯"〇"或邏輯"丨”）寫入儲 存電容11 24或自其讀出來控制至搞合至各汲極18之儲存電 容器24之存取。因此，連接至相關汲極18之兩個電容器24 中之各者可含有一位元之資料（即邏輯，，〇"或邏輯"丨"）。在 記憶體陣列中，選定之數位線與字線之組合可唯一識別應 寫入或§賣出資料之儲存電容器24。 接著返回圖1，可更詳細地討論記憶體裝置丨〇之設計及 幾何形狀。在圖1之右下角，描述了多個軸。此等軸大體 上與形成記憶體裝置1 〇之電路元件之縱軸對準，且經描述 更清晰地展示於各種電裝置與組件之間形成之角。軸A代 表有效區16之縱軸。各有效區16之汲極18及源極2〇較佳具 有可用以界定縱軸之大體上之線性關係。如所說明，所有 有效區16大體上平行。當然，應瞭解汲極18及源極2〇不需 要形成絕對之直線且實際上可由此等三點界定實質之角 度。因此，在一些實施例中，轴A可由兩個汲極18或由源 極20及僅一個汲極1 8或以熟習此項技術者清楚理解之多種 其他方式界定。在其他實施例中，有效區包含單―〉及極及 單一源極’其中軸A可由單一汲極與單一源極間之直線界 定。 軸B代表數位線14b之縱軸。在說明之實施例中，數位線 Π 4280.doc 1329351 14b形成大體上之直線。正如有效區16較佳係平行的，數 位線14a ' 14b亦較佳形成大體上平行之軸。因此，在一較 佳實施例中，至少在各記憶體單元區中每一有效區16之轴 A與數位線14之每一轴B形成類似之角度。 在圖1說明之一較佳實施例中，軸A與軸B之間形成銳 角。在說明之實施例中，軸A與軸B之間界定之此銳角^為 450 ° .有效區16相對於數位線14成角促進接觸插塞28之位置在 沒極18與相關儲存電容器24之間延伸。在一較佳實施例 中，由於此等接觸插塞28自汲極18之頂面延伸（圖2中所說 明），因此若數位線14不於汲極18頂部之上延伸，則工程 設計得以簡化。即使在數位線14大體上重疊且接觸相同有 效區16之源極20時，藉由使有效區16成角，可選擇數位線 14與汲極1 8之間之距離以促進汲極與接觸插塞之間之電子 接觸。 當然角Θ可具有多種值中之任何值，對其進行選擇以使 電裝置間距最大化。如熟習此項技術者所顯而易見，不同 角度將於相鄰有效區之間產生不同間距。在一實施例中， 角Θ較佳介於10〇與8〇。之間。在一更佳實施例中，角β介於 20與60。之間。在一更佳實施例中，角0係介於4〇〇與5〇。之 轉向圖3 -1 〇，其更詳細地說明一種製造記憶體裝置1 〇之 間距加倍字線12之方法。熟習此項技術者應易於瞭解，說 明之實施例之特定材料可以其他組群之材料個別替代或與 114280.doc 1329351 其組合。圖3說明半導體基板u，根據習知半導體處理技 術於其上形成在一較佳實施例中包含氧化物之薄臨時層 4〇。接著將諸如氮化矽之硬遮罩層42沈積於基板丨丨及臨時 層4〇上。硬遮罩層42可藉由尤其諸如濺鍍、化學氣相沈積 (CVD)或低溫沈積等任何熟知之沈積方法來形成。儘管在 較佳實施例中硬遮罩層42包含氮化石夕，但必須理解其亦可 由氧化矽（例如）或適用於下述選擇性蝕刻步驟之其他材料 形成。 接著，在圖中未說明之步驟中，使用於硬遮罩層42上形 成之光阻層將硬遮罩層42圖案化。可使用習知光微*影技術 將光阻層圖案化以形成遮罩，且接著可將硬遮罩層U經由 圖案化之光阻各向異性蝕刻以獲得複數個在y方向上延伸 之硬遮罩柱44(如圖4所界定），#中溝槽46將㈣管柱分 離。接著可以習知技術，諸如藉由使用基於氧之電漿移除 光阻層。 >考圖5 A在於硬遮罩層42中形成溝槽46後，可沈積間 隔材料之等形層以覆蓋記憶體裝置10之整個表面。較佳 也可參考基板11及臨時層40選擇性蝕刻間隔材料，且可 參考間隔材料分別選擇性㈣基板i i及臨時層4 q。在說明 之實施例中’ fB’隔材料包含多晶矽。可使用諸如CVD或物 理氣相沈積（PVD)之任何合適之沈積方法來沈積間隔材 料。 /在將間隔村料覆蓋於記憶體裝置10之垂直及水平表面上 y可乂疋向間隔钱刻使用各向異性钱刻冑先將㈤隔材料 114280.doc 16 1329351 自水平表面移除。因此，間 種材料之側壁延伸之材料。 槽46内形成且使其變窄。 隔材料形成間隔48，即自另一 如圖5所展示，間隔48係於溝
參考圖5B，接著可將第二硬遮罩層的沈積於記憶體裝置 狀整個表面上。較佳將在—較佳實施例中亦為氮化石夕之 此硬遮罩層49沈積至足以填充溝槽乜之厚度。當然，可藉 由已括CVD或PVD之多種合適沈積方法中之任何方法沈積 硬遮罩材料49。在沈積足夠量之硬遮罩材料倾，可藉由 熟習此項技術者所熟知之多種方法中之任何方法移除可能 於間隔48上及於先前沈積之硬遮罩42之其他部分上形成的 過量物。舉例而言，可將裝置1〇之表面平坦化至圖5b之虛 線水平，使得剩餘間隔48之側壁接近垂直。可使用諸如化 學機械研磨之任何合適之平坦化方法。
可使用多種方法中之任何方法去除目前曝露於記憶體裝 置10頂面之間隔48。在說明之實施例中，可使用相對於氮 化矽選擇性去除多晶矽之方法。舉例而言，在一實施例 中，可使用選擇性濕式蝕刻。藉由選擇性蝕刻臨時層4〇及 基板11之第二蝕刻進一步加深在蝕刻間隔48處形成之溝 槽。此等溝槽亦可較佳使用諸如離子研磨或反應性離子蝕 刻之定向方法形成。 圖6說明此等方法之結果’其中溝槽5〇形式之開口或凹 座經小於單獨使用光微影技術可能之最小間距分離。較佳 地’溝槽50在頂部具有約25 nm與75 nm之間之寬度。當 然’熟習此項技術者應瞭解可使用間距倍增之許多其他技 114280.doc 17 術達成圖6展示之階段。許多此等技術一般包括間隔處 理，藉此物理沈積可達成小於單獨光微影技術之間距❶溝 槽50通常亦具有大於1:1，且較佳大於2:1之縱橫比。深度 增加以難於填充合適材料為代價，使可用之體積最大化且 從而使字線之傳導率最大化。 在此等溝槽50形成後，藉由熟習此項技術者所熟知之多 種方法中之任何方法選擇性去除硬遮罩層Μ ◊在圖7中， 使閘極介電層54於裝置上毯覆式沈積或熱生長，從而將溝 槽之内表面加襯。在—較佳實施例中，所說明之閉極介 電層54包含以熱氧化作用形成之氧化矽，但在其他實施例 中八亦可為經沈積之高κ材料。接著亦可將在說明之實施 例中包含多晶矽之閘極材料層52毯覆式沈積於整個記憶體 裝置1〇上。在-實施例中，閘極層52完全填充溝槽5〇且形 成裝置1G之頂面。在―較佳實施例中，多晶♦為未經推雜 的〇 在界定電晶體沒極及源極之一系列摻雜步驟後，將溝槽 5 0中未經摻雜之多晶相姓直至閘極層5 2之頂部留在基板 頁面之下。此處理階段展示於圖8中。若經合適摻雜則 :8之内嵌多晶矽52可充當記憶體單元電晶體之字線及閘 較佳地陣列中之閘電極由比傳統多晶矽閉極具有 =導率之材料形成。其係歸因於内嵌開 ==電極更狹窄之事實。金屬材料完全或部分補 ㈣列中閉極之較小體積，從而改良沿字線之橫 114280.doc 由於2目此可將圓8之未經摻雜之多晶矽在内嵌後藉 ^上沈積金屬且反應切化物化。金屬石夕化物可具有 比經穆雜多晶料1G倍之傳導率且表現合適之功函數。 參考圖9_12,在另—配置中，最初將多㈣52㈣或向 下:坦化至閘極氧化物54 ’而非内嵌，從而在此階段無需 :飲而隔離溝槽50内之多晶石夕》使溝槽50内閑極層52之多 S自對準石夕化物化（salicidati〇n)反應以形成導電材 料層％。可將金屬層55(圖9)賴式沈積且退火步驟可在任 何金屬接财之處，諸如在多晶㈣極層以上形成石夕化 物材料56(圖12)。在一實施例中，矽化物化材料包含矽及 一或多種金屬，諸如鎢、鈦、釕、鈕、鈷或鎳。選擇性金 屬蝕刻移除過量金屬但不移除矽化物56。藉此金屬矽化物 5 6 成增加沿字線之橫向傳導率之自對準層。 較佳地，將閘極層52完全矽化物化以使橫向傳導率最大 化。完全反應亦確保矽化物向下形成至溝槽5〇之底部。在 說明之内嵌存取裝置（RAD)中，通道不僅延伸穿過閘極之 底部，而且亦沿閘極之側壁延伸。因此，不完全矽化物化 會導致沿RAD通道長度之不同功函數。此外，完全矽化物 化確保穿過陣列，在陣列間穿過晶圓及在晶圓間類似之閘 極功函數。然而，已發現於以單一金屬形成導電材料56在 所說明之溝槽50之緊密限制内難以達成完全矽化物化。例 如鎳或鈷傾向於在高縱橫比溝槽5〇内形成空隙。其他金屬 已表現出對於内嵌存取裝置之完全矽化物化之類似困難 性。熟習此項技術者應瞭解對於其他類型凹座内之材料完 114280.doc •19· 1329351 全矽化物化係具有挑戰的，諸 命如稞觸開口或通道，電容 器、電容器溝槽之堆疊容器形狀等等。 不希望束縛於理論，空隙形忐似伞及丄 • 丨承t成似子係由矽化物化反應過 ‘考呈中之擴散組合高縱橫比溝槽50之緊密限制所引起的。矽 於録中比銘於石夕中更容易擴散。因此，石夕傾向於在反應過 程中遷移’從而在溝槽50内留下空隙。此外，高溫相變退 火將矽化物自CoSi轉化為更穩定之c〇Si2。另一方面，鎳 • ㈣至矽中比矽擴散至鎳中更為容易，且因此亦具有在將
NiSi轉化為NiSh相之反應過程中產生空隙之趨勢。 因此，金屬層55較佳包含金屬混合物，其中混合物中至 少兩種金屬相對於矽具有相反擴散性。舉例而言，金屬層 55可包含鎳與鈷之混合物，使得擴散方向傾向於彼此平衡 且使空隙形成之危險降至最低。在此實例中，鈷較佳構成 少於50 at. %之混合金屬55，且更佳為混合物包含約70-90 at. %之Νι及約1 0-30 at. %之Co。已發現鎳與鈷之此混合物 _ 更容易達成閘極層之完全石夕化物化而無空隙形成，從而增 加沿字線之信號傳播速度。與部分矽化物化相比，完全經 矽化物化之字線不僅更具導電性，而且亦將確保沿通道長 度之一致功函數。由於部分矽化物化傾向於視局部溫度變 化等因素而定留下不一致之組合物，因此完全石夕化物化亦 表現出在裝置間穿過陣列，在陣列間或在晶圓間更佳之一 致性。 在一實例中，將包含80%之Ni及20%之Co之濺鍍標靶濺 鍍於多晶矽52上以產生金屬層55。接著使基板經歷矽化物 114280.doc -20- 1329351 化退火。儘管高溫（例如800〇C )退火歷經較短時間係可行 的’但退火較佳於較低溫度下執行歷經較長之時間。舉例 而言’將基板於400-60(TC下退火歷經25-35分鐘。在實驗 中’於5 00 C在環境下’於分批爐中執行石夕化物化退火 歷經3 0分鐘。 鑒於本文之揭示内容，熟習此項技術者可容易地選擇其 他合適的金屬混合物用於溝槽内之完全矽化物化。在矽内
比矽在金屬内更容易擴散之金屬之實例包括Ni、^及。 矽在其中比金屬在矽内更容易擴散之金屬之實例包括c〇、 Ti 及 Ta。 圖10A-11B為展示在以氧化矽加襯之5〇 nm寬之溝槽内内 嵌、το全矽化物化之NixCoySiz閘極材料的顯微照片。圖 10A及10B以兩種不同之放大率展示穿過雙溝槽寬度之截 面圖。圖11A及11B以兩種不同之放大率展示沿溝槽之一之 長度的截面圖。溝槽於頂部具有約5〇 nm之寬度及約i5〇 nm
之冰度，從而使得此等溝槽之縱橫比為約3:丨。觀察到光 α均之組合物’其填充溝槽之至少—下部部分而無空隙 形成。在圖U-12之實例中’在沈積多晶石夕52後（圖7)，可 將多晶♦僅回#至閘極介電頂面54, I而無需内嵌而隔離 溝槽内之石夕。 +現參考圖12,可將錢物化層％内敌於溝槽内且接著以 兮^化石夕之第—絕緣層58覆蓋。可將此等絕緣層W沈積 “钱刻或平坦化。藉此導電材料％形成完整記憶體裝 置1〇之字線…、12b，且字線Ua、12b經絕緣層58與其他 H4280.doc
•2N 1329351 電路元件分離。因此，熟習此項技術者應瞭解，字線丨之之 間距倍增且具有僅使用光微影技術可能之間距大約一半的 間距。然而應注意，無論字線之間距是否倍増，本文揭示 内容之特定態樣皆提供優點。 當然’在其他實施例中，可以熟習此項技術者所熟知之 多種方法中之任何方法進行間距倍增。 因此’說明之實施例之矽化物化層56填充溝槽5〇之下 部，較佳填充大於50%之溝槽高度，更佳填充大於75%之溝 槽咼度。在說明之實施例中，金屬矽化物56中約7〇 9〇 Μ % 之金屬為錄且金屬石夕化物中約丨〇_3 〇 at %之金屬為始。 如熟習此項技術者所瞭解，在一較佳實施例中，較佳隨 著以上特定步驟之完成同時界定周邊裝置之邏輯，藉此使 晶片製造方法更為有效。詳言之，界定内嵌字線之矽及金 屬沈積步驟較佳同時界定周邊裝置中CMOS電晶體基板上 之閘電極。 參考圖13-21，根據另一實施例，對於周邊裝置中陣列 及邏輯區内經同時處理之閘電極可確定不同之功函數及電 阻率。在說明之實施例中，此係藉由經形成周邊裝置中閘 極堆疊部分之多晶矽層蝕刻陣列RAD溝槽來促進。 參考圖13，在形成溝槽之前，可將多晶矽層6〇沈積於基 板11上。可首先將多晶矽層60沈積於薄介電質54a(例如生 長閘極氧化物）上。接著可以諸如參考圖3_6描述之間距加 倍遮罩（未圖示）將基板圖案化。亦形成蝕刻終止層6ι，在 說明之貫施例中其包含約1〇〇 2〇〇 A之以丁E〇s沈積之氧化 114280.doc -22- 1329351 物。 參考圖14，經由上覆蝕刻終止層61、多晶矽層6〇、下伏 介電質54a及基板11蝕刻溝槽5〇。接著可諸如藉由氧化溝 槽壁，於基板11之曝露部分上形成閘極介電質54b。如所 展示，由於預先存在之蝕刻終止層61，無顯著之其他氧化 物於多晶矽60之頂面上生長。 隨後，如圖15所展示，可將金屬材料62沈積於多晶矽 上且進入溝槽50中。如參考圖9_12所描述，較佳以 ^ 日日 矽更具導電性之材料填充溝槽5〇 ^在說明之實施例中，金 屬材料62包含氮化鈦（TiN) » 參考圖16，較佳將金屬材料62回蝕或平坦化以使導電材 料62之隔離線留在溝槽5〇中，於氧化物蝕刻終止層η上終 止（參見圖15)。在回蝕後，移除覆於多晶矽層6〇上之蝕刻 終止層61(例如對蝕刻終止層61之較佳氧化物材料使用 浸潰）’而溝槽50内之介電層54b受到金屬材料62保護。隨 後，將金屬層64、66沈積於矽層60上。如熟習此項技術者 所瞭解第"電層54a、多晶石夕層60及上覆金屬層64、 66可充當周邊裝置之電晶體閘極堆疊。所有此等層同時沈 積於所關注之兩個區域（在記憶體之實例中，於周邊裝置 及記憶體陣列區）中。多晶矽可經不同摻雜以確定所要的 電晶體功函數，從而使得可使用單一材料沈積及不同摻雜 步驟界定CMOS電路iNMOS&PM〇s之閘極。上覆金屬層 66可用以改良沿控制閘極之線的橫向信號傳播速度，且在 說明之實施例中包含鎢（w)<>介入金屬層64可確保多晶矽 114280.doc -23 - 層60鱼卜灣入府 ^ 復孟屬層66之間接合點處之物理及電學相容性 (例如執灯黏著及障壁功能）’且在說明之實施例中包含氮 化鈦且更詳言為富集金屬之金屬氮化物。 /、考圖17，閘極堆疊亦包括在說明之實施例中由氮化矽 " 现層68。圖1 7展示在基板之第一或記憶體陣列區 70中以金屬材料62填充之溝槽5〇。閘極堆疊層、⑼、 ^66及68延伸穿過基板之陣列區70及第二或周邊裝置或 邏輯區72。配置光阻遮罩76用於將周邊裝置72中之電晶體 閘極圖案化。 如圖18所展示，一系列蝕刻步驟首先經由頂蓋層68進行 蝕刻，其包括金屬蝕刻用以移除金屬層64、66。基於氯之 反應性離子蝕刻（RIE)例如可選擇性移除典型之金屬材 料，諸如所說明之鎢短接層66及介入金屬氮化物層Μ，而 在下伏多晶矽層60上終止。如所展示，高選擇度使得在多 晶矽60曝露後繼續金屬蝕刻直至金屬材料62内嵌於溝槽π 中。 Η 見 > 考圖19，在將金屬閘極材料6 2内嵌於陣列溝槽中後 可轉換蝕刻化學，且可使用相同之遮罩76將矽6〇圖案化， 從而完成周邊裝置72之閘極堆疊80之圖案化。 現參考圖20，在移除遮罩後，將間隔層84沈積於基板 上，等形塗覆閘極堆疊80但填充陣列溝槽50頂部之凹座。 在說明之實施例中，間隔層84包含氮化矽，但熟習此項技 術者應瞭解可使用多種不同之絕緣材料。 如圖21所展示，隨後之間隔蝕刻（定向蝕刻）沿閉極堆疊 114280.doc -24- 1329351 8〇之側壁留下侧壁間隔86 ’從而容許源極及極區之自對 準摻雜。然而在陣列72中，因為溝槽頂部之淺凹座經間隔 層84真充（參見圖20)，所以間隔蝕刻在陣列72中僅回蝕間 ' ⑯材料’從而留下絕緣頂蓋層以將閘極材料62掩埋於溝槽 50中。 熟習此項技術者應瞭解，為簡明起見本文描述中省略了 包括源極/汲極、通道增強、閘電極、輕微摻雜汲極仏〇1)) • 及鹵素摻雜之CMOS電晶體之各種摻雜步驟。 因此，圖13-21之實施例促進陣列與周邊裝置中電晶體 之同時處理。在說明之實施例中，陣列電晶體為内嵌存取 裝置（RAD)，而周邊閘極如習知平坦M〇s電晶體形成於基 板11之上。儘管在周邊裝置中習知CMOS電路之情形下進 行描述，但熟習此項技術者應瞭解周邊電晶體可呈其他形 式。有利的為在說明之實施例中’可在將周邊閘極堆疊圖 案化之同時内嵌RAD溝槽中之金屬層。此外，周邊側壁間 春隔與RAD閘極或字線上之絕緣頂蓋同時形成。 儘管未展示，但應瞭解可使用習知之DRAM製造技術來 製造圖2中展示之其他電路元件。舉例而言，可使用不同 之摻雜量形成圖2之汲極1 8及源極20，且可根據複數個沈 積及遮罩步驟形成堆疊儲存電容器24。 作為裝置佈置及其製造方法之結果，圖1及2所展示之完 整記憶體裝置1 〇與習知DRAM相比具有許多優點。舉例而 言’各記憶體單元之尺寸及記憶體裝置1〇之總尺寸可大體 上降低而無相應的相鄰感應放大器之間距離的實質降低。 H4280.doc -25- 1329351 字線12及數位線14可具有大體上不同之間距， t不同之間距，此使
空間的間隔（如可易於自圖2所見）^因此， 10製造得更為緻密。 可將記憶體裝置 用盡閘極與有效區之源極或汲極之間之有價值 此外，金屬混合物之使用促進掩埋於溝槽5〇内之矽的究 全矽化物化，而不形成有害空隙。因此，對於相對較小體 積之字線而言可達成較高傳導率。 儘管已描述本發明之特定實㈣卜但此等實施例僅以實 例之方式呈現，且不意欲限制本發明之範疇。實際上，本 文福述之新穎方法及裝置可以多種其他形式體現，，此外， 在不偏離本發明之精神之狀況下，可進行本文描述之方法 及裝置形式的各種省略、替代及改變°所附中請專利範圍 及其等效物意欲涵蓋本發明範疇及精神内之此等形式戋修 正。 > 【圖式簡單說明】 圖1為根據本發明之一較佳實施例佈置之記憶體裝置 平面示意圖。 、 圖2為根據本發明之一較佳實施例，沿線22獲取之圖1 4280.doc •26· 1329351 之§己憶體裝置的側截面示意圖。 圖3_7為根據本發明之一較佳實施例之半導體裝置之一 部分的—系列截面圖，其說明類似於圖1及2之DRAM存取 電晶體的形成。 圖8為根據本發明之一實施例，在將矽内嵌於溝槽内後 且在沈積用於矽化物化之金屬前，圖7之裝置之截面示意 圖。 圖9為根據本發明之另一實施例，在將溝槽内之矽平坦 化及沈積用於矽化物化之金屬後，圖7之裝置之截面示意 圖。 圖10A-11B為說明在圖9之裝置上執行矽化物化退火後， δ己憶體存取裝置之完全石夕化物化内嵌閘極之顯微照片。 圖12為展示在將完全矽化物化閘極内嵌及掩埋於其溝槽 内後，圖10Α-11Β之部分製成之半導體裝置之截面示意 圖。 圖1 3-2 1為根據本發明之另一實施例之半導體裝置之一 部分的一系列截面圖，其說明陣列中（類似於圖之）周 邊電晶體閘極堆疊與内嵌存取裝置之同時形成。 【主要元件符號說明】 10 記憶體裝置 11 基板 12a 字線 12b 字線 12c 字線 114280.doc -27- 1329351
12d 字線 14a 數位線 14b 數位線 16 有效區 18 汲極 20 源極 22 數位線插塞 24 儲存電容器 26 下電極 28 接觸插塞 30 參考電極 32 介電材料 40 臨時層 42 硬遮罩層 44 硬遮罩柱 46 溝槽 48 間隔 49 第二硬遮罩層 50 溝槽 52 間極層 54 閘極介電層 54a 介電質 54b 介電質 55 金屬層 114280.doc -28- 1329351
56 矽化物 58 絕緣層 60 多晶矽層 61 钱刻終止層 62 金屬材料 64 金屬層 66 金屬層 68 頂蓋層 70 陣列區 72 邏輯區 76 光阻遮罩 80 閘極堆疊 84 間隔層 86 側壁間隔 88 絕緣覆蓋層 114280.doc -29-

Claims (1)

1329351 第095132096號專利申請案 中文申請專利範圍替換本(99年3月） 十、申請專利範圍： 1 · 一種於一積體電路中形成—金屬矽化物結構之方法，咳 方法包含： 於一部分製成之積體電路中提供一凹座； ' 將矽沈積於該凹座中； 將金屬混合物沈積於該凹座上且與該矽接觸，該金屬混 合物包含至少兩項相對於矽具有相反擴散性之金屬；及 φ 使該金屬混合物與該矽於該凹座内反應以於該凹座内 形成金屬矽化物， 其中该金屬混合物包含70-90原子％ (at.%)之錄及1〇_3〇 at·%之鈷’且其中該凹座具有一大於2」之縱橫比。 2 ·如請求項丨之方法，其中反應包含完全消耗該凹座内之 該矽。 3.如請求項}之方法，其中反應包含於約4〇〇。〇與6〇〇。(：之間 之溫度下將該基板退火。 • 4.如請求項3之方法，其中退火包含將該部分製成之積體 電路曝露於一分批爐中之氮環境。 5·如請求項1之方法，其進一步包含在沈積該金屬混合物 之别將該石夕内喪於該凹座内。 6. 如請求項1之方法，其進一步包含在沈積矽之前於該凹 座内之表面上形成一薄介電層。 7. 如請求項6之方法，其中該四座界定用於一記憶體陣列 之一内嵌存取裝置。 8 ·如吻求項7之方法，其中該凹座為界定該記憶體陣列之 114280-990324.doc U29351 一字線之一伸長溝槽。 9 ·如請求項8 $古、也 ^ 喟S之方法，其中該凹座於該溝 25_與75_之間之寬度。 以曰之頂部具有約 1〇.如請求項7之方法，其中該内嵌存取裝置 同源極區之-對内嵌存取裝置中之—者。^、用〜、 U.如請求们之方法，其進一步包含在沈積 之前回蚀該經沈積之石夕至該凹座之頂面。乂…合物 12·::求項丨之方法’其中提供該凹座 倍遮罩方法。 ]間距加 3.種形成用於一積體電路之一内嵌存取# 方法包含： 円t存取裝置之方法，該 於—半導體結構中蝕刻一溝槽； 將該溝槽以一介電層加襯； 以矽至少部分填充該經加 而不填充； ㈤曰且留下一剩餘容積 將:金屬層沈積於該溝槽上且與該石夕接觸； 使該於該溝槽内之矽在石夕化 全反應，·及 久愿甲興S金屬層完 以—絕緣材料填充該溝槽之剩餘容積。 如請求項13之方法，苴 、 1 /、中6亥金屬混合物包含第一金屬， 二金屬，盆擴散至= 屬中更為容易；及第 難。 ’、 矽擴散至該第二金屬中更為困 A如請求項14之方法，其中該第-金屬係選自由錦、麵及 114280-990324.doc -2- 1329351 銅組成之群。 16.如請求項14之方法，其中該第二金屬係選自由鈷、鈦及 钽組成之群。 17·如請求項13之方法，其中以矽至少部分填充該溝槽包含 回蝕該矽直至其内嵌於界定該溝槽之該結構之頂面下的 該溝槽内。 1 8.如請求項13之方法，其中該金屬層包含一鎳與鈷之混合 物。 1 9.如請求項18之方法，其中該混合物包含少於5 0 at.。/〇之 姑。 2〇.如請求項19之方法，其中該混合物包含70至90 at.%之鎳 及10至30 at.%之鈷。 21.如請求項18之方法，其中沈積該金屬層包含濺鍍包含鎳 與鈷之固定組合物之標靶。 22· —種積體電路’其包括一金屬矽化物結構，該結構包 含： 無空隙填充一凹座之一下部部分之一金屬石夕化物，該 金屬矽化物包含一至少一第一金屬與第二金屬之混合 物’該第一金屬於矽中之擴散性高於矽於該第一金屬中 之擴散性，該第二金屬於矽中之擴散性低於矽於該第二 金屬中之擴散性；及 一在該金屬矽化物上且與該金屬矽化物實體接觸之絕 緣材料’該絕緣材料用以填充該凹座之一上部部分。 23.如請求項22之積體電路，其中該凹座包含於一半導體基 )14280-990324.doc 1329351 板内形成之一溝槽。 24. 如請求項23之積體電路，其中該溝槽係以一薄介電層加 襯，且該金屬矽化物包含用於一記憶體陣列之一字線。 25. 如請求項22之積體電路，其中該凹座界定大於約之縱 橫比。 26. 如請求項22之積體電路，其中該凹座界定一具有介於約 25 nm與75 nm之間之寬度的開口。 27_如請求項22之積體l, j. V. . 貝組包路，其中s亥金屬矽化物包含鎳與 钻。 28. 如請求項27之積體雷攸 甘λ与τ人p , 书路，其中該金屬石夕化物中約70-90 at·%之金屬包含鎳。 29. 如請求項28之積體曹％ Λ„ 貝瓶包路，其中該金屬矽化物中約10-30 at.%之金屬包含姑。 30. 如請求項22之積體電路，其中該第一金層係選自由錄、 錄及銅組成之群，且該第二金屬係選自㈣、鈦及组組 成之群。 31. 一種記憶體裝置，其包含於一記憶體陣列中之一内嵌存 取裝置’該記憶體裝置包含： 在一半導體基板之半導體材料内之一凹座，該半導體 材料具有一上升之最外表面； 一加襯該凹座之電晶體閘極介電層；及 一包含接收在該凹座之一下部部分中金屬矽化物之傳 導電晶體閘極材料，兮·公厘r<WI_此θ > °茨金屬石夕化物具有一在接收該凹座 之該半導體材料中兮· μ在4 士 上升之农外表面朝内上升的上升之 114280-990324.doc 1329351 最外表面，該金屬矽化物包含至少二金屬，一在該凹座 之一上部部分中接收之絕緣材料，該絕緣材料上升至該 金屬矽化物上且橫跨該金屬矽化物之該上升之最外表面 與該金屬矽化物實體接觸。 ' 32.如請求項3 1之記憶體裝置，其中該至少二金屬相對於石夕 具有相反擴散性。 3 3 ·如請求項3 1之記憶體裝置，其中該金屬矽化物包含選自 鲁由鎳、鉑及銅組成之群之第一金屬，及選自由鈷、鈦及 钽組成之群之第二金屬。 34.如請求項3 1之記憶體裝置，其中該内嵌存取裝置與一相 鄰之内嵌存取裝置共用一源極。 3 5.如請求項3 1之記憶體裝置，其中該凹座界定一具有約25 nm與75 nm之間之寬度的開口。 36.如請求項31之記憶體裝置，其中該金屬矽化物中約7〇_9〇 at·%之金屬包含錄。 • 37.如請求項36之記憶體裝置，其中該金屬矽化物中約1〇_3〇 at·%之金屬包含|古。 114280-990324.doc
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SG165335A1 (en) 2010-10-28
US7557032B2 (en) 2009-07-07
WO2007030343A3 (en) 2007-06-14
CN101297392B (zh) 2011-05-11
KR20080039541A (ko) 2008-05-07
EP1929510A2 (en) 2008-06-11
SG165336A1 (en) 2010-10-28
CN101297392A (zh) 2008-10-29
US9076888B2 (en) 2015-07-07
US20070105357A1 (en) 2007-05-10
WO2007030343A2 (en) 2007-03-15
KR100984469B1 (ko) 2010-09-30
TW200721391A (en) 2007-06-01
JP4984177B2 (ja) 2012-07-25
US7977236B2 (en) 2011-07-12
US20070049015A1 (en) 2007-03-01
US20090239366A1 (en) 2009-09-24
JP2009507372A (ja) 2009-02-19
SG10201400297PA (en) 2014-06-27

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