TW201117358A - Electronic device and fabrication method thereof and memory device - Google Patents

Abstract

The embodiment provides an electronic device and fabrication method thereof and a memory device. The electronic device includes a substrate. A trench is formed in the substrate. A diffusion region formed in a portion of the substrate adjacent the trench. A conductive structure is disposed in the trench. The conductive structure includes a conductive layer having a recess covers a bottom of the trench. The diffusion region is exposed from the recess. A conductive plug fills the recess, covering sidewalls of the diffusion region. A barrier layer is disposed between the conductive plug and the conductive layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device and a method of fabricating the same, and more particularly to a bit line for a dynamic random access s memory cell and a method of fabricating the same. [Prior Art] Dynamic Random Access Memory (DRAM) belongs to a kind of volatile memory (v〇latile memory). The main principle of operation is to use the amount of charge stored in the capacitor to represent a binary bit. (bit) is 1 or 〇 to store data. To achieve high density requirements, the most effective method at present is to reduce the size of the wafer by reducing the manufacturing process and using cell design techniques. Another way to reduce the size of the wafer is to implement a more efficient array architecture. After several generations of development, the storage technology usually becomes a certain unit layout limitation. Every improvement of the unit requires a lot of work to reduce it. = small size. Therefore, there is a need for a dynamic random access memory having a new structure and a method of fabricating the same. In view of the above, an embodiment of the present invention provides an electronic swearing device, including a substrate; a groove formed in the substrate; a & a moon expansion region formed adjacent to the groove a portion of the sidewall of the substrate; - an electrical structure disposed in the trench, including a conductive layer covering the bottom surface of the trench, 9095-A34433TWF 4 201117358, the conductive layer having a recess to allow the diffusion region to be The recess is exposed; a conductive plug is filled in the recess and covers a sidewall of the diffusion region, wherein a barrier layer is disposed between the conductive plug and the conductive layer. Another embodiment of the present invention provides a memory device including a substrate; at least one vertical transistor formed in the substrate and having a vertical sidewall; at least one word line formed along the first direction In the substrate, the word line is disposed on the vertical sidewall of the pair of vertical transistors; at least one bit line is formed in at least one trench in the substrate along a second direction Φ different from the first direction. And being located below the pair of vertical transistors, and electrically contacting a non-polar region of the vertical transistor by a diffusion region formed in a portion of the substrate adjacent to the sidewall of the trench, wherein the bit line includes a bit line a conductive layer covering a bottom surface of the trench, the conductive layer having a recess to expose the diffusion region from the recess; a conductive plug filling the recess and covering a sidewall of the diffusion region, wherein the conductive plug A barrier layer is disposed between the plug and the conductive layer. Still another embodiment of the present invention provides a method of manufacturing an electronic device, including: providing a substrate; forming a trench in the substrate; forming a conductive layer in the trench to cover a bottom surface and a portion of the trench a conductive layer having a recess adjacent to the sidewall of the trench; a diffusion region formed in the substrate adjacent to the recess; a barrier layer formed in the trench to cover the conductive layer; A conductive plug is formed in the groove to fill the recess and cover the sidewall of the diffusion region. [Embodiment] The following is a detailed description of each embodiment and a description of the example 9095-A34433TWF 5 201117358, which is a reference for the present invention. In the drawings or the description of the specification, the same drawing numbers are used for the similar or identical parts. Also, in the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention. Fig. 1 is a perspective view showing an electronic device 600 according to an embodiment of the present invention. In an embodiment of the invention, the electronic device 600 can be, for example, a memory device, in particular, a dynamic random access memory crystal with a cell size of 4F2 (where F is the minimum lithography process size, or cell size). DRAM cell 600. As shown in FIG. 1, a vertical transistor 300 of the above-described dynamic random access memory cell 600, for example, a conductive structure 500 of a bit line (BL) 500, and a word line (word line, WL) 308 are all disposed in a substrate 200. As shown in FIG. 1, the electronic device 600 includes a substrate 200. A vertical transistor 300 is formed in the substrate 200. The vertical transistor 300 has a vertically stacked lower layer drain region 314, an intermediate layer channel region 316, and an upper layer source region 318. Additionally, vertical transistor 300 has at least one vertical sidewall 302. A word line 308 is formed in the substrate 200 along a first direction 322, wherein the word line 308 is disposed on the vertical sidewall 302 of the vertical transistor 300 and serves as a gate of the vertical transistor 300. An insulating layer 306 is disposed between the word line 308 and the vertical transistor 300 as a gate insulating layer of the vertical transistor 300. As shown in FIG. 1 , the electronic device 600 further includes a bit line 500 formed in a trench 202 in the substrate 200 along a second direction 320 different from the first direction 322 and located at a vertical voltage 9095-A34433TWF. 6 201117358 'Under the crystal 300, and electrically contacting the drain region 314 of the pair of vertical transistors 300 by a diffusion region 230 formed in a portion of the substrate 200 adjacent to the sidewall of the trench 202. In addition, the electronic device 600 further includes a capacitor 312 electrically contacting the source region 318 of the vertical transistor 300. 2a to 2e are cross-sectional views taken along line A-A' of Fig. 1 showing conductive structures 500a to 500e of, for example, bit lines of an electronic device according to various embodiments of the present invention (also referred to as bit lines 500a~). Sectional view of 500e). Further, the 2a to 2e diagrams further show the diffusion regions 230 adjacent to the bit lines 500a to 500e. As shown in FIG. 2a, the bit line 500a according to an embodiment of the present invention includes a conductive layer 214 covering the bottom surface of the trench 202. The conductive layer 214 has a recess 247 to expose the diffusion region 230 from the recess 247. A conductive plug 220a is filled in the recess 247 and covers the sidewall of the diffusion region 230. A barrier layer 218 is disposed between the conductive plug 220a and the conductive layer 214. The conductive plug 220a is made of tungsten. As shown in FIG. 2b, the bit line 500b of another embodiment of the present invention differs from the bit line 500a in that the bit line 500b further includes a germanide layer 232 formed in the trench 202. The insulating mat layer 208 covers the sidewalls and is adjacent to the diffusion region 230. As shown in FIG. 2c, in another embodiment of the present invention, the bit line 500c is different from the bit line 500a. The bit line 500c further includes a diffusion source layer 228 and a sidewall formed on the diffusion source layer 228. A germanide layer 232 is formed, wherein the diffusion source layer 228 is formed on sidewalls of the trench 202 that are not covered by the insulating pad layer 208 and between the germanide layer 232 and the diffusion region 230. As shown in Fig. 2d, the bit line 500d of still another embodiment of the present invention differs from the bit line 500a in that the material of the conductive plug 220a of the bit line 500d is polysilicon. As shown in FIG. 2e, in another embodiment of the present invention, the bit line 500e is different from the bit 9095-A34433TWF 7 201117358 line 500a. The conductive plug 220a of the bit line 500d is made of polysilicon. The bit line 500b further includes a germanide layer 232 formed on the sidewall of the trench 202 not covered by the insulating germanium layer 208 and adjacent to the diffusion region 230. 3 to 10 are schematic cross-sectional views showing a method of manufacturing the conductive structure 500a of the electronic device 600 according to an embodiment of the present invention shown in FIG. 2a, which particularly shows a bit line 500a of the dynamic random access memory cell. Manufacturing method. As shown in FIG. 3, first, a substrate 200 is provided. In an embodiment of the invention, the substrate 200 may be a stone substrate. In other embodiments, a germanium telluride (SiGe), a bulk semiconductor 'strained semiconductor, a compound semiconductor, a silicorl on insulator (SOI), Or other commonly used semiconductor substrates are used as the substrate 2〇〇. The substrate 200 can be implanted with a p-type or n-type dopant to change its conductivity type for design needs. In an embodiment of the invention, the substrate 2 can be implanted with a p-type dopant. Then, a patterned hard mask layer 201' can be formed on the substrate 2'' and a formation position of the trench 202 can be defined by a deposition and patterning process. In a consistent embodiment of the present invention, the patterned hard mask layer 201 may include a stacked structure formed of a lower layer of a hafnium oxide underlayer 201a and an upper layer of a tantalum nitride layer 2? Then, using the patterned hard mask layer 2〇1 as an etch hard mask layer, an anisotropic etching process is performed to remove the portion not covered by the patterned hard mask layer 201. The substrate 2 is formed to form a trench 202 in the substrate 200. After that, for example, chemical vapor deposition (CVD), low pressure chemistry can be utilized.

9095-A34433TWF 201117358 Method or high temperature oxidation (10) rigid method and other deposition edge layer. In the case of forming a ruthenium-palladium from 6 and the bottom surface of the present invention, the insulating underlayer 208 may comprise a deuterated layer, a nitride layer or a layer of tantalum which may be tetraethyl and an acid salt. In the example, insulating germanium, TEOS oxide. Receiver' Please refer to Figure 4, which can be formed in the stripping field _ in the barrier layer 212 and covered with /. In the present invention-embodiment, the barrier layer 212 can be combined with nitrogen and nitrogen. In the present embodiment, the barrier layer 212 may be a laminated structure. Then, the conductive material 211 can be formed by chemical vapor deposition in a static manner and filled into the trenches 202. In the present invention, a sound price is a metal such as ruthenium. After the conductive material is included in the example, please refer to the μ @ 4s » λ diagram, which can be made by etching back 211, 〇〇, upper and part of the conductive material in the trench 202, material The top surface of 21-1 is lower than the surface of the substrate 2〇〇. "The borrower ^ ° month refers to the 6th 51' can use the atomic layer deposition method (ALD) lit: the formation of the -dielectric layer 240 in the trench 2〇2, and covering the conductive material 211. _ 7ΛΠ In an embodiment of the invention, the first dielectric layer is formed by a second layer or a nitride layer. In this embodiment, the first dielectric screen 24f) lining the sidewall of the trench 202 is (4)_k) dielectric/ (Ancient person ^ is, for example, a high dielectric constant of constant density (Al2〇3). The constant of 42^^ means that the dielectric constant is greater than that of the dioxide, and the subsequent use of the gas phase 拎...which has a better density. Therefore, Doping can be formed in the middle;:: the substrate adjacent to the side wall of the Hankou 202 part avoids diffusion of dopant gas into other unwanted

9095-A34433TWF 201117358, the product domain and can facilitate the subsequent etching process as a residual hard mask without damaging the second conductive material 2U. In the present invention-embodiment, after the formation of the electrical layer 240, an annealing process may be performed to make the first dielectric: "more dense". Then, chemical vapor deposition (CM) may be utilized. Depositing a t-type, conforming to the trench 202 to form a second dielectric layer 八, covering the first dielectric layer 240. In the present invention - an embodiment, the second 丨 electrically layer 242 and the first dielectric The layer is said to be a different material, and the second dielectric layer is, for example, an undoped amorphous stone eve (und 〇 汹 汹 训 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ==) An ion implantation step is performed on the second dielectric layer 242 - not shown in the figure, because of the ion implantation step 262, the direction of the arrow 262, and the surface of the substrate 2 Having a Ί2 is determined by the formation position of the subsequent diffusion zone or may be between (10) and the formation position of the above diffusion zone or J = between the divisions CeSi_ati〇n). Therefore, the second dielectric is subtracted from the component. 242 forming a doped region 242a and a non-defective 262 can be implemented in the present invention, the ion implantation step is performed in the secret region. The boron (BF2) dopant can be For difluoride, please refer to Figure 8, to close the process, remove part of the doped region 242aV 242 to wet a portion of the first dielectric layer 24 。. In the wet, your miscellaneous region 242b, straight As shown in Fig. 7, during the process of the doping region, there is no non-doped region of the holding, and the ratio of the two is lower than the ratio, so when the undoped region 242b is completely The doped region 242a is selected by the impurity 2 (four).

9095-A34433TWF 201117358 Then, the residual tooth can be replaced by a wide-area pool such as dry (4) as a side hard mask layer, and the covered first-dielectric layer 24 engraving process 'removes the undoped area' - In the embodiment, the ridge 2 forms a hard mask structure 243. In the first dielectric layer 24G of the present invention, the doped region formed by the non-electric layer 242 is etched with v Η materials, for example, 筮 氧化 氧化 摩 摩 , , , , , , , , , , , 240 240 240 The appropriate _agent' is such that the first dielectric layer has a surname (having a good _ selection (four).

Thereafter, a hard mask structure 243 is formed which is an isotropically etched portion of the conductive material 211. In the Ming, one "f 〇 246' and exposed or size. After the _% position of the zoning area, 'reuse the hard mask structure 243 as a hard mask layer, for example dry (four) - non The isotropic process removes a portion of the conductive material 211 and the barrier layer 212 exposed from the opening to form a conductive layer 214 having a quadrant 247. The conductive layer 214 having the recess 247 may define a diffusion region in a subsequent process. The formation position of 230. Next, the hard mask structure 243 and the conductive layer 214 are used as an etching hard mask layer to perform an isotropic etching process such as wet etching, and a portion of the insulating pad layer 208 exposed from the recess 247 is removed. In order to expose a portion of the sidewall 226 of the trench 2 〇 2, in an embodiment of the invention, since the hard mask structure 243, the conductive layer 214 and the insulating pad layer 208 are respectively made of different materials, for example, the hard mask structure 243 The laminated structure 'the conductive layer 214 which is composed of oxidized (Al 2 〇 3) and polycrystalline hair is a metal such as a crane', and the insulating click 208 is an oxide. Therefore, an appropriate etchant may be selected to make the insulating underlayer 208 For 9095-A34433TWF 11 201117358 has a harder The mask structure 243 and the conductive layer 214 have a high etch rate (having a good etch selectivity). After the isotropic etch process, portions of the sidewalls 226 of the trenches 210 are exposed. Then, a portion of the substrate 200 adjacent the recesses 247. A diffusion region 230 is formed in the gas phase doping manner, and the dopant gas is injected into the adjacent portion of the substrate 200 from the exposed sidewall 226 of the trench 202 to form the diffusion region 230. In an embodiment of the invention, the gas phase doping method may include high temperature rapid gas phase doping (RvD), room temperature gas phase doping, gas immersion laser doping (GILd), etc. In the present invention In the embodiment, the diffusion region 230 can be used as a diffusion junction of the bit line and the drain of the vertical transistor. In the embodiment in which the conductivity type of the substrate 2 is p-type, the diffusion region 230 The conductivity type may be n. The conductivity type of the diffusion region 23〇 depends on the conductivity type of the gas dopant, but is not limited to the embodiment. In an embodiment of the invention, the hard mask structure 243 is, for example, oxidized. First dielectric layer 24 of aluminum (α 〇 2 〇 3) And the conductive layer 214 can be used as a barrier layer for gas phase doping, preventing the dopant gas from diffusing into the substrate 200 from the sidewalls of the first dielectric layer 240 and the trench 2 〇 2 covered by the conductive layer 214. The area affects the performance of the bit line. Then, referring to Fig. 9, the hard mask structure 243 as shown in Fig. 8 can be removed by wet etching. Then, a pre-cleaning step (pre-clean) can be performed. 'To remove, for example, a native oxide on the sidewall 226 of the trench 2〇2. Thereafter, a barrier layer 218 can be formed in the trench 202 by atomic layer deposition (ALD), and the sidewalls of the insulating pad layer 208, the conductive layer 214, and the diffusion region 23A can be covered. In an embodiment of the invention, the barrier layer 218 may comprise titanium, titanium nitride or a group thereof

9095-A34433TWF 12 201117358 合. In the present embodiment, the barrier layer 218 may be a stacked structure composed of titanium and titanium nitride. Then, a conductive material 220 can be formed in a comprehensive manner by a chemical vapor deposition (CVD) deposition method, and the trench 202 can be filled. In the present embodiment, the conductive material 220 may include a metal such as tungsten. As shown in FIG. 9, the conductive material 220 fills the recess 247 and covers the sidewall of the diffusion region 230. Thereafter, referring to FIG. 10, the conductive material 220 above the substrate 200 and partially located in the trench 202 may be removed by an etching back process to form the conductive plug 220a, wherein the top surface of the conductive plug 220a φ is lower than the surface of the substrate 200. Thereafter, a capping layer 258 may be formed in the trench 202 by, for example, chemical vapor deposition (CVD) and subsequent etching, for example, an etching back process, and the conductive plug 220a may be covered. In an embodiment of the invention, the material of the cover layer 258 may be, for example, an insulating material of cerium oxide. Then, through a subsequent planarization process such as chemical mechanical polishing (CMP), the conductive structure 500a of an embodiment of the present invention as shown in FIG. 2a is formed, and the conductive structure of an embodiment of the present invention as shown in FIG. 2a is formed. 5〇〇a, • A plurality of hard mask structures having etching options different from each other are formed in the trenches 202 by self-aligned to form a conductive layer 214 having recesses 247. The formation position of the diffusion region 23A is defined by a subsequent etching process. Moreover, the diffusion region 230 is directly electrically contacted to the conductive plug by a barrier layer such as a metal material, and the interface factor can be prevented from affecting the conductive property of the bit line. In addition, the hard mask structure may include, for example, a high dielectric constant dielectric-dielectric layer 240 that oxidizes i2〇3), which has a better density and thus can be used as a vapor phase rubbing process for forming a diffusion region. The barrier layer prevents the dopant gas from diffusing into the sidewall of the trench 2Q2 covered by the first dielectric layer

9095-A34433TWF 13 201117358 Entering an unwanted area in the substrate 200 affects the performance of the bit line. 11 is a cross-sectional view showing a method of fabricating the conductive structure 500b of the electronic device 600 according to another embodiment of the present invention as shown in FIG. 2b, which differs from the conductive structure 500a in that the conductive structure 500b further includes a covered diffusion region. For the vaporization layer 232 of the side wall of the 230, if the components in the above-mentioned drawings have the same or similar parts as those shown in the first to the tenth, the above description can be referred to, and the description thereof will not be repeated. Referring to FIG. 11 , after the diffusion region 230 is formed and the hard mask structure 243 as shown in FIG. 8 is removed, a deuteration process is performed to form a germanide layer 232 on the sidewall 226 of the trench 202 and covered. The sidewall of the diffusion region 230. In an embodiment of the invention, the germanide layer 232 may comprise a titanium germanide or a cobalt germanide for reducing the electrical resistance between the diffusion region 230 and the subsequently formed conductive plug 220a. Further, a subsequent planarization process such as chemical mechanical polishing (CMP) is performed to form the conductive structure 500b of an embodiment of the present invention as shown in Fig. 2b. 12 to 13 are schematic cross-sectional views showing a method of fabricating the conductive structure 500c of the electronic device 600 according to still another embodiment of the present invention as shown in Fig. 2c, the difference from the conductive structure 500a being the diffusion of the conductive structure 500c. The region 230 is formed by diffusion diffusion of the diffusion source layer 228 formed on the exposed sidewall 226 of the trench 202. If each element in the above figure has the same or similar portion as shown in FIGS. 1 to 11, Please refer to the previous related description, and no repeated explanation is given here. Referring to Fig. 12, a portion of the insulating underlayer 208 exposed from the recess 247 may be removed after exposing a portion of the sidewall 226 of the trench 202 as illustrated in FIG. A diffusion source layer 228 is formed on the sidewalls 226 of the 9095-A34433TWT 14 201117358 exposed by the trench 202 by a thin film deposition method such as chemical vapor deposition (CVD) and a subsequent etch back step, and removed by the second dielectric layer The electric layer is doped into a doped region 242a. In an embodiment of the invention, the diffusion source layer 228 may be a conductive layer doped with a polysilicon layer, such as an arsenic doped poly layer (As-doped poly). Then, the dopant of the diffusion source layer 228 can be diffused into the adjacent substrate 2 by, for example, an annealing process to form a diffusion region 23 in a portion of the substrate 2A adjacent to the diffusion source layer 228. Then, please refer to Fig. 13, and the first dielectric layer 24〇 as shown in Fig. 12 can be removed by wet etching. Thereafter, a deuteration process can be performed to form a lithiation layer 232 in the trench 202 and to cover the side walls of the diffusion source layer. In an embodiment of the invention, the lithium layer 232 may comprise a titanium alloy or an enamel compound for reducing the electrical resistance between the diffusion source layer 228 and the subsequently formed conductive plug 220a. Further, through a subsequent planarization process such as chemical mechanical polishing (CMP), a conductive structure 500c of an embodiment of the present invention as shown in Fig. 2c is formed. FIG. 14 is a cross-sectional view showing a manufacturing method of the conductive structure of the electronic device 600 according to still another embodiment of the present invention as shown in FIG. 2d. FIG. 2 is a conductive structure 5 different from the conductive structure 5G0a. The material of the conductive plug is doped with a polycrystalline stone. If the components in the above figures have the same or similar parts as those shown in Figures 1 to 13, refer to the front. The related description will not be repeated here. Referring to FIG. 14, the vapor deposition method can be used to form the diffusion region 230 and the barrier layer 218 is formed, and the film deposition by, for example, chemical vapor deposition (CVD) is performed. The method and the subsequent step of forming the conductive plug 220b of the material turned into a polycrystalline spine. In the present embodiment, the conductive plug 22〇b can be, for example, an arsenic doped polysilicon layer (As-d〇). Ped poly). After subsequent CMP, for example

9095-A34433TWF 15 201117358 (CMP) The planarization process is to form a conductive structure 500d according to a consistent embodiment of the present invention as shown in Fig. 2d. Fig. 15 is a cross-sectional view showing a method of manufacturing the conductive structure 500e of the electronic device 600 of the present invention as shown in Fig. 2e, and the difference from the conductive structure 500a is a conductive structure. The e further includes a germanide layer 232 covering the sidewall of the diffusion region 230. The material of the conductive plug is doped poly, and the components in the above figures are the same as or similar to those shown in FIGS. For the part, please refer to the previous related description 'Do not repeat here. Referring to FIG. 15, after the diffusion region 230 is formed and the hard mask structure 243 as shown in FIG. 8 is removed, a germanium formation process is performed to form a germanide layer 232 on the sidewall 226 of the trench 202, and The sidewalls of the diffusion region 230 are covered. In an embodiment of the invention, the germanide layer 232 may comprise a titanium germanide or a lithium compound for reducing the electrical resistance between the diffusion region 2, such as the subsequently formed conductive plug 220a. Thereafter, after the barrier layer 218 is formed, a conductive plug 220b made of doped polysilicon is formed by a thin film deposition method such as chemical vapor deposition (CVD) and a subsequent etch back step. In this embodiment, the conductive plug 22 can be, for example, a doped eutectic polycrystalline layer (As_d〇ped.) and then subjected to a subsequent <scientific mechanical polishing (CMP) planarization process, forming a & The conductive structure of the embodiment of the present invention is 〇〇e. τ Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and anyone skilled in the art can avoid the invention. The protection of the present invention is defined as defined in the appended claims.

9095-A34433TWF 201117358 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view showing an electronic device according to an embodiment of the present invention. 2a to 2e are cross-sectional views taken along line A-A' of Fig. 1 showing conductive structures such as bit lines of the electronic device of the different embodiments of the present invention. 3 to 10 are schematic cross-sectional views showing a method of manufacturing a conductive structure of an electronic device according to an embodiment of the present invention as shown in Fig. 2a. Figure 11 is a cross-sectional view showing a method of manufacturing a conductive structure of an electronic device according to another embodiment of the present invention as shown in Figure 2b. Figs. 12 to 13 are schematic cross-sectional views showing a method of manufacturing a conductive structure of an electronic device according to still another embodiment of the present invention as shown in Fig. 2c. Fig. 14 is a schematic cross-sectional view showing a method of manufacturing a conductive structure of an electronic device according to still another embodiment of the present invention as shown in Fig. 2d. Figure 15 is a cross-sectional view showing a method of manufacturing a conductive structure of an electronic device according to still another embodiment of the present invention as shown in Figure 2e. [Main component symbol description] 200 to substrate; 201 to patterned hard mask layer; 201a to yttrium oxide pad layer; 201b to tantalum nitride layer; 202 to trench; 204, 212 to bottom surface; 206 to sidewall; Insulation underlayer; 211, 220~ conductive material; 9095-A34433TWF 17 201117358 212, 218~ barrier layer; 214~ conductive layer; 22 8~ diffusion source layer; 230~ diffusion region; 232~ Shi Xihua layer; a first dielectric layer; 242~2nd dielectric layer; 242a~doped region; 242b~undoped region; 243~hard mask structure; 246~opening, 24 7~ recessed, 262~ ion implantation step; 220a, 220b~ conductive plug; 258~ cover layer; 300~ vertical transistor; 302~ vertical sidewall; 306~insulation layer; 308~word line; 312~capacitor; 314~> and pole region, 316~ channel Area; 318 ~ source area, 320 ~ first direction; 322 ~ second direction;

9095-A34433TWF 201117358 A 500, 500a, 500b, 500c, 500d, 500e ~ conductive structure 600 ~ electronic device; a ~ angle.

9095-A34433TWF 19

Claims (1)

201117358 VII. Patent application scope: 1. An electronic device comprising: a substrate; a trench formed in the substrate; a diffusion region formed in a portion of the substrate adjacent to the sidewall of the trench; and 'a conductive structure Locating in the trench, comprising: a conductive layer covering a bottom surface of the trench, the conductive layer having a recess to expose the diffusion region from the recess; and a conductive plug filling a recess The sidewall of the diffusion region is provided with a barrier layer between the conductive plug and the conductive layer. 2. The electronic device of claim 2, further comprising an insulating layer covering a sidewall and a bottom surface of the trench, wherein the diffusion region abuts a sidewall of the trench not covered by the insulating pad. 3. The electronic device of claim 2, wherein the barrier layer covers a sidewall of the diffusion region. The electronic device of claim 1, wherein the conductive structure further comprises a germanide layer formed on a sidewall of the trench not covered by the insulating pad and adjacent to the diffusion region. 5. The electronic device of claim 4, wherein the conductive structure further comprises a diffusion source layer formed on a sidewall of the trench not covered by the insulating pad, and interposed between the germanide layer and Between the diffusion zones. The electronic device of claim 1, wherein the conductive plug comprises a metal or polysilicon. 7. The electronic device of claim 1, wherein the conductive layer 9095-A34433TWF 20 201117358 is a metal layer. 8. The electron according to claim i, wherein the barrier layer comprises titanium, titanium nitride or a combination thereof. (2) The electronic device of claim 1, wherein a cover layer is formed in the trench and covers the conductive plug. 10. The electronic device of claim 3, wherein the insulating mat layer comprises an oxide layer, a nitride layer, or a combination thereof. 11. The electronic device of claim 5, wherein the source layer comprises doped polysilicon. 12. The electronic device of claim 1, wherein another barrier layer is disposed between the conductive layer and the trench. The electronic device of claim 1, wherein the conductive structure is a one-dimensional line. 14. The electronic device as described in item ii of the claim is a mobile memory random access memory device 1 to 15. a memory device, including: a substrate; at least the sidewall is formed in the substrate, having a vertical at least one word line formed along the first direction in the substrate, the word lines being disposed on the pair of vertical transistors And the at least one element line is formed along a second direction different from the first direction; in the substrate; the groove is located below the pair of vertical transistors and borrows Formed on a portion of the substrate adjacent to the sidewall of the trench, the m-day (four)-secret region of the substrate, the towel of the bit 9090-A34433TWF 21 201117358 includes: a cladding layer covering the trench a bottom surface of the trench, the conductive layer having a recess such that the diffusion region is exposed from the recess, and a V-electrode plug fills the recess and covers a sidewall of the diffusion region, wherein the conductive plug and the conductive layer There is a barrier layer between them. 16. The memory device of claim 15, further comprising at least one capacitor electrically contacting a source region of the vertical transistor. The memory device of claim 15, wherein the 7L line further comprises an insulating layer covering the sidewall and the bottom surface of the trench, wherein the money gap is adjacent to the trench. The side green raft covered by the insulating enamel layer 18. The memory body according to claim 17, wherein the early layer of the resisting P covers the side wall of the diffusion region. The memory device of claim 15, wherein the memory device further comprises a wafer layer formed on the sidewall of the trench not covered by the insulating layer and adjacent to the diffusion region. The memory device according to claim 19, wherein the first center line further comprises a diffusion source layer formed on the sidewall of the trench that is not insulated by the insulating layer _§_ Between the layer and the diffusion zone. The memory device of claim 15, wherein the conductive plug comprises a metal or polysilicon. 8. The memory device of claim 15, wherein the conductive layer is a metal. 23. The memory device of claim 15, wherein the barrier layer comprises titanium, titanium nitride, or a combination thereof. The memory device of claim 15 further comprising a cover layer formed in the trench and covering the conductive plug. 25. The memory device of claim 17, wherein the insulating germanium layer comprises an oxide layer, a nitride layer, or a combination thereof. 26. The memory device of claim 20, wherein the diffusion source layer comprises doped polysilicon. 27. The memory device of claim 15, wherein another barrier layer is disposed between the conductive layer and the trench. Φ 28. The manufacturing method of the electronic device comprises the steps of: providing a substrate; forming a trench in the substrate; forming a conductive layer in the trench covering the bottom surface and a portion of the side surface of the trench, the conductive The layer has a recess adjacent to the sidewall of the trench; a diffusion region is formed in the substrate adjacent to the recess; a barrier layer is formed in the trench to cover the conductive layer; and in the trench A conductive plug is formed to fill the recess and cover the sidewall of the diffusion region. 29. The method of fabricating an electronic device according to claim 28, wherein the step of forming the conductive layer further comprises forming an insulating underlayer on the sidewalls and the bottom surface of the trench. 30. The method of manufacturing the electronic device of claim 29, wherein the step of forming the conductive layer further comprises: forming a conductive material in a comprehensive manner and filling the trench; and performing an etching process, shifting In addition to the substrate above and partially located in the trench. i 9095-A34433TWF 23 201117358 conductive material in the trench; the port is formed in the trench to form a hard mask structure, which has - open to expose a portion of the conductive a material; and a portion of the conductive material that is not covered by the hard mask structure to form the conductive layer having the recess. The method for manufacturing an electronic device according to claim 30, wherein the step of forming the diffusion region further comprises: = removing the portion (4) of the portion of the wire from the recess to expose the portion of the trench a sidewall; and a removal of the hard mask structure. ^2, as in the manufacturing method of the electronic device of the 3G item, the step of forming the conductive layer in L further includes conforming to form another barrier layer on the side soil and the bottom surface of the Hankor spoon. 33. The method of claim 4, wherein the step of forming the hard mask structure further comprises: conforming to forming a first dielectric layer and an upper layer in the trench. a second dielectric layer; ^ an ion implantation step on the first dielectric layer of the δH to form a doped region and an undoped region in the first electrical layer; Removing the undoped region until a portion of the first dielectric layer is exposed; and '- performing a dry etching process to remove the first dielectric layer that is not covered by the second dielectric layer after the last name The electrical layer forms a hard mask structure. 34. The method of manufacturing an electronic device according to claim 28, wherein the step of forming the diffusion region further comprises: 9095-A34433TWF 24 201117358 using a gas phase doping method to remove a gas containing a dopant from the dew The side wall is in the part of the county plate, and (4) into the diffusion zone. *, 35' The manufacture of an electronic device as claimed in claim 28, wherein the step of forming the diffusion region further comprises forming a diffusion source layer on the sidewall of the trench. ^ As for the manufacturer of the device, the diffusion region is adjacent to the diffusion source layer. The method of manufacturing the electronic device of the electronic device described in claim 36, before the step of forming the barrier layer, further comprises forming a layer of the cerium in the trench and covering the side of the diffusion source layer. wall. The method of manufacturing an electronic device according to Item 33 of the patent application of the present invention, wherein the first dielectric layer and the second dielectric layer are made of different materials. In the method of the invention, the manufacturing layer of the electronic farm described in Item 38 of the patent application is an uncoated layer including an oxide layer or a nitride layer, and the second dielectric method (4) is a manufacturer of 28 electronic devices for riding. The conductive plug includes a metal or polysilicon. In the manufacturing method of the electronic device described in Item 28 of the Japanese Patent Application Serial No. 28, the conductive layer is a metal. 42. If the patent scope law is applied, the manufacturing line of the electronic device of the mine; One of the dynamic random access memory cells 7095-A34433TWF 25