TWI292616B - Offset-bonded, multi-chip semiconductor device - Google Patents

Offset-bonded, multi-chip semiconductor device Download PDF

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Publication number
TWI292616B
TWI292616B TW093136257A TW93136257A TWI292616B TW I292616 B TWI292616 B TW I292616B TW 093136257 A TW093136257 A TW 093136257A TW 93136257 A TW93136257 A TW 93136257A TW I292616 B TWI292616 B TW I292616B
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Taiwan
Prior art keywords
bump
semiconductor
wafer
semiconductor device
bumps
Prior art date
Application number
TW093136257A
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English (en)
Other versions
TW200527646A (en
Inventor
Masaya Kawano
Satoshi Matsui
Original Assignee
Nec Electronics Corp
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Publication date
Application filed by Nec Electronics Corp filed Critical Nec Electronics Corp
Publication of TW200527646A publication Critical patent/TW200527646A/zh
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Publication of TWI292616B publication Critical patent/TWI292616B/zh

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

1292616 九、發明說明： 【發明所屬之技術領域】 趙裝備= ί 趙 合型多晶片半導體裝置。 " 隹且且接&成之偏矛夕接 【先前技術】 ^ 了同時減少半導體積體電路 裝單元。 妾口方式為基準來彼此接合，藉以形成一安 示之眾體出一隹種coc型半導體裝置的習知構造。圖中所 ^ ϊ/5Γ；Γί ^ LSI LSI 51 合方式為基準接合的Ϊ於與凸塊55形式的面朝下接 間則填滿著一絕緣樹脂56 曰與第二⑶晶片52 架”的-晶粒烊塾6〇上弟=日曰片5H糸以焊料固定在導線 線架57的内引線58則孫一晶片51的外部電極54與導 電連接在―起^ 、二厶由薄金屬配線所組成的接合配線59而 在上述的“丨線585接合配線59來成形。
晶片51的幾何尺寸，如果第二LSI晶片52與第一 LSI 大的幾何尺寸、諸如超過配目置果第二LSI晶片52具有較 Λ糊己置其下的第一 LSI晶片51之幾何尺寸 1292616 ϊ 部署連接著第—LSI晶片51上導線架57之内引 連接的外部電極54來構成半導體裝置。 片與著接合不同魏的；（諸如上晶 二LSI日。為一邏輯#作與一記憶體)而構成的。對於上面第 寸將會^曰it j，片的一示例情況來說，未來晶片的幾何尺 曰片二二、思體容置增加而擴張。另一方面，對於下面第一 LSI i曰何ίΐ邏^操作晶片的—示例情況來說，電路的細微製造可降低 、 此，§己憶體晶片的幾何尺寸會變得較邏輯晶片者大二
7"^LSI 子配ii 3 ’這會無法將與外部交界著的外部連接端 造而+在ϋ表面_周部份上。換言之，針賴16所示的構 利Situ提出各種建議案。舉例來說在曰本公開專 tin I2號中，以旋轉方式讓上面與下面晶片彼此移 露出來。3讓下晶片角洛部份上的主晶片表面從上晶片外圍處曝 曰片=公3,報第·3—68975號提出一種堆疊式的上與下 ^^目山的在確保有—較大區域供外部連接端子區之用，盆中 出-ίϊίϊΐί位、以便於超出上晶片四邊任-者。此文件亦提 位。+财置’其中讓上晶片與下晶片沿對角線方向來彼此移 轉苹3 ί=ίΓ公報第1G—256472號中所述之方法，其中是旋 =^並猎此與另一晶片移位，以便於讓下晶片角落部份 外部連與下晶片的中心位置維持一致’並以曝露部份當作 ίϊί”之用，然而其僅容許有限數量的電極設置其中。 、、土一情况提供日本公開專利公報第2003一68975號中所述之方 /-種優點’其中讓上晶片與下晶片平行移位，以便於避免兩者中 6 1292616 心一致，以便藉此確保有一較大區域來作為外部·連接端子區之用。 然而，在此方法中的上與下晶片移位可能會造成如圖17所示 的情況，其中上晶片61的重心G會落在由上晶片Μ與下晶片 間之隶外側凸塊所圍繞的一區域之外。此會對因上晶片Μ自上方 所施加的凸塊63貞重（由圖π中的空白箭號所表示）產生出抗_ 力（由圖17中的填滿箭號所表示）。該應力可能會導致上與下晶片 間的凸塊63破裂，因而退化結合的可靠性。 這種情況因此提高了對於C0C型半導體裝置的要求’其中藉著 上曰曰片對下晶片偏移而讓上晶片與下晶片經由凸塊接合，以便於避 免兩者中心一致’並因而確保晶片接合並同時確保有一足夠 面積來作為外部連接端子區之用。 【發明内容】 依本發明所提供的半導體裝置，具有未對正兩者中心的 一 f導，兀件與堆疊其上之—第二半導體元件，且該第—半導體元件 所设置之電極係經由凸塊而連接至位在重疊區内、該 工：；，極，其中，該第二半導體元件之重心是“由接 體導體元叙 -半該導體元件之負荷可僅作為加壓在該第 棟私禮料體70件間之凸塊上的—勤，而非對凸 维靠，；趙元件與 —m潰疋彼此—致。依此構造，發揮至凸 本發明可勒於半導雜置，其愤第—凸塊區包含三個凸塊 1292616 :者 兮第可適用於半導體裝置’其中該第一凸塊區包含至少以 ίΐ導體雜之中心線為基準相對於單—轴線對稱配置的凸 元^3而成的半導體裝置中，較佳之情況是該第一半導體 該第二半導體元件所重疊區域外側之一區域内所配置- =化斜部連接端子的間距。在採用交錯配置時，給: 區=定面積將因此具有大量的外部連接端子配置其間。此g於 工奴曰η 士仟移位將尤0足夠。換吕之，即便外部連接端 加時’亦很容易讓該第二半導體元件的重心落在該第-凸 更佳之情況是-第三半導體元件係堆疊在該第二半導體 上’致使該第三半導體元件之重心是與該第二半導體元件心一 致的。又更佳之情況是複數個半導體元件係堆疊在該 件上’致使該複數個半導體元件之各個重心是分別與導 元件之重心一致的。 、 對於一或複數個半導體元件係堆疊在該第二半導體元 情況來說’所堆疊之半導體元件的重心與該第二半導體元件的重心 一致會使其可能僅將壓力發揮在各個鄰近堆疊之半導體元的 整個接合部份(例如凸塊）之上，則此成功地避免接合可靠性二退 化0 在如此建構而成的本發明半導體裝置中，該第一半 該第二半導體元件係接合的，同時容許該第二半導體元件之一面 超出該第一半導體元件之至少一端面。 在此情況下，較佳之情況是將一虛擬晶片配置在該第二半導體 8 1292616 擬晶片超:本;^過該第二半導體元件與該虛 ί :半“元件二;2體半=未對 iiSESSil i少二ίΐ^ΐί=元件之—端面超出該第—半導體元件之 ，叠區；;====== ΐ第=ΐίί一最大化區的一區域内側，而該最大化區係由連接 一第rt4區中之最外侧凸塊與—第二凸塊區中之最外侧凸塊、以 便於^職別凸塊區的脑部份所定義而成的，其中該第一凸塊 一半導f7"件與該第二半導體元件之該最外側 ίίΐϊ成的’而該第二凸塊區縣由接合著該第二半導體元 件與该虛擬晶片之該最外側凸塊所圍繞而成的。 依，構造，該第一半導體元件的重心係由該虛擬晶片所支撐、 以便於財該第二凸塊區_，或落在藉著連結該第—凸塊區中之 最外側凸塊與該第二凸塊區中之最外側凸塊所決定的一區域内 側L如此一來即便上面該第二半導體元件大幅超出下面該第一半導 體元ί、其亦可維持機械強度，且上面該第二半導體元件的重心是 因此落在連接著下面該第一半導體元件與上面該第二半導體元件 之該第一凸塊區外側。 、在该第一半導體元件與該第二半導體元件係以樹脂成形時，因 為該第二半導體元件之超出區下方空間係由該虛擬晶片所佔滿，故 此亦有助於避免讓樹脂進入該第二半導體元件下方的空間。因為較 樹脂不易引起熱膨脹之該虛擬晶片係部署在該第二半導體下方，故 加熱週期測試中之負荷較不可能施加在該第二半導體元件上，因此 將可避免凸塊連接部的中斷。由該虛擬晶片來佔滿該第二半導體元 件超出部份下方之空間亦可成功地避免在利用樹脂成形接合著之 1292616 該第一半導體元件與該第二半導體元件後、空氣殘留在該第二半導 體元件下方。該第二半導體元件係因此不再施加以在加熱週期測試 期間之空氣膨脹所導致之樹脂隆起的負荷，如此一來將不再害怕造 成凸塊連接部的中斷。 在此情況下的該虛擬晶片較佳之情況係由具有接近該第一半 導體元件者之一熱膨脹係數的一材料所製成的。又更佳之情況是該 虛擬晶片係由石夕所製成的。 又較佳之情況是該虛擬晶片之厚度落在一最大值與一最小值 間，該最大值係定義成該第一半導體元件的厚度與該第一半導體元 件上所設置之該凸塊的接合前高度之一總和，而該最小值係定義成 由該第一半導體元件之背面與該第二半導體元件之頂面間的接合 後距離、減去該凸塊的接合前高度所獲得的一剩餘值。依此構造， 該第二半導體元件與該第一半導體元件的凸塊接合係可建立，即便 該虛擬晶片遺留在該第二半導體元件之超出區下方，致使嗜窠一 導體元件可與該虛擬晶片以一可靠方式來連接。 ϋ弟一牛 二較佳之情況是該虛擬晶片具有其表面上所設置的一金屬膜，且 該金屬膜較佳之情況包含一鉻膜與其上所設置的一鋁膜。在由矽所 製成之該虛擬晶片上設置鋁膜，同時在其間放置鉻膜，會成功地改 善鋁膜的附著性。依照改善該第二半導體元件與該虛擬晶片 的附著性來說，當該第二半導體元件之凸塊係由_製成時亦期^ 有此類的膜構造。 又車父佳之情況是該虛擬晶片的厚度是相當於該第一半導體元 件的厚度。依此構造’該第-半導體元件與該虛擬晶#係給予依照 凸塊接合觀點3Μ歧相等的-構造，致使其可能執行歡的凸塊接 合0 =據本發明’其中上面該第二半導體元件係安排成與下面該 了半¥體元件移位’且其中該外部連接端子係部署在該第一 疋件之表面的曝露部份上’該第一半導體元件與該第二半導體 係接合的、致使該第二半導體元件的重^是落在由該第__半導體元 1292616 件與該第二半導體元件間之該凸塊所圍繞成_域關。依此構 造’上面該第一半導體元件之負荷可僅作為加壓在該第一半導體元 件與遠第二半導體it件間之凸塊上的-壓力，而非對凸塊發揮抗張 應力。此使得其可能維持透過該第一半導體元件與該第二半導體元 件間之凸塊接合的可靠性。 ' 半導體裝置係亦可建構成具有一第一半導體元件與堆疊其上 之-第二半導體元件，同時容許該第二半導體元件之一端面^出該 第一半導體元件之至少一端面；將一虛擬晶片部署在該第二半導體 元件之超出區下方，透過該凸塊來將該第二半導體元件接合至該虛 擬晶片；並容許該第二半導體元件之重心是落在具有一最大化區的 -區，内側，而該最大化區係由連接—第—凸塊區中之最外侧凸塊 與第一凸塊區中之最外侧凸塊、以便於包含該個別凸塊區的整個 部份所定義而成的，其中該第-凸塊區係由接合著該第一半導體元 件與該第二半導體元件之該最外側凸塊所圍繞而成的，而該第二凸 塊區則係由接合著該第二半導體元件與該虛擬晶狀該最外側凸 塊所圍繞而成的。即便該第二半導體元件之重心是落在由該 件，該第二半導體元件間之凸塊所圍繞成的區域外側時，此 構造亦使得其可確保機械強度，並改善電接合的可靠性。 【實施方式】 ^發明現在將於此參照實施舰a絲加以描述。熟悉該項技術 之相關人士將理朗本發_指導將可完餅多獅性 細例，且本發明不侷限於作為解释目的所說明的實施例。 (第一實施例） ' ，2顯示本發明第一實施例的coc型半導體裝置構造之側視 圖，而圖2則如圖1所示的半導體裝置之平面圖。 ，在參照圖卜作為電極端子的球狀凸塊i係配置在其上已設 ”線之基板2(例如印刷配線板）的一表面上。 ’則安裝有一第一晶片3。第-晶片3與-第二 係彼此接e，以便讓第二晶片4姉於第—晶片3平行移位，同時 1292616 容許第二晶片4的一部份超出第一晶片3。 ，而具有較邏輯晶片 片。第一晶片3可為 下側上所部署的第一晶片3為一邏輯晶片 者大之幾何面積的第二晶片4則為—記憶體晶 亦即第=1 μ3ί第二晶片4係以面朝下接合方式為基準接合的。 Γ/面:：曰 表面與第二晶片4表面為面對面的’而第二晶片 所ϊ置之凸塊6係接合至第—晶片3表面電極上所配 曰=45。此處實施例是顯示出—種技術，藉此讓凸塊配置在上 曰田曰片/、1晶片表面電極兩者上、然後讓彼此接合，反之也可容許使 上面第二晶片4上之凸塊6來與其上未配置有凸塊5的下面第一 晶片3接合。 未/、弟一日日片4重：g：之弟一晶片3區域為配置著複數個接合墊 8的一外部連接端子區。 位在第一晶片3上的接合墊8係電連接至基板2週圍部份上所 配置的接合墊9。而接合墊9係再電連接至基板2背面上的球狀凸 塊1。外部連接並非總是仰賴如圖丨所示的球狀凸塊丨來建立的。 亦可容許使用導線架來替代球狀凸塊i。 、在第一晶片3與第二晶片4的連接狀態中，第一晶片3之一部 份與第二晶片4之一部份並未對正兩者的中心來重疊。再者於本發 明中，第二晶片4的重心會落在由第一晶片3與第二晶片4間之^ 外側凸塊所圍繞的區域（以下稱為「凸塊區7」）内側。理解到「内 側」亦包含正好落在最外侧凸塊上的位置。因為凸塊不是點狀、而 疋具有一截面積，所以「内側」更嚴格來說表示位在最外側凸塊的 外部輪廓與其内側區域的位置。在目前的實施例中，第二晶片4的 重心與凸塊區7的中心重疊。 將參照圖3來解釋此構造的效果。為了簡化說明，故圖3將圖 1所示的凸塊5、6顯示成單一的凸塊1〇。 如圖3所示，當第一晶片3與第二晶片4係接合成讓第二晶片 4的重心G與凸塊區7的中心對正時，則將僅會以壓力施加在所有 12 1292616
凸塊ίο上。換言之，未有抗張應力施加在凸塊10上，而此合 地避免掉接合可靠性的退化。 9 J 在此實施例中，位在曝露於第二晶片4外之第一晶片3表 的接合墊8係配置成交錯圖案。與非處於交錯配置者之^ 交錯配置的接合墊8會窄化接合墊8配置的間距。交錯置因j 為外部連接端子區之既定面積内設置大量的襯塾。此^利於 部連接端子區中的襯墊數量增加時，則第二晶片4僅 曰 片3少量移位(偏移)將就會足夠。換言之，即便外部連接端曰曰 =襯墊數量增加時，亦很容易讓第二晶片4的重娜在凸塊^ 7内 雖然上述實施例顯示出一種構造(參見圖2)，复曰 4相對於第-晶片3移位、以便創造連續形成的外;曰片 但本發明並不紐於此構造。_上述第—晶片3卜^接 ，，，-邏輯晶片、與幾何面積大於邏片 其了此案例乃疋利用日本公開專利公郝筮 之圖利b)與⑻崎稍絲單元來 g 匕貫施例之安鮮元雌構成的半導難=用任何其 3與第圖以; a 一可能構造具有如圖4所示、位在第 晶片4沿對角線方向與第—晶片 :士、猎者讓弟二 ^子區。這働造錢.财彻外部連 (GaAs、SiGeC、CMOS)的堆疊。 稷成正方形之单元 ，下=上面第二晶片4為矩形的情況來說，—可倉n日1 弁下面弟-晶片3之—端部份超出上_ ^構w疋诸如容 圖5所示般。. 面第—日日片4的四邊之一，如 1292616 對於下面第一晶片3 容許上面第二晶片4之_=^的情況來說H能構造是諸如 =圖6所示般。又另—可J以，出下面第-晶片3的四邊之一， 各許其一部份超出下面第一曰=如圖7所不，諸如具有移位成 片4。 日日月3的四邊之一的一矩形上面第二晶 能提供一大面積給外Γρϋί山^於第一晶片3超出的情況會讓其可 另一方面，對於第二曰^而，並確保其内的端子數量大。 似的情況來說，—可巧大顿乎與第m者相 :立’如此-來讓其-端部第? 4:圖8所示般移 顯示出第—晶片3 一曰曰曰片3的四邊至少一者。圖8 第二晶片4是小於；玆=為正方形的特殊情況，上面 第二:曰曰片4的重心是位在凸:區7 =不會超出第一晶片3，且 4 在第二晶是具有諸如部署 擬晶片24接合。此構造能夠穩定其曰片上，該虛 的空間中，龄力笙一曰μ Q办雄—节社乐一日日片4超出下方 裝製，，幾乎完;;免讓樹====的封 週期測試中的負荷較不可能施加在第二^片在/上口熱 4τ^-ίί ^ 地避免在以樹脂成形之第—晶片3與第二晶片4封裝 二钱留在弟二晶片4的下方。第二晶片4係因此不再施加以 1292616 在加熱週期測試期間之空氣膨脹所導致之樹脂 來將不再害怕造成凸塊連接部的中斷。 、、。 所制擬=得由由接近第一晶片3材料之膨脹係數的材料 大值間’其中最 接合前高度的總和，而最小^的上”巧凸塊5的 晶“頂面(凸塊設置表 2置：二接t 一剩餘值。依此構 洛在弟一日日片4赵出區下方亦可建立起第二 =塊接合’如此一來第二晶片4之凸塊6即；】4；^ = 與虛擬晶片24連接。 嗖置22 Γ乍ί擬晶片24之用，然後將鉻膜與鋁膜依此順序 以塊當作第二晶片4之凸塊6之用。這個 成著声之凸塊6可緊密地接觸著虛擬晶片24。而位在組 ===。夕表面上的絡膜係用來改善石夕表面與最頂触 料、改善層並不侷限於鉻，而是可任意選自於任何材 ϊ二ίϊΐ 夕表面的附著性即可，其案含鎳、鈦、组、 因為ί用ϊΐί化15等。目前之實施例顯示出一示例性情況，其中 马知用金凸塊而將鋁膜設置在虛擬晶片24上。除此 凸凸塊、銅凸塊、錄凸塊與由堆疊這些材料、諸如銘/錄 並凸塊所得的凸塊。同時在虛擬晶片24所堆疊的金屬膜 兀不侷限於鋁膜，亦可任意選自於上面所列的材料。 盥第所示的構造中’虛擬晶片24的厚度係設定成 忒ids乎相同’具有與第一晶片3上者相同幾何尺寸的 式在虛擬晶片24上’而第二晶片4係以凸塊連凸塊方 刀 5至第一晶片3與虛擬晶片24。在此於虛擬晶片24上的 15 1292616 凸塊屬於虛擬凸塊，其不像第一晶片3上的凸塊具有任何電氣連接 的效益。此現象會使得第一晶片3與虛擬晶片24具有 合的結構，並實現穩定的凸塊接合。 " §作3己恍體晶片之第二晶片4的凸塊區7具有如圖所示的3 個凸塊群，而該3個凸塊群包含當作輸入/輸出者、當作電源者與 ，作GND者。更特別的是，讓一中心1/〇凸塊群12建構成具有複 數個凸塊列，各列各自包含橫向配置的複數個1/〇凸塊（當作輸入/ 輸出#號的凸塊）。並讓部署在圖示中之中心1/〇凸塊群12右手側 亡的GND凸塊I3建構成具有複數個凸塊列，各 塊。且讓部署在圖示中之左手侧上的電^^群 ，、有衩數個凸塊列，各列各自包含橫向配置的複數個電源 凸塊。 m ^ f示的凸塊區7内之凸塊配置外，另—可能構造如 圖11所不，其中將具有幾乎相同數量凸塊之凸塊群14、15以第二 中，烈為基準相對於單一軸線對稱配置(稱之為反射對 二行並二曰到本發明並不揭限於包含兩凸塊群的凸塊區，並容 置的凸塊群。一記憶體之示例情況將具有-交錯設置 κΐΐίίί侷限於具有相對於單—軸線對稱配置的凸塊群 ϋ亦可對稱於橫向與縱向的兩軸線理 塊區it無嫩顯示出以上所ί置 之對正私不配置與電源配置所得的完美對稱。 接合其中第二晶片4之重心是落在 县m几」如圖12A 12c所示般、讓第二晶片4之重心 -晶片3鱼第I日=。圖12β顯示出一示例情況，其中接合著第 晶片24 *第塊區7(第—凸塊區）、以及接合著虛擬 相同的幾何尺—，二凸塊區）係建構成具有 丁弟—日曰片4之重心此時是落在凸塊區7與虛擬凸 16 1292616 塊區25的中間區26。此構造使其可確保一穩定凸塊接合。圖12C 顯示出-示例情況，其中接合著第-晶片3與第二晶片4的凸塊區 7(第-凸塊區）、以及接合著虛擬晶片24與第二晶片4的虛擬區 25(第二凸塊區）係建構成具有不同幾何尺寸，且係沿圖示中的丫軸 方向移位。在此情況下，可藉著讓第二晶片4之重心落在_區域内 ，來達成穩定凸塊接合，其中該區域具有藉著連結第一凸塊區中之 最外側凸塊與第二凸塊區中之最外側凸塊、以便包含個別凸塊區整 個部份所定義出的-最大化區，而其中第—凸塊區係由方形即⑶ ，合而成的，而第二凸塊區則係由方形ABCD接合而成的。更特別 ，利用一直線連接第一凸塊區中之最外侧凸塊E與第二凸塊區中之 ，外側凸塊A，並利用一直線連接第一凸塊區中之最外側凸塊G與 第二凸塊區中之最外侧凸塊C，藉此來定義出包含第一凸塊區與第 二凸塊區整個部份的最大化區，以便於容許讓第二晶片的重心落在 其中。在此情況下，該最大化區的區域將大於利用連接第一凸塊區 與第二區塊區對邊EF、DCJi的凸塊e、D與凸塊F、C所定義出的 區域，多了三角形AE1D與FCG。假如第二晶片之重心是落在三角形 内，亦可獲得穩定凸塊接合。 在某些情況下，可利用複數個不規則散亂的凸塊群來建構成凸 塊區。在此情況下，凸塊區係利用直線與凸塊群外圍等所圍繞、將 晶片外圍區上所坐落之凸塊群巾的最外側凸顧酸直線連接以 便包含所有凸塊群而獲得的最大化區所定義的。圖13A顯示出一示 例情況，其中由第二晶片的觀點來看其設置有9個凸塊群。除了凸 ，群外的任何構造並未說明。在此之中，7個凸塊群27至33具有 最外側的凸塊:而2個凸塊群34、35則沒有最外侧的凸塊。因此 此時的凸塊區係由直線與7個凸塊群外圍所圍繞的區域定義而成 的，其中的直線會將晶片外圍部份上所坐落、除了凸塊群34、35 以外之7個凸塊群中、鄰近凸塊群内的最外側凸塊連接在一起。第 二晶^的重心係設計成落在該區域内。圖13B顯示出一示例情況， 其中第一凸塊區包含9個凸塊群36至44，而第二凸塊區包含β個 17 1292616 的第-凸塊區盘第二化述情況是有關於接近矩形 亦容許除了矩it L形Γ圓表*僅偈限於矩形者， (第二實施例） a如第列是以具有兩個堆疊於基板上之晶片的半導體穿置 有咖增於基m導 分別t實施例的半導體裝置之側視圖’其 施例圖14顯不出具有三個堆疊於基板上之晶片的半導體裝置之實 線的2:=-= 晶片3_術已猶電線配 —曰κ 二日日片係以面朝下接合方式為基準而接合在第 ΐί^ΐτ'" 塾二二而所曝露區即當作其間配置有複數個接合 讓兩第三晶片16係接合在第二晶片4上，以便於 .：!：:； 2 四晶片π、第五晶片18與第六晶片 1292616 示例半導體裝置。 19的- 第一至第六晶片4、16、17、18與19個別具有壤頂而盘此； 上之=電連接的通孔2〇,個別晶片之頂面上的電極具*設置^上 的凸塊，且個別晶片之背面上的電極則具有 ^ ^ 的凸塊21與背面上之=上 的凸，22^¾接合的，並係透過通孔2〇而電連接的。 ^一晶片3之頂面上的電極具有設置其上 面ί的日電極具有設置其上的凸塊22，然後透過這些tr21 22而讓弟一日日片3與第二晶片4接合。 晶的ϊίί S m5所示的構造，因為接合第—晶片3上所堆 。亦即，不怕對任何凸塊造ϊ抗S力= 並非總是需要讓第二晶片上所放置的晶片具 3:、弟了片對正的重心，且如果包含第二晶片與其 =區内侧的話’則可達到穩定的凸塊i合。 例在二13者’個晶片且其間個別放置著凸塊的-示 的^數）曰許包含第（n+1)個(η為從1至(堆疊晶片數量一 υ i ^與其上所堆疊全部者之整悔疊的重4錢接著第 ϋ曰晶片數量―1)晶片與第㈣)個(II為從1至(ί ii曰片的凸塊區内側，則可達到各鄰近晶片的 鱼曰ίί意Ϊi在本發明中’第一晶片3與第二晶片4的堆叠模式 的構造可等同於諸如第—實施射所描述者。 的精神實施例’其係可在不脫離本發明 【圓式簡單說明】 ^ 19 1292616 cocSiiir第—實施例中堆疊著第κ與第二晶片的， 严1置構造之側視圖； 半導體裝置之平面圖； 圖示； 本龟明第一實施例的C0C型半導體裝置的效果之 裝單堆疊第—晶片與第u所建構成的另，種安 成的圖上:示、由堆疊第-晶片與第二晶片所建構 安裝單元模豐弟—晶片與第二晶片所建構成的又另〆種 的又^ -種安穿不出由堆疊第一晶片與第二晶片所建構成 圖8 ^，〇^%式之側視圖與平面圖； 圓8疋顯不出由堆疊第一曰 安裝單元模式之平面圖；曰曰/、弟二晶片所建構成的又另一種 接可靠性的本進-纽雜麵度與電連 例凸塊結構之平面圖； 月牛蜍體裝置之第二晶片的另一示 圖Η是顯示出適用於本發明 例凸塊結構之平面圖； ‘體衣置之第二晶片的另一示 圖12Δ至12C是顯示出有助於 一、 可靠性的本發明示例性丰導髀又進一乂改善機械強度與電連接 圖⑽與戰顯… 在其中的凸塊區與最大化區定義之” 中了讓弟二晶片之重心落 圖14是顯示出本發明第二實’ 示例C0C型半導體裝置之侧視圖、；Η，，、有三個晶片堆疊其中的 圖15是顯示出本發明第二實 示例C0C型半導體裝置之側視圖、她例，具有六個晶片堆疊其中的 20 1292616 =是置觀之剖面圖 Γ主要元件符解_題之圖示。 1〜球狀凸塊 以及 球狀凸塊 Z〜基板 63〜凸塊 4 ，一晶片，為一邏輯晶片 第二晶片，為一記憶體晶片 b N 6〜接合凸塊 7〜第一凸塊區 8、9〜接合墊 10、21、22、55 11〜電源凸塊群 U〜中心I/O凸塊群 13〜GND凸塊 14、15〜反射對稱凸塊群 16〜第三晶片 17〜第四晶片 18〜第五晶片 19〜第六晶片 20〜通孔 23〜第二晶片4之中心線 24〜虛擬晶片 25〜第二凸塊區 如〜中間區 3:、3、巧右外Γι、32、33〜具有最外侧凸塊之凸塊群 叫、35〜沒有取外側凸塊之凸塊群 36、37、38、39、40、41、42、43、44〜第一凸綠 f 夕几地 46、47、48、49、50〜第二凸塊區之 ⑽之凸^ 51〜第一 LSI晶片 21 1292616 52〜第二LSI晶片 53〜内部電極 54〜外部電極 56〜絕緣樹脂 57〜導線架 58〜内引線 59〜接合配線 60〜晶粒焊墊 61〜上晶片 62〜下晶片 64〜模塑樹脂 ABCD〜第二凸塊區接合方形 EFGH〜第一凸塊區接合方形 G〜重心 22

Claims (1)

1292616 十、申請專利範圍： 二半1 導體S導·?ί5ίί—第一半導體元件與重疊其上之-第 [ίΐ 元件與該第二料體元件兩者的中心 經由凸塊而連接於該第二轉體元件上所設置之電極^置之電才 i ^第'^ t件之重心*落在由接合著該第一半導體 -第二;體讀之該等凸塊中之最外側 2*-種半導體裝置，具有―第―半導體元重上 =導體元二，該第一半導體元件與該第二半導體元;兩=中： 件少阳㈣—轉體元件之—端面超出該第—料體元 力^ 於該第Γ半導體元件與該第二半導體元件兩者的重疊區 半導體70件上所設置之電極經由凸塊而連接於該第二半 V體70件上所設置之電極；且 -主=第二半導體元件之該超出區下方配置—虛擬“，而該第 一 +導體7〇件上戶斤言史置之豸電極經由凸塊而接合至在該虛擬晶 上所設置之電極； 其中，該第二半導體元件之重处落在具有—最大化區的一區 ，内側，而該最大化區係由連接_第—凸塊區中之最外侧凸塊與一 第二凸塊區中之最外側凸塊，以包含個別凸塊區的整個部份所定義 而成的，其中該第一凸塊區係由接合著該第一半導體元件與該第二 半Ϊ體Ϊ件之該最外側凸塊所圍繞而成，而該第二凸塊區貝ί係由接 合著该第二半導體元件與該虛擬晶片之該最外側凸塊所圍繞而成。 3·如申請專利範圍第1項的半導體裝置，其中，該第一凸塊區 之中心與該第二半導體元件之重心是彼此一致的。 4二如申請專利範圍第丨項的半導體裝置，其中，該第一凸塊區 包含三個凸塊群，而該三個凸塊群包含作為輸入/輸出用者、作為 電源用者與作為接地用者。 23 1292616 區 作為 5一·如申明專利乾圍弟2項的半導體裝置，复 包含二個凸塊群，而該三個凸塊群包 ，、中，該第一凸塊 電源用者與作為接地用者。 &局输入/輪出用者、作^ 一 6·如申請專利範圍第1項的半導體梦晉， 元件是一記憶體晶片。 、 〃中，該第二半導體 7·如申請專利範圍第2項的半導 元件是一記憶體晶片。 丑又置，其中，該第二半導體 8>申請專利範圍第j項的半導體褒置， 包含至少以該第二半導體元件之中 編、^凸塊區 稱配置的凸塊群。 、、、土準相對於單一轴線對 勺入申明專利範圍第2項的半導體裝置，1中，9楚JL 包含至少以該第二半導體元株 "、中该第一凸塊區 稱配置的凸鱗。 ^線絲準相對於單-輛線對 ϊ〇·如申请專利範圍第1項的半導 體元件具有與該第二半導體元件置;、中，該第一半導 配置。 卩連接编子，而该稷數個外部連接端子係以交錯方式 體元ί牛1且如利範圍第2項的半導體裝置，其中，該第一半導 晉的、-^^有^以苐―半導體70件所重疊區域外側之一區域内所配 配置固外部連接端子’而該複數個外部連接端子係以交錯方式 導體圍第1獅半導體健，其巾，在該第二半 心是細3重3j二第三半導體元件，而使該第三半導體元件之重 疋，、巧弟—半導體元件之重心一致。 莫辦^如申請專利範_2項的半導雜置，其巾，在該第二半 心是第三半導體元件，而使該第三半導體元件之重 厂〜弟—丰¥體元件之重心一致。 導體申晴w專利範圍第1項的半導體裝置’其中’在該第二半 -儿件上重疊有複數個半導體元件，而使該複數個半導體元件之 24
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