TWI267858B - A method and apparatus for improving stability of a 6T CMOS SRAM cell - Google Patents

A method and apparatus for improving stability of a 6T CMOS SRAM cell Download PDF

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TWI267858B
TWI267858B TW093114516A TW93114516A TWI267858B TW I267858 B TWI267858 B TW I267858B TW 093114516 A TW093114516 A TW 093114516A TW 93114516 A TW93114516 A TW 93114516A TW I267858 B TWI267858 B TW I267858B
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gate
pull
sram cell
wings
wing
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TW093114516A
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TW200514082A (en
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Suman Datta
Brian S Doyle
Robert S Chau
Jack Kavalieros
Bo Zheng
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Intel Corp
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    • H01L29/772—Field effect transistors
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Description

1267858 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體積體電路設計及製造領域，且更特 定言之，本發明係關於一種使用三閘極完全耗盡基板電晶 件之具有六個電晶件（6T)的CMOS SRAM單元及其製造方 法。 【先前技術】 隨著矽技術一代接一代不斷地#展，最小幾何尺寸體積 (bulk)平面電晶件中之固有臨限電壓（Vt)變化的影響減少 了 CMOS SRAM單元靜態雜訊容限（SNM)。此由愈加變小之 電晶件幾何所引起之SNM的減少係非吾人所要的。當Vcc 按比例減少至一較低電壓時，可進一步減少SNM。 平面電晶件中之臨限電壓（Vt)變化主要由該等電晶件之 耗盡區域中的摻雜原子的數目及/或位置的統計變動而產 生。該等Vt變化對供給電壓之縮放比例、電晶件尺寸造成 了障礙，且因此對最小之具有6個電晶件（6T)的CMOS SRAM單元尺寸造成了障礙。此由於晶粒尺寸及成本約束而 限制了受控於習知6T SRAM之高性能CMOS ASIC及微處理 器的總電晶件。 目前，可藉由以下任一途徑在電路/佈局方面解決由 SRAM單元電晶件之Vt不穩定性而導致SNM減少的問題： (a)增加為用以操作該單元所必需的最小供給電壓（Vccmin) 並保持最小幾何尺寸電晶件，或（b)增加單元電晶件之通道 長度與寬度以在損害最小單元尺寸的情況下啓用一較低之 93448.doc 1267858 最小操作電壓。在設備水平方面，在平面設備中，在損害 額外製造過程複雜性的情況下，可藉由盒狀井或超急劇倒 退井（suPer_SteeP retrograde well)來最小化由隨機摻雜變動 (RDF)之Vt失配。 圖1中說明了一使用平面電晶件之6T CMOS SRAM單元 電路圖。該SRAM單元由兩個N型存取設備1〇2、兩個1^型下 拉設備104及兩個P型上拉設備1〇6組成。
圖2說明了 一使用平面電晶件之6t CM〇s Sram單元的 佈局。每一存取設備之閘極位於區域2〇2中。每一下拉設備 之閘極位於區域204中。每一上拉設備之閘極位於區域2〇6 中。藉由位於P型擴散區域212或N型擴散區域2 1 〇上的多晶 矽區域214來指示該等閘極區域。金屬層218提供功率（v⑶） 及接地（Vss)。金屬層218亦可將該單元中之一平面電晶件的 閘極/源極/汲極連接至該單元中之另一電晶件的閘極/源極 /汲極，且可將一單元互連至另一單元。接觸216指示其中 可與金屬層連接的區域。對於一給定Vcc，藉由設定每一存 取電B曰件寬度的尺寸及每一下拉電晶件寬度的尺寸來修整 單元比率以達成最大SNM值。
圖3為一曲線圖300，其說明了供給電壓計數（scaiing)對使 用平面電晶件之典型6T CMOS SRAM單元的影響。雜訊容 限值假定標稱臨限電壓、標稱Vcc及標稱設備尺寸。虛線31〇 指不SNM之最小所要值（24〇 mV)。該曲線圖展示了當vcc 自2 V按比例降低至小於i ^寺，該單元比率必須增加以維 持一所要的SNM值。對於丨_5之單元比率（3〇2)，當維持24〇 mV 93448.doc 1267858 之標稱SNM時能達成之最小電壓略低於2〇v。當將該單元 比率增加至2.0(304)時，當維持一標稱議時能達成之最小 電壓小於15 V。若將該單元比率增加至35(3〇6)，則最小 電麼可降低至小於i.OVL增加該單元比率對應於— 呈增加單元尺寸之形式的區域損失。 【發明内容】 本發明係一種互補金氧半導體靜態隨機存取記憶體 (CMOS SRAM)單元’包含：兩個存取設傷，每一存取設備 各由一具有一單翼板之三閘極電晶件組成；兩個上拉設 備，每-上拉設備各由-具有—單翼板之三閘極電晶件組 成；及兩個下拉設備，每一下拉設備各由一個具有多個翼 板之三閘極電晶件組成。本發明亦提供了 —種用於製造 CMOS SRAM單元(包錢翼板三閘極電晶件)之方法。 【實施方式】 本發明係關於-使用非平面三閑極電晶件之6丁 cm〇s SRAM單元及其製造方法。在以下描述中，闡述了大量特定 細郎以提供對本發明之詳盡的理解。在其它情況中，並未 特別詳細地描述吾人已知之半導體處理及製造技術，從而 不會對本發明造成不必要的混淆。 本發明利用非平面三閉極電晶件之較高驅動電流性能以 改良6T CMOS SRAM單元之穩定性，從而啓動較低 電壓操作及減少之單元佈局尺寸。多翼板組態中之； =件能對一給定佈局寬度輸送比—平面電晶件更多的驅 動電流。 93448.doc 1267858 圖4說明了典型單翼板三閘極電晶件4〇〇之橫截面。一個 單翼板三閘極電晶件為一具有單個半導體本體41〇之三閘 極電晶件。該半導體本體亦稱為"半導體翼板，，。該半導體 本體形成於絕緣基板402上。該絕緣基板由一位於矽或其它 半導體基板404上之一内埋氧化物或其它絕緣層4〇6組成。 閘極介電416形成於半導體翼板41〇之頂部上及側面上。閘 極420形成於該閘極介電之頂部上及側面上。該閘極具有一 閘極長度0：^。源極（S)及汲極（D)區域形成於該閘極極之任 一側上的半導體翼板中。 "亥半導體翼板具有頂面412及側面相對之側壁414。該半 導體翼板具有-等於Tsi之高度或厚度。該半導體翼板具有 等於Wsi之寬度。一個單翼板三閘極電晶件之閘極寬等於 形成於半‘體本體上之三個閘極中之每一閘極的閘極寬度 之和，或等於Tsi+Wsi+Tsi。 圖5根據本發明之一實施例說明了 一典型雙翼板三閘極 電晶件500之橫截面。-雙翼板三閘極電晶件為一具有兩個 位於絕緣基板402上之半導體本體（或翼板）41〇之三閘極電 晶件，其中該等兩個翼板中之每-翼板均具有-形成於頂 面及側面相對之側壁上的閘極介電，且每一翼板共享一形 成於閘極介電上及周圍的單閘極。每一半導體翼板具有頂 面化及側面相對之側壁叫。該等半導體翼板被距離㈣ 而隔開。藉由普通微影技術來進行圖案化可允許最小…約 為240 nm雙翼板二閘極電晶件之閘極寬度等於該等兩 個半導體本體中之每一半導體本體的閘極寬度之和，或等 93448.doc 1267858 於[2(Tsil) + (Wsil)] +[2(Tsi2)+(Wsi2)]。若以每一半導體本體 具有大體上相似尺度之方法來形成半導體本體，則一雙翼 板三閘極電晶件之閘極寬度可有效地為一單翼板三閘極電 晶件之閘極寬度的兩倍。可藉由將額外翼板添加至一三閑 極電晶件來進一步增加該三'閘極電晶件之閘極寬度。因為 一具有與一平面電晶件相同尺寸之三閘極電晶件將具有— 更大的閘極寬度，所以一多翼板組態中之三閘極電晶件能 對一給定佈局寬度輸送比一平面電晶件更多的驅動電流。 圖6根據本發明之一實施例說明了 一使用三閘極電晶件 之6T CMOS SRAM單元電路圖。該SRAM單元由兩個N型存 取設備（602)、兩個N型下拉設備（6〇4)及兩個p型上拉設備 (606)組成。每一N型存取設備6〇2為一單翼板三閘極電晶 件。每一 P型上拉設備606為一單翼板三閘極電晶件。每一 n 型下拉設備604為一雙翼板三閘極電晶件。將一雙翼板三閘 極電晶件用作τ拉設備允許—電路設計者達成該SUM單 元之-較高單元比率。該雙翼板三閘極電晶件將輸送比該 單翼板三閘極電晶件更多的電流，從而增加單元比率，而 不會增加單元佈局尺寸。 將SRAM單元之單元比率界定為該下㈣型電晶件之轉 導因子與該存㈣型電晶件之轉導因子的比率。—電晶件之 轉=子等於閘極寬度與閘極長度之比率乘以遷移:及閘 極容量。當存取及下拉設狀遷移率及閘極容量恒定時， 轉導因子變成電晶件間極寬度與電晶件閘極長度的比率。 因為在相同佈局區域内雙翼板三閉極電晶件之電晶件閉極 93448.doc -10- 1267858 寬度比平面電晶件之間極寬度大，所以該雙翼板三 晶件之轉導因子將比該平面電晶件之轉導因子大。 因為雙翼板設備之閘極寬度與間極長度之比率將 設備之閘極寬度與閘極長度 、做 负度之比率大，所以該雙翼板三間 極電晶件之轉導因子蔣:g锻 ❹ung早翼板三閘極電晶件之 子大据將—雙翼板三閉極電晶件用作下拉設備會增加該下 拉設'之轉導因子，從而增加SRAM單元之單元比率。如上 所述’‘藉由增加單元比率爽 ^ 术達成較兩且因此更為吾人所 要之靜態噪聲容（SNM)位準。 L 平將非千面三閘極電晶件用於 設計SRAM單元能允許在 、………“σ 5亥物理單元佈局尺寸的情 況下增加早7L比率。表丨（如 ^ Μ馮關於一使用平面電晶件 之S AM早兀的單元比率一
扣一 — 便用二閘極電晶件之SRAM 早兀的早兀比率的對比，直 佈局區域。 -中母— MM單元均具有相同的 平面SRAM單元 三閘極SRAM單元 注意：每_ 早兀 表1 单元比率=1 5 單元比率=2 15 j晶件 互導 下拉 1.6 存取 1.1 1.3 下拉 60 存取 2.8 ^上拉 3.0 良域均相同 圖7根據本發明之—實施例說明了-使用三閘極電晶件 93448.doc -11 - 1267858 之6T CMOS SRAM單元佈局。每一存取設備之閘極位於區 域702中。每一下拉設備之閘極位於區域7〇4中。每一下拉 設備為一雙翼板設備。該設備之每一翼板由位於犧牲區塊 709之任一側上的區域7〇8指示。將犧牲區塊7〇9用於形成彼 此緊密接近的翼板。使用犧牲區塊能允許該等翼板彼此之 間的間隔小於1 〇〇 nm，而使用傳統微影技術將不可能達成 此。每一上拉設備之閘極位於區域7〇6中。藉由位於p型擴 月欠區域712或N型擴散區域710之上的多晶石夕區域714來指示 該等閘極區域。金屬層718提供功率（乂(^)及接地（乂88)。金 屬層71 8亦可將該單元中之一平面電晶件的閘極/源極/汲極 連接至該單元中之另一電晶件的閘極/源極/汲極，且可將一 SRAM單元連接至另一 SRAM單元。接觸716指示其中可與 金屬層連接的區域。對一給定Vcc，藉由設定每一存取電晶 件及每一下拉電晶件之閘極寬度來修整單元比率以達成最 大SNM值。如上所述，將一；^型雙翼板三閘極設備用作下拉 設備及並將一N型單翼板三閘極設備用作存取設備，此將允 許三閘極SRAM單元被設計成在與—平面沾趟單元相同 的佈局區域中具有一較高單元比率。 圖8為在相同佈局區域中之一 to . Λ τ ^ 很據本發明之一實施例之 雙翼板三閘極電晶件的閘極寬声盘 ^ π炫見度與一平面電晶件的閘極寬 度的對比。橫截面800展示了 一來出^ μ α 心成於絕緣基板808上的雙 翼板二閘極電晶件。藉由半導體本 π版不體802形成該三閘極電晶 件之翼板。精由距離（Ds)來隔間兮榮塑1 ^木丨网開4荨翼板，該距離（Ds)由上 述犧牲區塊之寬度來確定。可兹 了错由可予以圖案化之最小微 93448.doc -12- 1267858 影特徵尺寸來界定距離（Ds)。閘極介電804覆蓋了位於該閘 極區域中之三閘極電晶件的每一翼板。在每一半導體翼板 與閘極介電層上及周圍形成了閘極806。為該雙翼板三閘極 電晶件之每一翼板形成了三個閘極G卜G2及G3。所形成之 每一閘極具有一閘極寬度。G1之閘極寬度等於Z1或該翼板 之高度。G2之閘極寬度等於Z2或該翼板之寬度。G3之閘極 寬度等於Z3或該翼板之高度。每一翼板之總閘極寬度等於 Z1+Z2+Z3 〇對一雙翼板三閘極電晶件而言，該總閘極寬度 等於2(Z1+Z2+Z3)。一具有N個翼板之三閘極電晶件具有一 等於N(Z1+Z2+Z3)之總閘極寬度。在本發明之一實施例 中，Z1 =60 nm，Z2 = 60 nm，Z3 = 60 nm且 Ds = 60 nm 〇 根據此 實施例，該三閘極電晶件之閘極寬度為2(60 nm+60 nm+60 nm)或3 60 nm。所使用之總佈局寬度等於Z3+DS+Z3或（60 nm+60 nm+60 nm)=180 nm 〇 橫截面820展示了 一形成於半導體基板828上的平面電晶 件。該平面電晶件之閘極寬度等於電晶件閘極822之寬度或 Zp。對於180 nm之佈局寬度而言，平面電晶件820之閘極寬 度等於1 80 nm。因為對於相同佈局區域而言，該三閘極電 晶件之閘極寬度為該平面電晶件之閘極寬度的兩倍，所以 根據本發明之一實施例，可藉由使用單及雙翼板三閘極電 晶件設計一 6T CMOS SRAM單元，來增加該單元之單元比 率。 圖9為一曲線圖900，其說明了作為用於平面SRAM單元 920及三閘極SRAM單元910之VCC的函數的靜態雜訊容限 93448.doc -13- 1267858 (SNM) ’其中該等單元具有相同尺寸。一個三閘極sram單 凡叹计將允許在超出240 mV(930)之較低SNM限度之前具 有VCC之較低計數。因為根據本發明之一實施例，當使用 二閘極電晶件來設計SRAM單元時，該單元比率較高，所以 月b在不將SNM減少至低於240 mV的情況下來將供給電壓縮 J至#乂低。在不將SNM減少至小於240 mV的情況下，能在 一略小於2.0 V之供給電壓下來操作一使用平面電晶件而設 。十成的SRAM單το。根據本發明之一實施例，可在達到§ΝΜ 阳度之刖在低得多的供給電壓下來操作一具有相同尺寸 但為使用雙或單翼板三閘極電晶件而設計成的sram單 元。該供給電壓可在SNM減少至小於24〇mVi前低至丨乃乂。 圖10為一流程圖1000，其展示了一根據本發明之過程， 八次明了 一用於形成一具有一減少之佈局寬度的多翼板三 閘極電晶件之普遍方法，以下進—步細節將結合圖nA」u 一起說明並描述流程圖1 〇〇〇中之每一區塊。 如區塊1002中所述，—個石夕或半導體薄膜形成於-絕緣 基板上。制緣基板包括—較低之單晶基板及—頂部絕緣 層’諸如二氧切薄膜或氮切薄膜。該絕緣層有時稱 為"内埋氧化物”層。在本發明之—實施例中，該半導體薄 膜具有60 nm之厚度。 如區塊1004中所述，—具有一頂面及側面相對之側壁的 犧牲區塊接著形成於該半導體薄膜上。在本發明之一實施 例中’藉由首先形成-層犧牲材料並使用微影技術來圖案 化該犧牲材料以形成-區塊，來形成該犧牲區塊。該犧牲 93448.doc -14- 1267858 區塊可由氮化物組成，但其並不僅限於氮化物。犧牲區塊 之寬度確定了該等翼板之間隔。在本發明之一實施例中，A 犧牲區塊之側面相對的側壁相隔60 nm。在本發明之另一實 施例中，藉由一距離來隔開該犧牲區塊之側面相對的側 壁，該距離由可使用微影技術來形成之最小特徵尺寸界定。 如區塊1006中所述，在形成了犧牲區塊之後，將一絕緣 層形成於該犧牲區塊及該半導體薄膜上及周圍。該絕緣層 可由一種氧化物或其它絕緣材料組成。沈積該絕緣層以使 該層之厚度約等於所要之半導體翼板寬度。在本發明之一 實施例中，絕緣層之厚度在4〇至8〇11111之間。在本發明之另 一貫施例中，該絕緣層之厚度為6〇 nm ° 如區塊1008中所述，接著藉由在絕緣層上執行一各向異 性蝕刻而將絕緣間隔物形成於犧牲區塊之任一側上。在完 成各向異性蝕刻之後，絕緣間隔物將保留於犧牲區塊之任 側上。該等絕緣間隔物之寬度將等於原始絕緣層之厚 度。在本發明之一實施例中，該等絕緣間隔物寬度為6〇nm。 在本發明之另一實施例中，可形成多個犧牲區塊以形成 額外間隔物。可使用此方法來形成-具有兩個以上翼板之 三閘極電晶件。所形成之翼板的數目將等於絕緣間隔物的 數目。在本發明之-實施例中，可形成偶數（2N)個翼板。 為形成一具有2N個翼板之三閘極電晶件，需要N個犧牲區 塊及2N個絕緣間隔物。 %如區塊1010中所示，在形成了絕緣間隔物之後，可藉由 白知方法來移除該犧牲區塊。例如，可使用—選擇性姓刻 93448.doc 1267858 過％來移除該犧牲區塊，同時使絕緣間隔物保存完好。 接下來，如區塊1()12中所示，藉由將絕緣間隔物用作為 一遮罩來蝕刻半導體薄膜，來形成兩個半導體翼板。在未 被=緣間隔物覆蓋之區域中將該半導體薄膜㈣掉，從而 曝露該絕緣基板。所形成之每一半導體翼板具有一頂面及 -對側面相對之侧壁。將該等絕緣間隔物用作一遮罩可允 =藉由-距離來隔開該等翼板，該距離小於可使用當前微 影技術而達成之距離。當前微影技術允許對特徵部分進行 印刷，該等特徵部分具有接近於6Gnm之最小尺寸且在特徵 部分之間具有接近於24〇 nm之最小間隔。使用根據本發明 之方法的一實施例，可形成間隔小於24〇 nm的翼板。在本 發明之一㈣例中，藉由6〇_或更小之距離來隔開該等翼 板0 一實施例之雙翼板三閘 雙翼板三閘極電晶件之 圖ΠΑ至11J說明了根據本發明之 極電晶件的形成。如圖11A中所示， 製造自絕緣基板m2開始。將—㈣或半導體薄膜形 成於絕緣基板1102上。絕緣基板11〇2可由一較低之單晶基 由梦或另 板1HM及-頂部絕緣層蘭組成，諸如—個二氧化石夕或氮 化矽薄膜。絕緣層11〇6將半導體薄膜ιι〇8與基板11〇4分 離，且有時將其稱為”内埋氧化物"層。半導體薄膜謂可 一半導體組成，諸如（但不限於）鍺（Ge)、矽鍺合金 (SixGey)、砷化鎵（GaAs)、銻化銦（InSb)、燐化鎵⑴"卜銻 化鎵（GaSb)或碳毫微電子管。半導體薄膜11〇8可為一内在 或未摻雜之矽薄膜，或可將其摻雜成具有1>型或n型傳導 93448.doc -16- 1267858 性。形成半導體薄膜π〇8，使其具有一厚度（Tsi)，該厚度 (Tsi)近似等於為隨後所形成之三閘極電晶件之半導體翼板 所要的高度。在本發明之一實施例中該半導體薄膜1108具 有60 nm或更小之厚度。 圖11B說明了位於半導體薄膜11〇8之頂面上的一犧牲區 塊之形成。可藉由習知半導體製造技術來形成該犧牲區 塊，該等技術包括（但不限於）沈積一層犧牲材料11〇9，且隨 後藉由抗蝕劑mi來圖案化該層。可對未被抗蝕劑UUm 覆蓋之犧牲材料進行蝕刻以在該（等）所要位置中形成一個 或多個犧牲區塊。在本發明之一實施例中，犧牲材料丨丨〇9 由一種氮化物組成。待形成之犧牲區塊的寬度（Ws)將界定 三閘極電晶件之半導體翼板的隨後的間隔。在本發明之一 貝施例中，Ws為60 nm或更小。使用犧牲區塊能允許藉由 60 nm或更小之距離來隔開該等半導體翼板，該距離顯著小 於可藉由習知微影技術而達成的特徵之間的距離。 圖11 C說明了絕緣層1112在絕緣區塊111 〇上及周圍且在 半導體薄膜1108之表面上的形成。在本發明之一實施例 中’ 5亥絕緣層由一種氧化物組成。以一種允許絕緣層1 1 1 2 具有一均勻厚度（Τοχ)之方式來沈積該層。在一隨後之處理 步驟中，該絕緣層之厚度將確定該等半導體翼板之寬度。 在本發明之一實施例中，該絕緣層具有60 nm或更小之厚 度。 圖11D說明了絕緣間隔物1114之形成。藉由在圖11C：之絕 緣層1112上執行一各向異性蝕刻來形成絕緣間隔物丨丨14。 93448.doc -17- 1267858 χ種允0午自犧牲區塊111 〇之頂面來全部移除絕緣層但保 隸於犧牲區塊之任一側上的絕緣間隔物⑴4的方式來執 行該各向異性蝕刻。形成具有寬度(w〇x)之絕緣間隔物 ⑴4,該寬度（w〇x)等於圖11C之絕緣薄膜的厚度（τ〇小在 本!，明之一貫施例中，每一絕緣間隔物之寬度(W〇x)為 60 nm或更小。 圖11E說明了在移除犧牲區塊之後所形成的結構。可藉由 習知方法來移除該犧牲區塊，該等方法包括使用—選擇性 蝕刻過程。例如，可使用一濕式蝕刻來移除一種具有犧牲 性質的氮化物區塊，同時該等氧化物間隔物將保持未受該 钱刻過程的影響。移除了犧牲區塊之後，#留兩個絕緣間 隔物1114，其中每一間隔物具有一等於w〇x之寬度。藉由一 等於犧牲區塊之寬度（Ws)的距離來隔開該等間隔物。 圖11F說明了半導體翼板112〇之形成。藉由將絕緣間隔物 1114用作一遮罩來蝕刻半導體薄膜1108，可形成半導體翼 板1120。在本發明之一實施例中，該蝕刻為一電漿乾式蝕 刻過程。對該半導體薄膜進行完全蝕刻，從而曝露絕緣基 板1102之表面。形成具有一寬度（Wsi)之半導體翼板，該寬 度（Wsi)荨於被用作一遮罩之絕緣間隔物的寬度。在本發明 之一實施例中，Wsi為60 nm或更小。藉由一距離（Ds)來隔 開該等半導體翼板，該距離（Ds)等於先前所形成之犧牲區 塊的寬度。在本發明之一實施例中，^為⑼nm或更小。 如圖11G中所述，在形成半導體翼板112〇之後，可藉由習 知技術來移除该專絕緣間隔物。此時，兩個半導體翼板1 1 2 〇 93448.doc 1267858 保留於絕緣基板1102上。半導體翼板1120具有一頂面1121 及側面相對之側壁1123。該設備之總佈局寬度將等於Wsi + Ds+Wsi。在本發明之一實施例中，該設備之總佈局寬度 為180 nm或更小。 圖11H說明了在每一半導體翼板1120之頂面1121上及側 壁1123上形成閘極介電層1122。可藉由仔細地控制該半導 體翼板之角1125的幾何形狀來設計該三閘極電晶件，使其 固有地不受Vt之不穩定性的影響。藉由使該設備之鄰近閘 極Gl、G2與G3(頂部及側面）相交來形成該半導體翼板之 角。因為該三閘極電晶件之角1125首先開啟，所以其確定 了該設備之臨限電壓（Vt)。當僅藉由摻雜物植入來設定vt 日守’在该等推雜物中會存在變動，該等變動又會引起Vt變 動。當控制圓角（corner rounding)時，該三閘極電晶件不依 賴於用以設定Vt之摻雜，且因此可設計該電晶件，使其固 有地不受Vt之不穩定性的影響。矽翼板之圓角主要由閘極 介電形成過程而產生。可在矽翼板之表面及側壁上生長或 沈積閘極介電1122。在本發明之一實施例中，使用原子層 沈積（ALD)來沈積閘極介電層，此允許將圓角控制至原子尺 度。在本發明之一實施例中，該半導體翼板之每一角的彎 曲半徑（R)小於10 nm ° 接下來，如圖1II中所說明，將一閘極材料沈積於每一半 導體翼板之頂面及側壁上及絕緣基板上。圖案化該閘極材 料以將閘極1124形成於該閘極介電層上。 如圖11J中所說明，在形成了該閘極之後，將一對源極/ 93448.doc •19- 1267858 沒極區域形成於每一半導體翼板中，使其位於閘極之相對 側。在本發明之一實施例中，如箭頭11 3 0所說明，藉由在 該半導體本體中植入N型或P型摻雜物來形成源極與汲極區 域。在本發明之實施例中，可在該三閘極設備上執行另外 的操作，該等操作包括（但不限於）··形成頂端或源極/汲極 延展區域、光暈區域、重摻雜之源極/汲極接觸區域，在源 極/汲極及閘極區域上沈積矽，及在源極/汲極及閘極區域上 形成碎化物。 如圖11J中所說明，所得之雙翼板三閘極電晶件之每一半 導體翼板具有一等於2Tsi+Wsi之閘極寬度。該雙翼板三閘 極電晶件之閘極寬度等於每一翼板之閘極寬度的和或 2(2Tsi + Wsi)。可在一具有2Wsi+Dsi佈局寬度的區域中來 製造該設備。在本發明之一實施例中，雙翼板三閘極電晶 件之閘極寬度為360 nm或更小，且該設備形成於一具有 180 nm或更小之佈局寬度的區域中。 在本發明之其它實施例中，可使用上述方法以形成具有 兩個以上之半導體翼板的三閘極電晶件。 【圖式簡單說明】 圖1為一幅關於一使用平面電晶件之先前技術6T CMOS SR AM皁元電路圖的插圖。 圖2為一幅關於一使用平面電晶件之先前技術6丁 cM〇s SRAM單元佈局的插圖。 圖3為一曲線圖，JL今日日7 a 1 7 0
”成明了作為用於改變單元比率之6T SRAM單元的供給電壓之φ鉍a p ^ 包土 <函數的靜態雜訊容限。 93448.doc -20- 1267858 圖4為一個單翼板三閘極電晶件之橫截面圖。 圖5為一個雙翼板三閘極電晶件之橫截面圖。 圖6為一幅關於一具有根據本發明之一實施例之三閘極 電晶件的6T CMOS SRAM單元電路圖的插圖。 圖7為一幅關於一根據本發明之一實施例之使用單翼板 及雙翼板三閘極電晶件的6T CM〇s SRAM單元佈局的插 圖。 圖8為一根據本發明之一實施例之雙翼板三閘極電晶件 與一平面電晶件的閘極寬度的對比。 圖9為一曲線圖，其將作為用於根據本發明之一實施例之 一個二閘極SRAM與用於一個平面SRAM之供給電壓的函 數的SNM進行了比較，其中兩個SRAM均具有相同的佈局區域。 圖10為一流程圖，其描述了根據本發明之一實施例之用 於形成一個雙翼板三閘極電晶件的步驟。 圖11 A-11J說明了根據本發明之一實施例之一個雙翼板 三閘極電晶件的形成。 【主要元件符號說明】 102 N型存取設備 104 N型下拉設備 106 P型上拉設備 110 絕緣區塊 120 半導體翼板 202 區域 204 區域 93448.doc 區域 N型擴散 P型擴散 多晶碎區域 接觸 金屬層 曲線圖 單元比率 φ 單元比率 單元比率 虛線 典型單翼板三閘極電晶件 絕緣基板 半導體基板 絕緣層 半導體本體（半導體翼板） _ 頂面 側面相對之側壁 閘極介電 閘極 典型雙翼板三閘極電晶件 . N型存取設備 _ N型下拉設備 P型上拉設備 -22- 區域 區域 區域 區域 犧牲區塊 N型擴散 P型擴散 多晶碎區域 接觸 金屬層 橫截面 半導體本體 閘極介電 閘極 絕緣基板 橫截面 電晶件閘極 半導體基板 靜態雜訊容限圖 三閘極SRAM單元之Vcc 平面SRAM單元之Vcc Vcc之較低計數 絕緣基板 早晶砍基板 -23- 1267858 1106 . 絕緣層 1108 矽或半導體薄膜 1109 犧牲材料 1110 絕緣區塊 1111 抗蝕劑 1112 絕緣層 1114 絕緣間隔物 1120 半導體翼板 1121 頂面 1122 閘極介電層 1123 側面相對之側壁 1124 閘極 1125 角 1130 箭頭 93448.doc 24-

Claims (1)

1267858 十、申請專利範圍： 1. 一種電路，其包含： 至少一存取設備，該至少一存取設備由一具有一單翼 板之非平面電晶件組成； 至少一上拉設備，該至少一上拉設備由一具有一單翼 板之非平面電晶件組成；及 至少一下拉設備，該至少一下拉設備由一具有多個翼 板之非平面電晶件組成。 2. 如請求項1之電路，其中該至少一下拉設備由一具有兩個 翼板之非平面三閘極電晶件組成。 3. 如請求項2之電路，其中該非平面三閘極電晶件之兩個翼 板位於彼此相距小於60 nm處。 4. 一種CMOS SRAM單元，其包含： 兩個存取設備，每一存取設備各由一具有一單翼板之 三閘極電晶件組成； 兩個上拉設備，每一上拉設備各由一具有一單翼板之 三閘極電晶件組成； 兩個下拉設備，每一下拉設備各由一具有多個翼板之 二閘極電晶件組成，及 其中該CMOS SRAM單元具有一單元比率、一靜態雜訊 容限（SNM)及一供給電壓。 5. 如請求項4之CMOS SRAM單元，其中每一下拉設備由一 具有兩個翼板之二閘極電晶件組成’每一翼板具有一南 度及一寬度。 93448.doc 1267858 6. 如請求項5之CMOS SRAM單元，其中該等翼板位於彼此 相距小於60 nm處。 7. 如請求項5之CMOS SRAM單元，其中每一翼板之高度為 60 nm 〇 8. 如請求項5之CMOS SRAM單元，其中每一翼板之寬度為 60 nm 〇 9. 如請求項4之CMOS SRAM單元，其中每一三閘極電晶件 包含至少一個角，每個角具有一小於10 nm之彎曲半徑。 10. 如請求項4之CMOS SRAM單元，其中該單元比率大於2.0。 11. 如請求項4之CMOS SRAM單元，其中該靜態雜訊容限 (SNM)大於 240 mV。 12. 如請求項11之CMOS SRAM單元，其中該供給電壓小於 1·5 V。 13. —種CMOS SRAM單元，其包含： 兩個N型存取設備，每一N型存取設備各由一具有一單 翼板之三閘極電晶件組成， 兩個P型上拉設備，每一 P型上拉設備各由一具有一單 翼板之三閘極電晶件組成； 兩個N型下拉設備，每一N型下拉設備各由一具有多個 翼板之三閘極電晶件組成。 14. 如請求項13之CMOS SRAM單元，其中每一N型下拉設備 由一具有兩個翼板之三閘極電晶件組成，每一翼板具有 一高度及一寬度。 15. 如請求項14之CMOS SRAM單元，其中該等翼板位於彼此 93448.doc 1267858 相距小於60 nm處。 I6· —種用於形成一具有6個電晶件（6T)iCM〇s SRAM單元 的方法，其包含： 形成兩個N型存取設備，每一N型存取設備各由一具有 一單翼板之三閘極電晶件組成； 形成兩個P型上拉設備，每一p型上拉設備各由一具有 一單翼板之三閘極電晶件組成； 形成兩個N型下拉設備，每一下拉設備各由一具有 至少兩個翼板之三閘極電晶件組成。 17. —種用於形成一半導體設備之方法，其包含： 在一基板上形成一石夕薄膜； 在口亥石夕薄膜上形成一犧牲區塊，該犧牲區塊具有側面 相對之側壁； 在該犧牲區塊及該矽薄膜上沈積一絕緣層，· 藉由在該絕緣層上執行一各向異性餘刻而在該氮化物 區塊之每一側面相對之側壁上形成一絕緣間隔物； 移除該犧牲區塊； *藉由將該等絕緣間隔物用作—遮罩而㈣穿過該石夕薄 膜至該基板，從而形成兩個矽翼板，其中每一矽翼板具 有一頂面及一雙側面相對之側壁，·及 移除該等絕緣間隔物以曝露每一矽翼板之頂面。 I如請求項17之方法，其中該基板為—絕緣基板。 f 1 7之方法，其中該絕緣層由—種氧化物層組成。 .如請求項17項之方法，其中該矽薄膜之厚度為60·。 93448.doc 1267858 21 ·如請求工苜1 7 、7之方法，其中該犧牲區塊之該等側面相對的 側壁相距60 nm。 2 2 ·如請求工苜1 7 貝17之方法，其中藉由微影技術來界定該犧牲區 塊。 士明求項1 8之方法，其中該犧牲區塊由氮化物組成。 24· 士明求項17之方法，其中該絕緣層之厚度在40 nm與80 nm 之間。 25·如喷求項17之方法，其中該絕緣層之厚度為60 nm。 士明求項17之方法，其中藉由60 nm或更小之一距離來隔 開該等兩個矽翼板。 27·如明求項17之方法，其進一步包含在每一矽翼板之頂面 上及側壁上形成一閘極介電層。 28·如請求項27之方法，其中藉由原子層沈積（ald)來形成該 閘極介電層。 29.如凊求項28之方法，其中每一矽翼板具有至少一個具有 一彎曲半徑之角，藉由該閘極介電層之原子層沈積來界 定該彎曲半徑。 30·如請求項29之方法，其中該彎曲半徑小於1〇11111。 31·如請求項27之方法，其進一步包含在每一矽翼板之頂面 及側壁上及在該絕緣基板上沈積一閘極材料。 32.如請求項31之方法，其進一步包含圖案化該閘極材料以 在該閘極介電層上形成一閘極。 33·如請求項32之方法，其進一步包含在位於該閘極之相對 的側壁上的每一矽翼板中形成一對源極/汲極區域。 93448.doc
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