TWI261906B - Semiconductor device having a wire bond pad and method therefor - Google Patents
Semiconductor device having a wire bond pad and method therefor Download PDFInfo
- Publication number
- TWI261906B TWI261906B TW092105327A TW92105327A TWI261906B TW I261906 B TWI261906 B TW I261906B TW 092105327 A TW092105327 A TW 092105327A TW 92105327 A TW92105327 A TW 92105327A TW I261906 B TWI261906 B TW I261906B
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- layer
- pad
- wire
- passivation layer
- wire bond
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0495—5th Group
- H01L2924/04953—TaN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/097,059 US6614091B1 (en) | 2002-03-13 | 2002-03-13 | Semiconductor device having a wire bond pad and method therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200305267A TW200305267A (en) | 2003-10-16 |
| TWI261906B true TWI261906B (en) | 2006-09-11 |
Family
ID=27765409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092105327A TWI261906B (en) | 2002-03-13 | 2003-03-12 | Semiconductor device having a wire bond pad and method therefor |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US6614091B1 (enExample) |
| EP (1) | EP1483789B1 (enExample) |
| JP (1) | JP4308671B2 (enExample) |
| KR (1) | KR100979080B1 (enExample) |
| CN (1) | CN100461397C (enExample) |
| AU (1) | AU2003218146A1 (enExample) |
| TW (1) | TWI261906B (enExample) |
| WO (1) | WO2003079434A2 (enExample) |
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-
2002
- 2002-03-13 US US10/097,059 patent/US6614091B1/en not_active Expired - Lifetime
-
2003
- 2003-03-12 CN CNB038045214A patent/CN100461397C/zh not_active Expired - Lifetime
- 2003-03-12 EP EP03714137.1A patent/EP1483789B1/en not_active Expired - Lifetime
- 2003-03-12 JP JP2003577330A patent/JP4308671B2/ja not_active Expired - Lifetime
- 2003-03-12 AU AU2003218146A patent/AU2003218146A1/en not_active Abandoned
- 2003-03-12 TW TW092105327A patent/TWI261906B/zh not_active IP Right Cessation
- 2003-03-12 KR KR1020047014382A patent/KR100979080B1/ko not_active Expired - Lifetime
- 2003-03-12 WO PCT/US2003/007783 patent/WO2003079434A2/en not_active Ceased
- 2003-06-24 US US10/606,674 patent/US6846717B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP4308671B2 (ja) | 2009-08-05 |
| KR100979080B1 (ko) | 2010-08-31 |
| CN100461397C (zh) | 2009-02-11 |
| CN1639865A (zh) | 2005-07-13 |
| KR20040088584A (ko) | 2004-10-16 |
| US20030173637A1 (en) | 2003-09-18 |
| AU2003218146A1 (en) | 2003-09-29 |
| EP1483789A2 (en) | 2004-12-08 |
| TW200305267A (en) | 2003-10-16 |
| AU2003218146A8 (en) | 2003-09-29 |
| WO2003079434A3 (en) | 2004-03-11 |
| JP2005520342A (ja) | 2005-07-07 |
| US20040036174A1 (en) | 2004-02-26 |
| US6846717B2 (en) | 2005-01-25 |
| US6614091B1 (en) | 2003-09-02 |
| EP1483789B1 (en) | 2016-11-16 |
| WO2003079434A2 (en) | 2003-09-25 |
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