TWI261867B - SOI substrate and method for manufacturing the same - Google Patents

SOI substrate and method for manufacturing the same Download PDF

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Publication number
TWI261867B
TWI261867B TW094117092A TW94117092A TWI261867B TW I261867 B TWI261867 B TW I261867B TW 094117092 A TW094117092 A TW 094117092A TW 94117092 A TW94117092 A TW 94117092A TW I261867 B TWI261867 B TW I261867B
Authority
TW
Taiwan
Prior art keywords
active layer
substrate
film thickness
thickness
oxide film
Prior art date
Application number
TW094117092A
Other languages
English (en)
Chinese (zh)
Other versions
TW200603247A (en
Inventor
Etsurou Morita
Ritarou Sano
Akihiko Endo
Original Assignee
Sumitomo Mitsubishi Silicon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Mitsubishi Silicon filed Critical Sumitomo Mitsubishi Silicon
Publication of TW200603247A publication Critical patent/TW200603247A/zh
Application granted granted Critical
Publication of TWI261867B publication Critical patent/TWI261867B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
TW094117092A 2004-05-28 2005-05-25 SOI substrate and method for manufacturing the same TWI261867B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004159398A JP4407384B2 (ja) 2004-05-28 2004-05-28 Soi基板の製造方法

Publications (2)

Publication Number Publication Date
TW200603247A TW200603247A (en) 2006-01-16
TWI261867B true TWI261867B (en) 2006-09-11

Family

ID=35451156

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094117092A TWI261867B (en) 2004-05-28 2005-05-25 SOI substrate and method for manufacturing the same

Country Status (6)

Country Link
US (1) US7736998B2 (fr)
EP (1) EP1758168B1 (fr)
JP (1) JP4407384B2 (fr)
CN (1) CN100474594C (fr)
TW (1) TWI261867B (fr)
WO (1) WO2005117123A1 (fr)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
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JP2007317988A (ja) * 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
WO2008081904A1 (fr) * 2006-12-27 2008-07-10 Hitachi Chemical Co., Ltd. Plaque gravée et matériau de base ayant un motif de couche conductrice utilisant la plaque gravée
JP5245380B2 (ja) * 2007-06-21 2013-07-24 信越半導体株式会社 Soiウェーハの製造方法
JP5498670B2 (ja) * 2007-07-13 2014-05-21 株式会社半導体エネルギー研究所 半導体基板の作製方法
TWI437696B (zh) 2007-09-21 2014-05-11 Semiconductor Energy Lab 半導體裝置及其製造方法
JP5250228B2 (ja) * 2007-09-21 2013-07-31 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5452900B2 (ja) * 2007-09-21 2014-03-26 株式会社半導体エネルギー研究所 半導体膜付き基板の作製方法
JP2009094488A (ja) * 2007-09-21 2009-04-30 Semiconductor Energy Lab Co Ltd 半導体膜付き基板の作製方法
JP2009135430A (ja) 2007-10-10 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP5506172B2 (ja) * 2007-10-10 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の作製方法
JP5490393B2 (ja) 2007-10-10 2014-05-14 株式会社半導体エネルギー研究所 半導体基板の製造方法
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
TWI493609B (zh) 2007-10-23 2015-07-21 Semiconductor Energy Lab 半導體基板、顯示面板及顯示裝置的製造方法
JP5248838B2 (ja) * 2007-10-25 2013-07-31 信越化学工業株式会社 半導体基板の製造方法
JP5466410B2 (ja) * 2008-02-14 2014-04-09 信越化学工業株式会社 Soi基板の表面処理方法
US8003483B2 (en) * 2008-03-18 2011-08-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US7749884B2 (en) * 2008-05-06 2010-07-06 Astrowatt, Inc. Method of forming an electronic device using a separation-enhancing species
KR20110028278A (ko) * 2008-05-17 2011-03-17 애스트로와트, 인코포레이티드 분리 기술을 사용하는 전자 디바이스 형성 방법
KR20100009625A (ko) * 2008-05-30 2010-01-28 캐논 아네르바 가부시키가이샤 규소 화합물 형성 방법 및 이의 시스템
FR2938118B1 (fr) * 2008-10-30 2011-04-22 Soitec Silicon On Insulator Procede de fabrication d'un empilement de couches minces semi-conductrices
KR101651206B1 (ko) * 2009-05-26 2016-08-25 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Soi 기판의 제작 방법
US8367519B2 (en) * 2009-12-30 2013-02-05 Memc Electronic Materials, Inc. Method for the preparation of a multi-layered crystalline structure
CN102918336B (zh) 2010-05-12 2016-08-03 布鲁克机械公司 用于低温冷却的系统及方法
US20120129318A1 (en) * 2010-11-24 2012-05-24 Semiconductor Energy Laboratory Co., Ltd. Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate
JP5799740B2 (ja) * 2011-10-17 2015-10-28 信越半導体株式会社 剥離ウェーハの再生加工方法
TWI669760B (zh) * 2011-11-30 2019-08-21 日商半導體能源研究所股份有限公司 半導體裝置的製造方法
CN104040686B (zh) * 2012-01-12 2017-05-24 信越化学工业株式会社 热氧化异种复合基板及其制造方法
CN105990215B (zh) * 2015-03-02 2019-04-26 北大方正集团有限公司 Soi基片的制作方法和soi基片
US10651015B2 (en) 2016-02-12 2020-05-12 Lam Research Corporation Variable depth edge ring for etch uniformity control
FR3051973B1 (fr) 2016-05-24 2018-10-19 X-Fab France Procede de formation de transistors pdsoi et fdsoi sur un meme substrat
US10410832B2 (en) * 2016-08-19 2019-09-10 Lam Research Corporation Control of on-wafer CD uniformity with movable edge ring and gas injection adjustment
CN108695147A (zh) * 2017-04-08 2018-10-23 沈阳硅基科技有限公司 Soi键合硅片的制备方法
JP6834932B2 (ja) * 2017-12-19 2021-02-24 株式会社Sumco 貼り合わせウェーハ用の支持基板の製造方法および貼り合わせウェーハの製造方法
JP6525046B1 (ja) * 2017-12-19 2019-06-05 株式会社Sumco 半導体ウェーハの製造方法
CN116053191B (zh) * 2022-12-21 2024-02-09 中环领先半导体科技股份有限公司 一种绝缘体上硅衬底及其制备方法
CN116845027B (zh) * 2023-09-01 2023-11-21 青禾晶元(天津)半导体材料有限公司 一种fd-soi衬底的制备方法及soi器件

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964321A (ja) * 1995-08-24 1997-03-07 Komatsu Electron Metals Co Ltd Soi基板の製造方法
JP3582916B2 (ja) 1995-10-14 2004-10-27 スピードファム株式会社 プラズマエッチング装置
JP3250721B2 (ja) * 1995-12-12 2002-01-28 キヤノン株式会社 Soi基板の製造方法
JPH09260620A (ja) * 1996-03-25 1997-10-03 Shin Etsu Handotai Co Ltd 結合ウエーハの製造方法およびこの方法で製造される結合ウエーハ
US6210593B1 (en) * 1997-02-06 2001-04-03 Matsushita Electric Industrial Co., Ltd. Etching method and etching apparatus
JP3324469B2 (ja) * 1997-09-26 2002-09-17 信越半導体株式会社 Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ
US6331473B1 (en) * 1998-12-29 2001-12-18 Seiko Epson Corporation SOI substrate, method for making the same, semiconductive device and liquid crystal panel using the same
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
CN100454552C (zh) * 2001-07-17 2009-01-21 信越半导体株式会社 贴合晶片的制造方法及贴合晶片、以及贴合soi晶片
US7084046B2 (en) * 2001-11-29 2006-08-01 Shin-Etsu Handotai Co., Ltd. Method of fabricating SOI wafer
JP2003243668A (ja) * 2001-12-12 2003-08-29 Seiko Epson Corp 電気光学装置、液晶装置ならびに投射型表示装置

Also Published As

Publication number Publication date
JP4407384B2 (ja) 2010-02-03
WO2005117123A1 (fr) 2005-12-08
JP2005340622A (ja) 2005-12-08
EP1758168B1 (fr) 2020-02-19
CN100474594C (zh) 2009-04-01
US7736998B2 (en) 2010-06-15
CN1989620A (zh) 2007-06-27
EP1758168A4 (fr) 2012-09-05
TW200603247A (en) 2006-01-16
EP1758168A1 (fr) 2007-02-28
US20080063840A1 (en) 2008-03-13

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