TWI260776B - Epitaxially deposited source/drain - Google Patents

Epitaxially deposited source/drain Download PDF

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TWI260776B
TWI260776B TW093132256A TW93132256A TWI260776B TW I260776 B TWI260776 B TW I260776B TW 093132256 A TW093132256 A TW 093132256A TW 93132256 A TW93132256 A TW 93132256A TW I260776 B TWI260776 B TW I260776B
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gate electrode
transistor
source
forming
thickness
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TW093132256A
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TW200515596A (en
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Nick Lindert
Anand Murthy
Justin Brask
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1260776 (υ 九、發明說明 t發明所屬之技術領域】 本發明係關於一種金屬氧化半導體場效電晶體。 【先前技術】 金屬氧化半導體場效電晶體包括一閘極，該閘極自動 對齊一源/汲極。此源/汲極可包括一較深或重摻雜區和一 較淺和輕摻雜區，有時稱其爲一尖塞端或源/汲極延伸。 閘極下疊爲在離子植入和後續熱處理後，在閘極下方 ’源/汲極材料擴散的量。在植入後.，所植入的材料曝露 至熱’而此熱會使材料向下和些微程度的側向至閘極下方 的基底。因此，在使用離子植入源/汲極延伸的系統中， 下擴散的量受決定當成接面深度的函數。 於此所需的是源/汲極延伸具有相當淺的接面深度以 支持較小電晶體尺寸。通常，在源/汲極延伸植入技術中 ，極小尖塞端接面深度乃由必需的閘極下疊所決定。 一般而言，源/汲極延伸愈淺，可使用而不會增加關 斷狀態漏電流的閘極長度愈短。在閘極邊緣下方的延伸摻 雜需用以確保介於在閘極下方的相反層和高摻雜源/汲極 延伸區間的低電阻路徑。對於高電路開關速度相當重要的 高驅動電流而言，需要低電阻。 因此，於此需要較佳的方式以製造場效電晶體的源/ 汲極接面。 (2) 1260776 【發明內容和實施方式】 參考圖1，一重摻雜半導體基底12可由一犧牲、未 摻雜、或輕摻雜磊晶矽層1 8所覆蓋。在一實施例中，此 層1 8可小於5 00A厚。包括形成在一閘極介電14上的閘 極1 6的閘極電極構造可界定在磊晶矽層1 8上。 犧牲磊晶矽層1 8的選擇性沉積可使用、例如、二氯 矽烷基化學物在一單晶圓化學蒸氣沉積處理器、如 Epsilon3 000 磊晶處理器、由荷蘭 ASM International NV， Bilthoven，所製造，而執行。此膜可以1 5 0-200 seem的 二氯矽烷，1 00- 1 5 0 seem的HC1，20 slm的H2的氣體流 量，在8 3 5 °C，在20 Torr的處理壓力下沉積。在此處理 條件下，可在曝露基底上達成用於矽的每分鐘10-15奈米 的沉積速率，並達成對間隙壁和氧化區的選擇性。於此亦 可使用其他的沉積技術。 如圖1所示的構造有時稱爲一 δ摻雜電晶體。因此有 相當高的摻雜在磊晶層18下方，因此在介於基底12和磊 晶矽層1 8間的介面上會發生濃度上的大量δ變化或改變。 如圖1所不的構造可由一間隙壁材料所覆蓋，而後各 向異性蝕刻以形成如圖2所示的側壁間隙壁2 8。依照對 間隙壁蝕刻的選擇性，於此亦可能同時發生磊晶矽層18 的部份限制蝕刻。 在間隙壁形成後，一選擇性濕蝕刻可移除磊晶矽層 1 8的曝露部份，且可在閘極1 6下方持續蝕刻以達成如圖 3所示的下切構造。閘極1 6的下切程度可藉由調整蝕刻 -6 - (3) 1260776 時間而控制。 磊晶矽層1 8可以、例如、各種氫氧基溶液選擇性蝕 刻。但是，對於未摻雜或輕摻雜層]8對重摻雜基底1 2的 高選擇性，亦可使用相當溫和的處理條件。 在一實施例中，可和音波一起使用在2 0 °C下、濃度 範圍爲2至1 0%重量百分比的氫氧化胺水溶液。在本發明 的一實施例中，可藉由散佈具有每平方公分（cm2) 0.5至5 瓦功率的超或兆音波能量的換能器而提供此音波。由於δ 摻雜電晶體在未摻雜區下方具有一重摻雜區，其可當成用 於濕蝕刻的鈾刻阻止層。 在濕蝕刻下切後，可成長摻雜的選擇性磊晶矽層50 。一淺、重摻雜源/汲極延伸50a側向的延伸所需的距離 在閘極1 6邊緣和側壁間隙壁2 8下方，如圖4所示。一較 厚源/汲極區5 Ob對齊間隙壁2 8的邊緣，且延伸離開間隙 壁28。間隙壁28使延伸50a的長度受到修剪，且使層50 的厚度擴展而不會短於閘極16。此較厚區50b降低區50 的電阻和使較低電阻區接近閘極1 6的邊緣。 在形成P型MOS(PMOS)電晶體時，源/汲極延伸50a 和源/汲極5 Ob可藉由、例如、選擇性沉積磊晶硼摻雜矽 或鍺濃度高達 30%的鍺化矽而形成。在處理條件爲100 seem 的二氯石夕院，20 slm 的 H2，750-800 °C，20Torr， 1 5 0 - 2 0 0 s c c m 的 H C 1，1 5 0 - 2 0 0 s c c m 的乙硼烷流，和 1 5 0 - 2 00 seem的GeH4流下，可達成在一實施例中具有每分鐘 20奈米沉積速率的高摻雜鍺化矽膜，1E20 的硼濃度 1260776 (4) ’和20%的鍺濃度。從膜的高硼濃度可導致ο.? _〇9m Ω · c m的低電阻率。 在部份實施例中，低電阻率提供在延伸和源/汲極區 中的高導電率的優點。此較低的電阻率可降低外部電阻。 在部份實施例中，在源/汲極區5〇b中呈現的鍺化矽的較 大單元胞會對通道作用壓力應變，而其隨後會導致增強移 動率和電晶體效能。 在N型電晶體（NMOS)中，源/汲極50b和源/汲極延 伸5 0a可使用沉積在一實施例中的磷摻雜矽而形成在原處 。此矽可選擇.性沉積在1 00 seem的二氯矽烷，25 -5 0 seem 的 HC1，以 20 $1111的 H2 氣體載流的 200-300 seem 的 1°/。 PH3，在7 5 0 °C，20 Torr壓力的處理條件下。在一實施例 中，在沉積膜中可達成具有 0.4-0.6 mQ-cm的電阻率的 2E20 cnT3的磷濃度。 而後，如圖5所示，使用習知技藝而形成第二薄間隙 壁3 4。藉由離子植入，使用間隙壁2 8和3 4和閘極1 6當 成掩模，可形成一深源/汲極32。以和降低或減少包括在 層5 0中的摻雜劑的摻雜劑擴散的方式，可達成深源/汲極 3 2的退火。 淺源/汲極延伸5 0a的特性和它們下疊閘極1 6的程度 可和深源/汲極接面32的特性無關。源/汲極延伸50a的 閘極1 6的延伸下疊的程度可依需要受到控制。 本發明並不限於上述之實施例，且於此仍可達成各種 改變和修飾，但其仍屬本發明之精神和範疇。因此，本發 -8- (5) 1260776 明之精神和範疇應由下述申請專利範圍界定之。 【圖式簡單說明】 圖1爲在一製造階段上的較大擴大橫截面圖； 圖2爲在依照本發明的一實施例的一後續製造階段上 的擴大橫截面圖； 圖3爲在依照本發明的一實施例的又一後續製造階段 上的擴大橫截面圖； 圖4爲在依照本發明的一實施例的一後續製造階段上 的擴大橫截面圖；和 圖5爲在依照本發明的一實施例的又一後續製造階段 上的擴大橫截面圖。 【主要元件符號說明】 12 半導體基底 18 磊晶矽層 16 閘極 14 閘極介電層 28 側壁間隙壁 5 0 嘉晶砂層 5 0 a 延伸 5 0 b厚區 3 4 第二薄間隙壁 32 深源/汲極 -9-

Claims (1)

  1. (1) 1260776 十、申請專利範圍 1 · 一種場效電晶體的形成方法，包含： 形成一金屬氧化半導體場效電晶體，該金屬氧化半導 體場效電晶體具有一磊晶沉積源/汲極以延伸在一閘極電 極之邊緣下方， 其中該電晶體爲一 δ摻雜電晶體。 2 ·如申請專利範圍第1項的方法，該方法包括形成一 源/汲極延伸以延伸在一閘極電極之邊緣下方。 3 .如申請專利範圍第〗項的方法，該方法包括形成一 犧牲嘉晶沉積材料在一基底上，和形成一閘極電極在該磊 晶丨几積層上。 4.如申請專利範圍第3項的方法，其中形成一犧牲磊 晶沉積材料包括磊晶沉積一矽材料。 5·如申請專利範圍第3項的方法，該方法包括選擇性 的蝕刻該磊晶沉積材料。 6.如申請專利範圍第5項的方法，該方法包括使用音 波以選擇性的鈾刻該材料。 7·如申請專利範圍第3項的方法，該方法包括形成一 側壁間隙壁在該閘極電極上和在該側壁間隙壁下方鈾刻。 8 .如申Μ專利範圍第5項的方法，該方法包括選擇性 的鈾刻該磊晶沉積材料以下切該閘極電極。 9.如申請專利範圍第8項的方法，該方法包括沉積一 嘉晶材料在該基底上和在該閘極電極下方延伸。 1 〇.如申請專利範圍第9項的方法，該方法包括形成 -10 - 1260776 (2) 一丨爹雜嘉晶材料。 1 1 ·如申請專利範圍第8項的方法，該方法包括形成 6亥嘉晶材料在接近閘極電極處較薄和隔開該閘極電極處較 厚。 12·一種場效電晶體，包含： 一基底； -ί參雜嘉晶半導體材料形成在該基底上；和 -鬧極電極形成在該摻雜磊晶半導體材料上，該摻雜 嘉晶半導體材料在該閘極電極下方延伸， 其中該電晶體爲一 δ摻雜電晶體。 1 3 .如申請專利範圍第1 2項的電晶體，該電晶體包括 一源/汲極具有一源/汲極延伸，該源/汲極延伸以該摻雜磊 晶半導體材料形成且在閘極電極之邊緣下方延伸。 1 4 ·如申請專利範圍第1 3項的電晶體，其中該材料在 接近該閘極電極處具有第一厚度和隔開該閘極電極處具有 第二厚度，該第二厚度大於第一厚度。 1 5 ·如申請專利範圍第1 4項的電晶體，該電晶體包括 一側壁間隙壁，該材料在該側壁間隙壁下方延伸。 1 6 ·如申請專利範圍第1 5項的電晶體，其中該第二厚 度對齊該側壁間隙壁。 1 7 .如申請專利範圍第1 2項的電晶體，該電晶體包括 一離子植入源/汲極在該摻雜磊晶半導體材料下方。 -11 - 1260776 (3) 18.—種場效電晶體的形成方法，包含： 形成一磊晶半導體層在一半導體基底上，其中該磊晶 半導體層具有比基底低的摻雜濃度； 形成一閘極構造，包括一閘極電極和一側壁間隙壁在 該磊晶半導體層上方；和 選擇性蝕刻該磊晶半導體層的曝露部份以及在閘極電 極下方的該磊晶半導體層的部份。 1 9·如申請專利範圍第1 8項的方法，該方法包括磊晶 沉積一摻雜半導體材料在該基底上以充塡在該閘極電極下 方和該側壁間隙壁下方的區域。 20.如申請專利範圍第19項的方法，其中該磊晶半導 體層在閘極電極下方具有第一厚度和與閘極電極隔開處具 有第二厚度。 2 1 .如申請專利範圍第20項的方法，該方法包括形成 第二厚度對齊該間隙壁。 22.如申請專利範圍第1 8項的方法，該方法包括以離 子植入形成一深源/汲極區。 23 ·如申請專利範圍第1 8項的方法，該方法包括形成 該磊晶半導體層延伸在該閘極電極下方，且在該閘極電極 外側具有較大厚度，而在閘極電極下方具有較小厚度。 -12 - 1260776 七、指定代表圖 (一）、本案指定代表圖為：第（5)圖 (二） 、本代表圖之元件代表符號簡單說明： 12 半導體基底 16 閘極 28 側壁間隙壁 32 深源/汲極 3 4 第二薄間隙壁 5 0 聶晶砂層 5 0 a延伸 50b厚區 八、本案若有化學式時，請揭示最能顯示發明特徵的化學 式：無
TW093132256A 2003-10-24 2004-10-22 Epitaxially deposited source/drain TWI260776B (en)

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US7060576B2 (en) 2006-06-13
US20050087801A1 (en) 2005-04-28
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TW200515596A (en) 2005-05-01
US20060197164A1 (en) 2006-09-07
CN1898785A (zh) 2007-01-17
DE112004002017B4 (de) 2009-03-05
DE112004002017T5 (de) 2006-08-31
KR100841806B1 (ko) 2008-06-26
CN1898785B (zh) 2011-09-07

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