TW432457B - Semiconductor device with selective epitaxial growth layer - Google Patents

Abstract

Disclosed is a method of moving a production process of a lightly doped region and a halo region to let it be later than the annealing of the source/drain. This method makes the junction depth of the lightly doped drain become shallow which has a good effect on the short channel effect of the device. The method comprises using a semiconductor substrate; sequentially forming a gate oxide layer and a polysilicon layer on the semiconductor substrate; etching the polysilicon layer and the gate oxide layer to form a gate structure; depositing an uniform dielectric layer on the gate structure and the semiconductor substrate; etching back the dielectric layer to form a dielectric spacer on both sides of the gate structure; using the gate structure and the dielectric spacer as the hard mask and implanting a first ion inside the semiconductor substrate to form a source/drain region; selectively forming a conductive layer on the gate structure and the source/drain region; forming a self-aligned silicide on the conductive layer; removing the dielectric spacer on both sides of the gate structure; vertically implanting a second ion inside the semiconductor substrate to form a lightly doped drain region; and implanting a third ion inside the semiconductor substrate at a tilting angle where the third ion is formed below the lightly doped drain region and surrounding the lightly doped drain region to form a halo region.

Description

V. Description of the invention (1) '1 ~ · 5-1 Field of invention: The present invention relates to a seven-structure of a metal oxide semiconductor field effect transistor, and particularly to a lightly doped drain and halo After the region (ha 1 〇reg i on) process is moved to source / drain tempering, this method makes the lightly doped drain junction depth shallower, which has a good effect on the short channel effect of the device. effect. — BACKGROUND OF THE INVENTION: '3Recently' The demand for semiconductor components has increased rapidly due to the large number of electronic components used. In particular, the rapid spread of computers has increased the demand for semiconductor components. Metal halide semiconductor field effect transistors are of great importance for very large integrated circuits such as microprocessors and semiconductor memories. Metal oxide semiconductor field effect transistors are already an important power element. Since complex circuits with hundreds or thousands of transistors are required to be fabricated on a single half-conductor wafer, it is important to reduce the device size and provide a semiconductor device with an improved method of selective epitaxial growth (SEG). In the element size less than 0 1 3 // m, the extension of the source / drain structure () (lightly doped drain) must be controlled to less than 50nm, and the junction / source junction depth) must also be less than 150 nm. However, in the subsequent self-aligned metal silicide process, the metal silicide will react with the stone at the source / wave electrode, resulting in junction drag (j u n c t i ο η

Page 5 5. Description of Invention (2) 1 eakage). In order to solve this problem, it is important to add a selective epitaxial growth layer (SEG) after the source / drain region is formed and before the formation of the self-metal silicide. It is used as a sacrificial layer to react with the metal silicide in the subsequent processes, but the selective epitaxial growth layer (SEG) itself has a problem of poor selectivity, which affects the quality and production line of the device. However, as devices become smaller and smaller, the distance between lightly doped drains will be closer and closer. After the source / drain tempering process, the lightly doped drain regions will diffuse to both sides of the channel. This leads to short-channel effects, which cause leakage & current. 5-3 Objects and Summary of the Invention: In the background of the invention described above, many shortcomings of the existing metal oxide semiconductor field-effect transistors, the main purpose of the present invention is to lightly doped anodes and halo regions (halo After the region (region) process is moved to the source / drain loopback, this method makes the lightly doped drain junction depth shallower, which has a very bad effect on the short channel effect of the device. By using this invention technology, the size can be made smaller than 0 micron in the process. Another object of the present invention is to provide a metal oxide semiconductor field effect transistor. The oxidation barrier wall can completely erode, so the distance between the gate structure and the drain / drain can be extended, and bridging can be suppressed.

432457 V. Description of the invention In order to overcome the phenomenon of selective epitaxial growth (SEG) phenomena), because of the problem of poor selectivity. Another purpose of Xinxinyue is to provide a kind of metal oxide semiconductor field-effect electric power b-body, adding a selective epitaxial growth layer (SEG) as a sacrificial layer, so that the selective epitaxial growth layer and the subsequent process The metal silicide reacts without affecting the junction depth of the source / drain region, resulting in the generation of junction leakage. According to the above-mentioned object, the present invention provides a metal oxide semiconductor field effect transistor structure of a selective epitaxial growth layer (SEG) as a sacrificial layer by adding a selective epitaxial growth layer (SEG) to enable selective epitaxy. The growth layer reacts with the metal silicide in subsequent processes without affecting the junction depth of the source / inverter region, resulting in the generation of junction leakage, which includes a semiconductor substrate. A gate oxide layer and a polycrystalline sand layer are sequentially formed over the semiconductor substrate. Then, the polycrystalline silicon layer and the gate oxide layer are etched to form a gate structure. A uniform dielectric layer is deposited over the gate structure and the semiconductor substrate, and then the dielectric layer is etched by an etch-back method to form a dielectric spacer on both sides of the gate structure. The gate structure and the dielectric spacer are used as a hard mask, and the first ion is implanted inside the semiconductor substrate to form a source / drain region. Furthermore, a conductive layer is selectively formed over the gate structure and the source / drain regions. Thereafter, a self-aligned metal silicide layer is formed over the conductive layer, and then the dielectric spacers on both sides of the gate structure are removed. Next, a second ion is implanted vertically inside the semiconductor substrate to shape

Page 7 Fifth, the invention description (4) into the light broadcast miscellaneous. Drain region. Finally, a third ion is implanted at an oblique angle into the semiconductor substrate, and the third ion is formed below the lightly doped region and surrounds the lightly doped drain region to form a halo region (ha j 〇 region). ). 5-4 Brief description of the diagram: The first diagram is a schematic diagram of the steps of the metal oxide semiconductor field effect transistor structure in the embodiment of the present invention, which includes the gate structure, oxidation = gap wall, source / drain and selection Epitaxial growth layer and the shape of metal silicide ^ Brother

θ, and the key steps are the schematic diagrams of the various steps of the cyanide semiconductor structure, including the formation of electricity and the removal of the oxidation barrier. The second picture is the action of each step of the body structure in the embodiment of the present invention. "Lice compound semiconductor field-effect transistor. It is not intended to include a light-emitting hybrid drain. The fourth picture is In the embodiment of the invention, the operation sound of each step of the body structure, the rolling semiconductor semiconductor field effect transistor, and / or the formation of a halo region are included. The representative symbols of the main part · 10 semiconductor substrate > '20 shallow trench Isolation area (30 gate oxide layer

432457 V. Description of the invention (5) 4 0 polycrystalline layer 5 0 oxidation spacer 6 0 source / drain region 70 selective epitaxial growth layer (SEG) 80 self-aligned metal silicide 9 0 lightly doped drain Pole 9 ο I r-type ions 1 0 0 Military area 1 0 0 IP-type ions 5-5 Detailed description of the invention: 0 The first to fourth figures show the decomposition of the metal halide semiconductor field effect transistor structure. In these drawings, the same elements are denoted by the same reference numerals. The first figure shows that the semiconductor substrate 10 is a P-type semiconductor substrate-however, an N-type silicon substrate can also be used. The wafer is sent into the oxidizing furnace tube, and the stone on the surface is oxidized to a thickness of ΠΗ) by the dry oxidation method. The oxidized layer will be the gate oxide layer of each piece. . Next, a low-pressure chemical vapor deposition method is used to deposit a polycrystalline 40 ° C layer with a thickness of about 2000 to 3000 Angstroms. On the surface ... thermal diffusion method or ion implantation; Polycrystalline silicon to reduce gate current

4 3 24 5 7

Resistivity. Next, the wafer is subjected to a lithography process, and a photoresist layer (not shown) is used to define the gate area. Then the wafer is sent to an etching machine 7 and is self-aligned to a reactive ion etching method using an anisotropic rhyme ( self

Reactive etch) etches the polycrystalline silicon layer 40 on the wafer without photoresist protection to form a gate structure. Thereafter, a uniformly-covered oxide layer 50 is deposited on the wafer by chemical vapor deposition (cvd), and the thickness is about 1000-2000 Angstroms. The material is silicon dioxide. (^ 1 ^ (: 1 ^) The oxide layer is etched to form the oxide spacers 50 on both sides of the internal gate. Thereafter, the gate structure 40 and the oxide spacer 50 are used as a mask, and phosphorus or kun is used. ^ Ion source 'implants a high-concentration and deeper-ion ion into the wafer, implanted inside the exposed semiconductor substrate 10 to form a source / drain region 60, with a concentration of about 1015 / cm2. Implantation is called. Next, a selective epitaxial growth SEG (selective epitaxial growth SEG) 1 /!) Is formed on the gate structure 40 and the source / inverted region 60, and the thickness is about 5 〇〇Angles. Because the structure of the gate 40 and the source / polar domain 60 is made of Shi Xi material, when the temperature is higher than 70 0 ° C, the crystal stone Xi (ep i tax ia 1 si 1 i con) will Start to produce. In the embodiment of the present invention, a selective epitaxial growth layer (SEG) 70 is added as a sacrificial layer, so that the selective worm crystal growth layer and the rear The reaction of the metal lithoate in the process does not affect the junction depth of the source / inverter region, resulting in the generation of junction leakage. The second picture is not shown. A layer of metal is deposited by the magnetron DC excitation method Chin (Ti) or cobalt (Co) metal, with a thickness of about 200 to 1,000 angstroms, and then using high temperature, the partially deposited titanium film is selectively epitaxially formed with the drain / source and the gate.

4SE45 on page 10 5. Explanation of the invention (7) The long layer (SEG) 70 reacts to form a cinnamate; ε evening or initiation zone, and titanium that does not participate in the reaction or after the reaction is removed by wet etching. A self-aligned metal silicide layer 80 is formed on the selective epitaxial growth layer (SEG) 70. The selective epitaxial growth layer (SEG) 70 of this device structure will react with the partially deposited titanium film to self-align the metal silicide. Next, the anisotropic etching method is used to remove the oxidation spacers 50 on both sides of the gate structure. In the practice of the present invention, the oxidation spacer 50 is completely removed to overcome the problem caused by the selective epitaxial growth layer (SEG) above the surface of the oxidation spacer structure due to poor selectivity. The third figure shows: using arsenic (As) or phosphorus (p) ions as the ion source, N-type ions are implanted vertically inside the silicon substrate, and the concentration is about 丨 〇u to 1014 / cm2. As a lightly doped drain 90 region, note that the ion concentration of the source / drain 60 region is higher than the lightly doped drain 90 region. Next, using boron ions and fluorinated butterfly ions as ion sources, P-type ions with a concentration of about 10 ls / cm2 to 10 "/ Cffl2 were implanted into the silicon substrate at an oblique angle, and the p-type ions were formed in The lightly doped drain region is below and surrounds the lightly doped drain region to form a halo region as shown in the fourth figure. Its inclination angle is 20 to 30 degrees relative to the vertical plane 2. In the implementation of the present invention The oxidation spacer is completely removed, so the distance between the gate structure and the source / drain can be extended, and the phenomenon of bridging Ό Phenomena can be suppressed to overcome the selective epitaxial growth layer (SEG).

_ 丨 _ ’— page 11. 5. Description of the invention (8) Because of poor selectivity. And in the implementation of the present invention, 'the process of lightly doped drain and halo region (ha 1 〇regi ◦ η) is moved to source / drain tempering, this way makes the lightly doped drain junction depth shallower. Without causing lightly doped diffusion to have a short effect on the short channel effect of the device. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention = patent application; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of patent applications.

Claims (1)

432457 VI. Scope of Patent Application-1 · A method for manufacturing a semiconductor device, including at least the following steps: providing a semiconductor substrate; forming a gate oxide layer over the semiconductor substrate; depositing a polycrystalline oxide layer over the gate oxide layer ; Engraving the polycrystalline stone layer and the gate oxide layer to form a gate structure; depositing a uniformly covering dielectric layer over the gate structure and the semiconductor substrate; etching the dielectric layer using an etch-back method, A dielectric spacer is formed on both sides of the gate structure; using the gate structure and the dielectric spacer as a hard cover, a first 6 ion is implanted inside the semiconductor substrate to form a source / drain Area; selectively forming a conductive layer over the gate structure and source / drain region; forming a self-aligned metal oxide layer over the conductive layer; removing dielectric on both sides of the gate structure A spacer; implanting a second ion into the semiconductor substrate vertically to form a lightly doped drain region, and implanting a third ion into the semiconductor substrate at an oblique angle _ To form a halo region, and the third ion is formed below the lightly doped drain region and surrounds the lightly doped drain region. 〆 2. The method according to item 1 of the scope of the patent application, wherein the dielectric spacer comprises at least silicon dioxide. Page 13 432457 6. Scope of patent application 3. The method according to the member of the scope of patent application ', wherein the above-mentioned conductive layer includes at least a selective epitaxial growth SEG. i 4. The method as described in the scope of the patent application, wherein the selective staggered crystal growth layer described above is at least a vegetarian. 5. The method according to item 1 of the scope of the patent application, wherein the conductive layer has a thickness of about 500 angstroms. 6. The method according to item 1 of the scope of patent application, wherein the inclination angle is about 20 to 30 degrees relative to the vertical plane. 7. The method according to item 1 of the scope of patent application, wherein the third ion system is a P-type ion, which contains at least a boron ion and a boron fluoride ion. 8. The method described in item 7 of the scope of patent application, wherein the above-mentioned third ion implantation concentration is about 丨 〇i3 / cm2 ~ 10 〇H / cm2. 9. The method described in item 1 of the scope of patent application The second ion system is a type ion, which includes at least arsenic ions and phosphorus ions. -1 10. The method according to item 9 of the scope of patent application, wherein the above-mentioned second sub-implantation concentration is about 0.15 / cm2. 43 24 5 7 6. Scope of patent application 1 1. The method described in item 1 of the scope of patent application, wherein the first ion system is an N + ion, which contains at least arsenic ions and phosphorus ions. 12. The method according to item 11 in the scope of patent application, wherein the above-mentioned first ion implantation concentration is about 10t5 / cm2. 1 3. The method according to item 1 in the scope of patent application, wherein the first The ion implantation concentration is greater than the second ion implantation concentration. 1 4. The method according to item 1 of the scope of the patent application, wherein the self-aligned metal silicide layer described above comprises at least cobalt silicide. 1 5. The method as described in item 1 of the scope of patent application, wherein the self-aligning metal fossilization layer includes at least a silicided surface. 1 6. A method for manufacturing a semiconductor device, including at least the following steps: providing a silicon substrate, the silicon substrate directly entering ions; forming a gate oxide layer over the semi-hazardous layer; depositing a polycrystalline oxide layer on the gate oxide Above Zhan; Qian carved the polycrystalline silicon layer and the gate oxide layer to form a gate structure; deposited a uniform covering oxide layer on the gate structure and the silicon substrate; etched the silicon substrate using an etch-back method to form a gate structure Oxidation spacers on both sides of the gate structure; Page 15 432457 VI. Patent application scope Use the gate structure and the oxidation barrier as a hard cover, implant N + ions inside the silicon substrate to form the source / drain region; Selective formation of a selectivity An epitaxial growth layer forms a self-aligned metal dream layer over the gate structure and above the source / anti-polar region. The selective epitaxial growth layer uses anisotropy to remove the two sides of the gate structure. Oxidation barriers · Implantation of ionized ions into the silicon substrate vertically to form a lightly doped doped drain region; and β " Implantation of P-type ions into the silicon substrate at an oblique angle to form halo A halo region, in which the P-type ions are formed below the nudged-drain region and surround the lightly doped drain region. 17. The method according to item 16 of the scope of patent application, wherein the above-mentioned gasification partition wall contains at least silicon dioxide. 18. The method according to item 6 of the patent application scope, wherein the selective worm crystal growth layer described above contains at least silicon element ^ 1 9 · The method according to item 16 of the patent application scope 'where the above option is selected The worm-like crystal growth layer has a thickness of about 50 angstroms. ' 6. Scope of patent application 21. The method according to item 16 of the scope of patent application, wherein the P-type ions mentioned above include at least boron ions and boron fluoride ions. 22. The method according to item 21 of the scope of patent application, wherein the above-mentioned P-type ion implantation concentration is about 1013 / cm2 ~ 1014 / cm2, 23. The method according to item 16 of the scope of patent application, The N-type ion described above includes at least a bell ion and a scale ion. 24. The method according to item 23 of the patent application, wherein the N-type ion implantation concentration is about 1014 / cm2 ~ 1015 / cm2. 25. The method according to item 16 of the patent application, wherein The aforementioned N + type ions include at least god ions and filling ions. 2 6. The method according to item 25 of the scope of patent application, wherein the above N + ion implantation concentration is about 10 5 / cm2. 27. The method according to item 16 of the scope of patent application, wherein The N + -type ion implantation concentration is greater than the r-type ion implantation concentration. 28. The method as described in item 16 of the scope of application for patents, wherein the above-mentioned P-type ion implantation concentration is greater than the silicon substrate implantation ion concentration. Page 17 6. Scope of patent application 29. The method described in item 16 of the scope of patent application, wherein the above-mentioned self-aligned metal stone oxide layer includes at least a stone diamond. 30. The method as described in item 16 of the scope of the patent application, wherein the self-aligned metal debris layer described above includes at least the Shixihua Formation. Page 18