TWI260734B - Architecture for circuit connection of a vertical transistor - Google Patents

Architecture for circuit connection of a vertical transistor Download PDF

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Publication number
TWI260734B
TWI260734B TW090121536A TW90121536A TWI260734B TW I260734 B TWI260734 B TW I260734B TW 090121536 A TW090121536 A TW 090121536A TW 90121536 A TW90121536 A TW 90121536A TW I260734 B TWI260734 B TW I260734B
Authority
TW
Taiwan
Prior art keywords
region
layer
regions
source
field effect
Prior art date
Application number
TW090121536A
Other languages
English (en)
Chinese (zh)
Inventor
Yih-Feng Chyan
John Michael Hergenrother
Donald Paul Monroe
Original Assignee
Agere Syst Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Syst Guardian Corp filed Critical Agere Syst Guardian Corp
Application granted granted Critical
Publication of TWI260734B publication Critical patent/TWI260734B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0195—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10W20/0698—

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW090121536A 2000-08-25 2001-08-29 Architecture for circuit connection of a vertical transistor TWI260734B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/648,164 US6903411B1 (en) 2000-08-25 2000-08-25 Architecture for circuit connection of a vertical transistor

Publications (1)

Publication Number Publication Date
TWI260734B true TWI260734B (en) 2006-08-21

Family

ID=24599689

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090121536A TWI260734B (en) 2000-08-25 2001-08-29 Architecture for circuit connection of a vertical transistor

Country Status (5)

Country Link
US (1) US6903411B1 (enExample)
JP (2) JP2002158350A (enExample)
KR (1) KR100748864B1 (enExample)
GB (1) GB2371921B (enExample)
TW (1) TWI260734B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113314422A (zh) * 2021-04-20 2021-08-27 芯盟科技有限公司 U型晶体管及其制造方法、半导体器件及其制造方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4219663B2 (ja) * 2002-11-29 2009-02-04 株式会社ルネサステクノロジ 半導体記憶装置及び半導体集積回路
TWI305669B (en) * 2006-07-14 2009-01-21 Nanya Technology Corp Method for making a raised vertical channel transistor device
JP5114968B2 (ja) * 2007-02-20 2013-01-09 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2009081163A (ja) * 2007-09-25 2009-04-16 Elpida Memory Inc 半導体装置およびその製造方法
JP2009088134A (ja) * 2007-09-28 2009-04-23 Elpida Memory Inc 半導体装置、半導体装置の製造方法並びにデータ処理システム
US8581333B2 (en) 2008-04-16 2013-11-12 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same
WO2009128450A1 (ja) 2008-04-16 2009-10-22 日本電気株式会社 半導体記憶装置
JP2010056215A (ja) * 2008-08-27 2010-03-11 Nec Electronics Corp 縦型電界効果トランジスタを備える半導体装置及びその製造方法
SG166752A1 (en) * 2009-05-22 2010-12-29 Unisantis Electronics Jp Ltd Semiconductor memory device and production method therefor
JP5692884B1 (ja) * 2014-08-19 2015-04-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Ｓｇｔを有する半導体装置の製造方法
US9627531B1 (en) * 2015-10-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Field-effect transistor with dual vertical gates
US9698145B1 (en) * 2015-12-28 2017-07-04 International Business Machines Corporation Implementation of long-channel thick-oxide devices in vertical transistor flow
KR102472673B1 (ko) * 2016-03-21 2022-11-30 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10032906B2 (en) * 2016-04-29 2018-07-24 Samsung Electronics Co., Ltd. Vertical field effect transistor and method of fabricating the same
US9859172B1 (en) 2016-09-29 2018-01-02 International Business Machines Corporation Bipolar transistor compatible with vertical FET fabrication
US9991359B1 (en) * 2017-06-15 2018-06-05 International Business Machines Corporation Vertical transistor gated diode
US10332972B2 (en) * 2017-11-20 2019-06-25 International Business Machines Corporation Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface
US10790357B2 (en) * 2019-02-06 2020-09-29 International Business Machines Corporation VFET with channel profile control using selective GE oxidation and drive-out
KR102839608B1 (ko) * 2020-04-20 2025-07-28 삼성전자주식회사 수직채널 구조체를 포함하는 집적회로 및 그 레이아웃방법
CN114220813B (zh) * 2021-12-10 2025-02-18 北京超弦存储器研究院 存储器件及其制备方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245058A (ja) * 1985-08-22 1987-02-27 Nec Corp 半導体装置およびその製造方法
JPS62166568A (ja) * 1986-01-20 1987-07-23 Nippon Telegr & Teleph Corp <Ntt> 半導体装置および製造方法
JPH0687500B2 (ja) * 1987-03-26 1994-11-02 日本電気株式会社 半導体記憶装置およびその製造方法
KR920022532A (ko) 1991-05-13 1992-12-19 문정환 이중 수직 채널을 갖는 스태틱램 및 그 제조방법
US5398200A (en) * 1992-03-02 1995-03-14 Motorola, Inc. Vertically formed semiconductor random access memory device
US5208172A (en) * 1992-03-02 1993-05-04 Motorola, Inc. Method for forming a raised vertical transistor
US5262352A (en) * 1992-08-31 1993-11-16 Motorola, Inc. Method for forming an interconnection structure for conductive layers
JP2889061B2 (ja) * 1992-09-25 1999-05-10 ローム株式会社 半導体記憶装置およびその製法
JPH06334130A (ja) * 1993-05-26 1994-12-02 Toshiba Corp 半導体装置
DE4417150C2 (de) * 1994-05-17 1996-03-14 Siemens Ag Verfahren zur Herstellung einer Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzellen
JP3003598B2 (ja) * 1995-11-22 2000-01-31 日本電気株式会社 半導体装置の製造方法
US5683930A (en) * 1995-12-06 1997-11-04 Micron Technology Inc. SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making
KR100223198B1 (ko) * 1996-04-11 1999-10-15 다니구찌 이찌로오, 기타오카 다카시 높은 강복 전압을 갖는 반도체 장치 및 그 제조 방법
DE19711483C2 (de) * 1997-03-19 1999-01-07 Siemens Ag Vertikaler MOS-Transistor und Verfahren zu dessen Herstellung
JPH11121400A (ja) * 1997-10-14 1999-04-30 Hitachi Ltd 半導体集積回路装置及びその製造方法
US6297531B2 (en) * 1998-01-05 2001-10-02 International Business Machines Corporation High performance, low power vertical integrated CMOS devices
US6027975A (en) * 1998-08-28 2000-02-22 Lucent Technologies Inc. Process for fabricating vertical transistors
US6143593A (en) * 1998-09-29 2000-11-07 Conexant Systems, Inc. Elevated channel MOSFET
JP3376302B2 (ja) * 1998-12-04 2003-02-10 株式会社東芝 半導体装置及びその製造方法
US6498367B1 (en) * 1999-04-01 2002-12-24 Apd Semiconductor, Inc. Discrete integrated circuit rectifier device
US6518622B1 (en) 2000-03-20 2003-02-11 Agere Systems Inc. Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor
US6300199B1 (en) * 2000-05-24 2001-10-09 Micron Technology, Inc. Method of defining at least two different field effect transistor channel lengths using differently angled sidewall segments of a channel defining layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113314422A (zh) * 2021-04-20 2021-08-27 芯盟科技有限公司 U型晶体管及其制造方法、半导体器件及其制造方法

Also Published As

Publication number Publication date
GB2371921B (en) 2005-04-06
GB2371921A (en) 2002-08-07
JP2010062574A (ja) 2010-03-18
KR100748864B1 (ko) 2007-08-13
JP2002158350A (ja) 2002-05-31
GB0120806D0 (en) 2001-10-17
KR20020016605A (ko) 2002-03-04
JP5479839B2 (ja) 2014-04-23
US6903411B1 (en) 2005-06-07

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