KR100748864B1 - 수직형 트랜지스터의 회로 접속을 위한 구조 - Google Patents

수직형 트랜지스터의 회로 접속을 위한 구조 Download PDF

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KR100748864B1
KR100748864B1 KR1020010053055A KR20010053055A KR100748864B1 KR 100748864 B1 KR100748864 B1 KR 100748864B1 KR 1020010053055 A KR1020010053055 A KR 1020010053055A KR 20010053055 A KR20010053055 A KR 20010053055A KR 100748864 B1 KR100748864 B1 KR 100748864B1
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KR20020016605A (ko
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치안위-펭
헤르겐로더죤마이클
먼로도날드폴
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에이저 시스템즈 가디언 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0195—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020010053055A 2000-08-25 2001-08-25 수직형 트랜지스터의 회로 접속을 위한 구조 Expired - Lifetime KR100748864B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/648,164 US6903411B1 (en) 2000-08-25 2000-08-25 Architecture for circuit connection of a vertical transistor
US09/648,164 2000-08-25

Publications (2)

Publication Number Publication Date
KR20020016605A KR20020016605A (ko) 2002-03-04
KR100748864B1 true KR100748864B1 (ko) 2007-08-13

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KR1020010053055A Expired - Lifetime KR100748864B1 (ko) 2000-08-25 2001-08-25 수직형 트랜지스터의 회로 접속을 위한 구조

Country Status (5)

Country Link
US (1) US6903411B1 (enExample)
JP (2) JP2002158350A (enExample)
KR (1) KR100748864B1 (enExample)
GB (1) GB2371921B (enExample)
TW (1) TWI260734B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4219663B2 (ja) * 2002-11-29 2009-02-04 株式会社ルネサステクノロジ 半導体記憶装置及び半導体集積回路
TWI305669B (en) * 2006-07-14 2009-01-21 Nanya Technology Corp Method for making a raised vertical channel transistor device
JP5114968B2 (ja) * 2007-02-20 2013-01-09 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2009081163A (ja) * 2007-09-25 2009-04-16 Elpida Memory Inc 半導体装置およびその製造方法
JP2009088134A (ja) * 2007-09-28 2009-04-23 Elpida Memory Inc 半導体装置、半導体装置の製造方法並びにデータ処理システム
WO2009128450A1 (ja) 2008-04-16 2009-10-22 日本電気株式会社 半導体記憶装置
JP5299422B2 (ja) 2008-04-16 2013-09-25 日本電気株式会社 半導体装置およびその製造方法
JP2010056215A (ja) * 2008-08-27 2010-03-11 Nec Electronics Corp 縦型電界効果トランジスタを備える半導体装置及びその製造方法
SG166752A1 (en) 2009-05-22 2010-12-29 Unisantis Electronics Jp Ltd Semiconductor memory device and production method therefor
JP5692884B1 (ja) * 2014-08-19 2015-04-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Ｓｇｔを有する半導体装置の製造方法
US9627531B1 (en) * 2015-10-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Field-effect transistor with dual vertical gates
US9698145B1 (en) * 2015-12-28 2017-07-04 International Business Machines Corporation Implementation of long-channel thick-oxide devices in vertical transistor flow
KR102472673B1 (ko) * 2016-03-21 2022-11-30 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10032906B2 (en) * 2016-04-29 2018-07-24 Samsung Electronics Co., Ltd. Vertical field effect transistor and method of fabricating the same
US9859172B1 (en) 2016-09-29 2018-01-02 International Business Machines Corporation Bipolar transistor compatible with vertical FET fabrication
US9991359B1 (en) 2017-06-15 2018-06-05 International Business Machines Corporation Vertical transistor gated diode
US10332972B2 (en) * 2017-11-20 2019-06-25 International Business Machines Corporation Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface
US10790357B2 (en) * 2019-02-06 2020-09-29 International Business Machines Corporation VFET with channel profile control using selective GE oxidation and drive-out
KR102839608B1 (ko) * 2020-04-20 2025-07-28 삼성전자주식회사 수직채널 구조체를 포함하는 집적회로 및 그 레이아웃방법
CN113314422B (zh) * 2021-04-20 2022-09-09 芯盟科技有限公司 U型晶体管及其制造方法、半导体器件及其制造方法
CN114220813B (zh) * 2021-12-10 2025-02-18 北京超弦存储器研究院 存储器件及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5392237A (en) * 1992-09-25 1995-02-21 Rohm Co., Ltd. Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array
US5710072A (en) * 1994-05-17 1998-01-20 Siemens Aktiengesellschaft Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US6027975A (en) * 1998-08-28 2000-02-22 Lucent Technologies Inc. Process for fabricating vertical transistors

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245058A (ja) * 1985-08-22 1987-02-27 Nec Corp 半導体装置およびその製造方法
JPS62166568A (ja) * 1986-01-20 1987-07-23 Nippon Telegr & Teleph Corp <Ntt> 半導体装置および製造方法
JPH0687500B2 (ja) * 1987-03-26 1994-11-02 日本電気株式会社 半導体記憶装置およびその製造方法
KR920022532A (ko) 1991-05-13 1992-12-19 문정환 이중 수직 채널을 갖는 스태틱램 및 그 제조방법
US5398200A (en) * 1992-03-02 1995-03-14 Motorola, Inc. Vertically formed semiconductor random access memory device
US5208172A (en) * 1992-03-02 1993-05-04 Motorola, Inc. Method for forming a raised vertical transistor
US5262352A (en) * 1992-08-31 1993-11-16 Motorola, Inc. Method for forming an interconnection structure for conductive layers
JPH06334130A (ja) * 1993-05-26 1994-12-02 Toshiba Corp 半導体装置
JP3003598B2 (ja) * 1995-11-22 2000-01-31 日本電気株式会社 半導体装置の製造方法
US5683930A (en) * 1995-12-06 1997-11-04 Micron Technology Inc. SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making
KR100223198B1 (ko) * 1996-04-11 1999-10-15 다니구찌 이찌로오, 기타오카 다카시 높은 강복 전압을 갖는 반도체 장치 및 그 제조 방법
DE19711483C2 (de) * 1997-03-19 1999-01-07 Siemens Ag Vertikaler MOS-Transistor und Verfahren zu dessen Herstellung
JPH11121400A (ja) * 1997-10-14 1999-04-30 Hitachi Ltd 半導体集積回路装置及びその製造方法
US6297531B2 (en) * 1998-01-05 2001-10-02 International Business Machines Corporation High performance, low power vertical integrated CMOS devices
US6143593A (en) * 1998-09-29 2000-11-07 Conexant Systems, Inc. Elevated channel MOSFET
JP3376302B2 (ja) * 1998-12-04 2003-02-10 株式会社東芝 半導体装置及びその製造方法
US6498367B1 (en) * 1999-04-01 2002-12-24 Apd Semiconductor, Inc. Discrete integrated circuit rectifier device
US6518622B1 (en) 2000-03-20 2003-02-11 Agere Systems Inc. Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor
US6300199B1 (en) * 2000-05-24 2001-10-09 Micron Technology, Inc. Method of defining at least two different field effect transistor channel lengths using differently angled sidewall segments of a channel defining layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5392237A (en) * 1992-09-25 1995-02-21 Rohm Co., Ltd. Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array
US5710072A (en) * 1994-05-17 1998-01-20 Siemens Aktiengesellschaft Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US6027975A (en) * 1998-08-28 2000-02-22 Lucent Technologies Inc. Process for fabricating vertical transistors

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Publication number Publication date
KR20020016605A (ko) 2002-03-04
GB2371921A (en) 2002-08-07
JP2010062574A (ja) 2010-03-18
US6903411B1 (en) 2005-06-07
GB2371921B (en) 2005-04-06
JP5479839B2 (ja) 2014-04-23
JP2002158350A (ja) 2002-05-31
GB0120806D0 (en) 2001-10-17
TWI260734B (en) 2006-08-21

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