KR100748864B1 - 수직형 트랜지스터의 회로 접속을 위한 구조 - Google Patents
수직형 트랜지스터의 회로 접속을 위한 구조 Download PDFInfo
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- KR100748864B1 KR100748864B1 KR1020010053055A KR20010053055A KR100748864B1 KR 100748864 B1 KR100748864 B1 KR 100748864B1 KR 1020010053055 A KR1020010053055 A KR 1020010053055A KR 20010053055 A KR20010053055 A KR 20010053055A KR 100748864 B1 KR100748864 B1 KR 100748864B1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 230000005669 field effect Effects 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
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- 229910021341 titanium silicide Inorganic materials 0.000 claims 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
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- 125000006850 spacer group Chemical group 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
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- IQXBLKYBDCBMNE-UHFFFAOYSA-N [Si]=O.[W] Chemical compound [Si]=O.[W] IQXBLKYBDCBMNE-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- 239000002243 precursor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- 239000007787 solid Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (33)
- 집적 회로 구조에 있어서,평면을 따라 형성된 주 표면을 갖는 반도체 층;상기 평면으로부터 상기 표면으로 확장하는 제 1 및 제 2 공간 이격 도핑된 영역들(spaced-apart doped regions);상기 제 1 영역과 상이한 도전형의 단결정 제 3 도핑된 영역으로서, 상기 평면 및 상기 제 1 영역 상에 위치되는, 상기 단결정 제 3 도핑된 영역;상기 제 1 영역과 제 2 영역 사이에 있으며, 상기 평면 상에 있는 도전층으로서, 상기 도핑된 영역들 간에 전기적 접속을 제공하고, 텅스텐 실리사이드(tungsten silicide), 텅스텐 니트라이드(tungsten nitride), 티타늄 실리사이드(titanium silicide), 티타늄 니트라이드(titanium nitride) 및 코발트 실리사이드(cobalt silicide)를 포함하는 그룹으로부터 취해지는 하나 이상의 재료들을 포함하는, 상기 도전층을 포함하는, 집적 회로 구조.
- 제 1 항에 있어서, 상기 제 1 도핑된 영역은 MOSFET의 제 1 소스/드레인 영역이고, 상기 제 3 영역은 MOSFET의 채널영역인, 집적 회로 구조.
- 제 2 항에 있어서, 상기 제 2 영역은 트랜지스터의 일부분인, 집적 회로 구조.
- 제 2 항에 있어서, 상기 제 2 영역은 제 2의 MOSFET와 연관된 제 2 소스/드레인 영역이고, 상기 구조는 상기 제 2 소스/드레인 영역과 정렬된 상기 제 2의 MOSFET의 채널영역을 더 포함하는, 집적 회로 구조.
- 제 1 항에 있어서,상기 제 2 영역과는 상이한 도전형의 제 2 영역 상의 제 4 도핑된 영역;상기 제 2 영역과 동일한 도전형의 상기 제 4 도핑된 영역 상의 제 5 도핑된 영역;상기 제 1 영역과 동일한 도전형의 상기 제 3 도핑된 영역 상의 제 6 영역을 더 포함하며, 상기 제 1 영역, 제 2 영역, 제 3 영역, 제 4 영역, 제 5 영역 및 제 6 영역과 도전성 층은 2개의 상호 접속된 트랜지스터들로서 구성되는, 집적 회로 구조.
- 제 5항에 있어서, 상기 2개의 트랜지스터들은 상보성 도전형(complementary conductivity type)인, 집적 회로 구조.
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- 제 1 항에 있어서,상기 제 1 및 제 2 도핑된 영역들은 제 1 및 제 2 소스/드레인 영역들이고, 상기 제 3 영역은 채널영역이고, 상기 구조는,상기 제 2 소스/드레인 영역 상에 형성된 제 2 채널영역;상기 채널 영역들 중 하나 및 상기 제 1 및 제 2 소스/드레인 영역들 중 하나와 각각 세로 방향으로 정렬된 제 3 및 제 4 공간 격리 소스/드레인 영역들; 및두 트랜지스터들 모두의 동작을 동시에 제어하기 위하여 접속된 도전성 소자를 더 포함하는, 집적 회로 구조.
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- 반도체 디바이스에 있어서,반도체 재료의 제 1 층;상기 제 1 층에 형성된 제 1 소스/드레인 영역, 상기 제 1 층상에 형성된 채널 영역, 및 상기 채널 영역 상에 형성된 제 2 소스/드레인 영역을 갖는 제 1 전계효과 트랜지스터;상기 제 1 층에 형성된 제 1 소스/드레인 영역, 상기 제 1 층 상에 형성된 채널 영역, 및 상기 채널 영역 상에 형성된 제 2 소스/드레인 영역을 갖는 제 2 전계 효과 트랜지스터; 및상기 제 1 층 및 상기 제 1 전계 효과 트랜지스터 채널 영역 간에서 확장하는 평면 내 도전층으로서, 한쪽의 제 1 소스/드레인 영역으로부터 다른 쪽의 제 1 소스/드레인 영역으로 전류를 도전하도록 각 트랜지스터의 상기 제 1 소스/드레인 영역 간에 위치된 금속을 포함하는, 상기 도전층을 포함하는, 반도체 디바이스.
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- 집적 회로 구조에 있어서,평면을 따라 형성된 주 표면을 갖는 반도체 층;상기 표면 내에 형성된 제 1 및 제 2 공간 이격 도핑된 영역들;상기 제 1 영역과는 상이한 도전형의 상기 제 1 영역 상의 제 3 도핑된 영역; 및상기 제 1 영역과 제 2 영역 사이에 있으며, 상기 평면 상에 형성된 도전층으로서, 상기 도핑된 영역들 간에 전기적 접속을 제공하고, 텅스텐 실리사이드, 텅스텐 니트라이드, 티타늄 실리사이드, 티타늄 니트라이드 및 코발트 실리사이드를 포함하는 그룹으로부터 취해지는 하나 이상의 재료들을 포함하는, 상기 도전층을 포함하는, 집적 회로 구조.
- 반도체 디바이스에 있어서,반도체 재료의 제 1 층;상기 제 1 층에 형성된 제 1 소스/드레인 영역, 상기 제 1 층 상에 형성된 채널 영역, 및 상기 채널 영역 상에 형성된 제 2 소스/드레인 영역을 갖는 제 1 전계 효과 트랜지스터;상기 제 1 층에 형성된 제 1 소스/드레인 영역, 상기 제 1 층 상에 형성된 채널 영역, 및 상기 채널 영역 상에 형성된 제 2 소스/드레인 영역을 갖는 제 2 전계 효과 트랜지스터; 및한쪽의 제 1 소스/드레인 영역으로부터 다른 쪽의 제 1 소스/드레인 영역으로 전류를 도전하도록 각 트랜지스터의 상기 제 1 소스/드레인 영역 간에 위치된 금속을 포함하는 도전층으로서, 상기 도전층은 메탈 실리사이드(metal silicide)를 포함하는, 상기 도전층을 포함하는, 반도체 디바이스.
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Application Number | Priority Date | Filing Date | Title |
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US09/648,164 | 2000-08-25 | ||
US09/648,164 US6903411B1 (en) | 2000-08-25 | 2000-08-25 | Architecture for circuit connection of a vertical transistor |
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Publication Number | Publication Date |
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KR20020016605A KR20020016605A (ko) | 2002-03-04 |
KR100748864B1 true KR100748864B1 (ko) | 2007-08-13 |
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US (1) | US6903411B1 (ko) |
JP (2) | JP2002158350A (ko) |
KR (1) | KR100748864B1 (ko) |
GB (1) | GB2371921B (ko) |
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Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4219663B2 (ja) * | 2002-11-29 | 2009-02-04 | 株式会社ルネサステクノロジ | 半導体記憶装置及び半導体集積回路 |
TWI305669B (en) * | 2006-07-14 | 2009-01-21 | Nanya Technology Corp | Method for making a raised vertical channel transistor device |
JP5114968B2 (ja) * | 2007-02-20 | 2013-01-09 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP2009081163A (ja) * | 2007-09-25 | 2009-04-16 | Elpida Memory Inc | 半導体装置およびその製造方法 |
JP2009088134A (ja) * | 2007-09-28 | 2009-04-23 | Elpida Memory Inc | 半導体装置、半導体装置の製造方法並びにデータ処理システム |
JP5299422B2 (ja) | 2008-04-16 | 2013-09-25 | 日本電気株式会社 | 半導体装置およびその製造方法 |
WO2009128450A1 (ja) | 2008-04-16 | 2009-10-22 | 日本電気株式会社 | 半導体記憶装置 |
JP2010056215A (ja) * | 2008-08-27 | 2010-03-11 | Nec Electronics Corp | 縦型電界効果トランジスタを備える半導体装置及びその製造方法 |
US8373235B2 (en) | 2009-05-22 | 2013-02-12 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor memory device and production method therefor |
JP5692884B1 (ja) * | 2014-08-19 | 2015-04-01 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する半導体装置の製造方法 |
US9627531B1 (en) | 2015-10-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field-effect transistor with dual vertical gates |
US9698145B1 (en) * | 2015-12-28 | 2017-07-04 | International Business Machines Corporation | Implementation of long-channel thick-oxide devices in vertical transistor flow |
KR102472673B1 (ko) * | 2016-03-21 | 2022-11-30 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US10032906B2 (en) * | 2016-04-29 | 2018-07-24 | Samsung Electronics Co., Ltd. | Vertical field effect transistor and method of fabricating the same |
US9859172B1 (en) | 2016-09-29 | 2018-01-02 | International Business Machines Corporation | Bipolar transistor compatible with vertical FET fabrication |
US9991359B1 (en) | 2017-06-15 | 2018-06-05 | International Business Machines Corporation | Vertical transistor gated diode |
US10332972B2 (en) * | 2017-11-20 | 2019-06-25 | International Business Machines Corporation | Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface |
US10790357B2 (en) * | 2019-02-06 | 2020-09-29 | International Business Machines Corporation | VFET with channel profile control using selective GE oxidation and drive-out |
CN113314422B (zh) * | 2021-04-20 | 2022-09-09 | 芯盟科技有限公司 | U型晶体管及其制造方法、半导体器件及其制造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5392237A (en) * | 1992-09-25 | 1995-02-21 | Rohm Co., Ltd. | Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array |
US5710072A (en) * | 1994-05-17 | 1998-01-20 | Siemens Aktiengesellschaft | Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells |
US6027975A (en) * | 1998-08-28 | 2000-02-22 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6245058A (ja) * | 1985-08-22 | 1987-02-27 | Nec Corp | 半導体装置およびその製造方法 |
JPS62166568A (ja) * | 1986-01-20 | 1987-07-23 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置および製造方法 |
JPH0687500B2 (ja) * | 1987-03-26 | 1994-11-02 | 日本電気株式会社 | 半導体記憶装置およびその製造方法 |
KR920022532A (ko) | 1991-05-13 | 1992-12-19 | 문정환 | 이중 수직 채널을 갖는 스태틱램 및 그 제조방법 |
US5208172A (en) * | 1992-03-02 | 1993-05-04 | Motorola, Inc. | Method for forming a raised vertical transistor |
US5398200A (en) * | 1992-03-02 | 1995-03-14 | Motorola, Inc. | Vertically formed semiconductor random access memory device |
US5262352A (en) * | 1992-08-31 | 1993-11-16 | Motorola, Inc. | Method for forming an interconnection structure for conductive layers |
JPH06334130A (ja) * | 1993-05-26 | 1994-12-02 | Toshiba Corp | 半導体装置 |
JP3003598B2 (ja) * | 1995-11-22 | 2000-01-31 | 日本電気株式会社 | 半導体装置の製造方法 |
US5683930A (en) * | 1995-12-06 | 1997-11-04 | Micron Technology Inc. | SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making |
KR100223198B1 (ko) * | 1996-04-11 | 1999-10-15 | 다니구찌 이찌로오, 기타오카 다카시 | 높은 강복 전압을 갖는 반도체 장치 및 그 제조 방법 |
DE19711483C2 (de) * | 1997-03-19 | 1999-01-07 | Siemens Ag | Vertikaler MOS-Transistor und Verfahren zu dessen Herstellung |
JPH11121400A (ja) * | 1997-10-14 | 1999-04-30 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
US6297531B2 (en) * | 1998-01-05 | 2001-10-02 | International Business Machines Corporation | High performance, low power vertical integrated CMOS devices |
US6143593A (en) * | 1998-09-29 | 2000-11-07 | Conexant Systems, Inc. | Elevated channel MOSFET |
JP3376302B2 (ja) * | 1998-12-04 | 2003-02-10 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6498367B1 (en) * | 1999-04-01 | 2002-12-24 | Apd Semiconductor, Inc. | Discrete integrated circuit rectifier device |
US6518622B1 (en) | 2000-03-20 | 2003-02-11 | Agere Systems Inc. | Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor |
US6300199B1 (en) * | 2000-05-24 | 2001-10-09 | Micron Technology, Inc. | Method of defining at least two different field effect transistor channel lengths using differently angled sidewall segments of a channel defining layer |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5392237A (en) * | 1992-09-25 | 1995-02-21 | Rohm Co., Ltd. | Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array |
US5710072A (en) * | 1994-05-17 | 1998-01-20 | Siemens Aktiengesellschaft | Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells |
US6027975A (en) * | 1998-08-28 | 2000-02-22 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
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TWI260734B (en) | 2006-08-21 |
US6903411B1 (en) | 2005-06-07 |
JP5479839B2 (ja) | 2014-04-23 |
JP2010062574A (ja) | 2010-03-18 |
KR20020016605A (ko) | 2002-03-04 |
GB2371921B (en) | 2005-04-06 |
JP2002158350A (ja) | 2002-05-31 |
GB0120806D0 (en) | 2001-10-17 |
GB2371921A (en) | 2002-08-07 |
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