TWI255020B - Stacked die semiconductor device - Google Patents
Stacked die semiconductor device Download PDFInfo
- Publication number
- TWI255020B TWI255020B TW092104209A TW92104209A TWI255020B TW I255020 B TWI255020 B TW I255020B TW 092104209 A TW092104209 A TW 092104209A TW 92104209 A TW92104209 A TW 92104209A TW I255020 B TWI255020 B TW I255020B
- Authority
- TW
- Taiwan
- Prior art keywords
- die
- bead
- chip package
- adhesive material
- stacked multi
- Prior art date
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Classifications
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
(1) l255〇2〇 發明說明 . &月t敘明_务明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 技術領域· 、本發明係關於積體電路及封裝積體電路之方法,更 堆®式多晶片封裝型式之積體電路。 g 先前技術 積體電路(1C)晶粒係一形成於半導體晶圓(諸如一矽晶圓) 上〈小裝置。此一晶粒通常是從該晶圓切割出且附著至一 承載基座,用於内部連線之埠端重佈。晶粒上之焊墊則經 由絲焊電連接至承載座上之引線。晶粒與絲焊會用保護性 材料封入以形成一封裝。已封入封裝之引線經埠端重佈於 承載座内的一網路且結束於封裝外部的一端點陣列。依據 封裝之型式,此等端點可被用於如TS0P中,或經進一步處 理後(如附著於球狀焊球)用於球格柵陣列(BGA)。該端點 允弄晶粒電連接至其他電路’諸如印刷電路板上。在後續 之範例中,將使用MAPBGA示範在此說明之本發明。 為了增加在一封裝内之電路容量,而不增加封裝之面積 以致該封裝不會佔用電路板上較多之空間,製造商已堆疊 包括二個或以上之晶粒於單一封裝.中。此裝置有時稱為堆 疊式多晶片封裝。圖1顯示一第一習知堆疊式多晶片封裝 1 0。該封裝1 0包括以一第一黏著層1 6附著於一承載基座 14(在此範例中為一 MAPBGA基板)的一第一或底部晶粒12。 —第二或頂部晶粒1 8係以類似第一黏著層1 6的一第二黏著 層2 0附著於底部晶粒1 2。底部與頂部晶粒1 2、1 8分別經由 絲焊以導線2 2與2 4電連接至承載基座1 4。端子2 6 (在此為球 (2) 1255020 發明說明續頁 T、子)係連接至承載基座14之網路或埭a + a 顯亍彳、 < 旱%重佈層(未 一、)。展邵與頂部晶粒、18與導線22、24妒、m,, 封, 十以树脂28密 U而形成堆疊式多晶片封裝10。為使底 絲r s 丨日日权12能以 …τ 土承載基座14之引線,頂部晶粒18必須j 12。 ,、小於展部晶粒 圖2顯示一第二習知堆疊式多晶片封裝3〇。^ 一 J-., 弟—封裝7 Γ) =以第—黏著層36附著於一承載基座或基板“的一第一 或辰部晶粒32。在底部晶粒32上之焊墊 弟 由蛘十曰+土 弟一導線38經 4沣境連接至基板34上之引線。通常由 件40佴η 〜 7 I成之間隔 係以一弟二黏著層42附著至底..部晶粒32。〜 晶耘心办、 弟二或頂部 系以一第三黏著層46附著至一間隔件4〇。 頂部晶粒44之尺寸約等於或大於底部 | θ曰私32。此情,'尸 如頂邵與底部晶粒32、44係如圖所示卩朴 件4川,、、 々不附者(即不具間隔 )展邵晶粒32之絲焊將不可能進行。炊 隔件40技1 “、、如圖顯示,間 件4〇係小於底部晶粒32以絲焊底部晶 因此,如日 乂 2而不受阻礙。 頂#日日粒44上之焊墊係以第二壤 導、’泉48經由辞惶兩、击 接至基板34。 二田、4岭電連 間隔件40與第二42與第三黏著層邨之全 大,以致當頂部晶粒44附著至間隔件 子又必頊足夠 〇干40時,連接至 粒32之導線38將不受干擾。球狀焊成“ —H曰曰 年琢碲子50係連接至美板 的一佈線層(未顯示)。底部晶粒32、 土 、邵晶粒44、間隔件40 與導線3 8、4 8均以樹脂5 2密封,阳^ ^ , 而形成堆疊式多晶片封 裝30。雖然此解決方案允許幾手如门 子相同的二晶粒被一起封 裝,間隔件40則增加封裝3〇製程之前 又則置時間、成本與尺寸(高 1255020 (3) 發明鍊明續頁 度)。 需求能夠堆疊包括相同尺寸或頂部晶粒較大的二個或以 上之晶粒於單一封裝内,而不致使產生之封裝尺寸不當地 增加,而且不需要一間隔件。 發明内容 以下連接附圖之說明預期是當作本發明較佳具體實施例 之說明,且不希望被視為可實現本發明之唯一型式。應瞭 解相同或相等之功能可藉由預期將包含於本發明之精神與 範疇之不同具體實施例而達成。為求簡化,用於示範本發 明之範例只引用具有二堆疊晶粒的封裝。然而,相同之發 明實際上可應用於封裝具有二個以上之堆疊晶粒。 附圖中一些特徵為易於示範而加以放大,因而圖式與元 件將不需要有正確之比例。然而,熟知此項技術人士將易 於了解此細節。在圖式中,相似之件號將在全文中用以表 示相似之元件。 為了提供頂部晶粒約相等或大於底部晶粒的一堆疊式多 晶片封裝,本發明係一堆疊式多晶片封裝,包括一承載基 座、一底部積體電路晶粒與一頂部積體電路晶粒。承載基 座具有一頂側與一底側。底部晶粒之底面係附著至承載基 座頂側。底部晶粒之頂面具有包板複數個第一焊墊與一中 央區域之周邊區域。一黏著性材料硃粒係形成於底部晶粒 的頂面上周邊區域與中央區域之間。頂部晶粒係位於底部 晶粒上,且頂部晶粒之底面係經由珠粒附著於底部晶粒之 頂面。珠粒維持介於底部晶粒與頂部晶粒間的一預定空 1255020 (4) 發明說明續頁 隙。 本發明也提供一種堆疊式多晶片封裝,包括一承載基 座、一底部積體電路晶粒、一頂部積體電路晶粒、一黏著 性材料珠粒與一封裝材。承載基座具有一頂側與一底側, 該頂側包括複數個第一引線與複數個第二引線。該底部晶 粒具有附著至承載基座頂側的一底.面與一相對之頂面。底 部晶粒之頂面具有包括複數個第一焊墊與一中央區域的一 周邊區域。底部晶粒係以第一導線電連接至承載基座。第 一導線具有電連接至第一焊墊之第一端,與電連接至第一 引線的第二端。珠粒係形成於底部晶粒的頂面上,介於周 邊區域與中央區域之間。一黏著性材料形成於底部晶粒的 頂面上之中央區域,且由該珠粒環繞。頂部晶粒具有一底 面與一頂面。頂部晶粒係位於底部_晶粒上方,而頂部晶粒 之底面係經由珠粒與黏著性材料附著於底部晶粒之頂面 上。珠粒維持介於底部晶粒與頂部晶粒間的一預定空隙。 頂部晶粒包括複數個位於頂面上一周邊區域内的第二焊 墊,而頂部晶粒係以第二導線電連接至該承載基座。第二 導線具有電連接至第二焊墊之第一端,與電連接至第二引 線之第二端。封裝材覆蓋第一與第二晶粒、第一與第二導 線與承載基座至少一部份的頂側。‘ 本發明也提供一種製造堆疊式多%%片封裝之方法,包括 下列步驟: . 附著一底部積體電路晶粒至一承载基座,該底部晶粒具 有一頂面與一底面,其中該底面係附著至承載基座的一頂 -10- (5) 1255020 發明說明續頁 側,且其中該底部晶粒頂面具有一 域與一周邊區 域,該周邊區域包括複數個第一焊塾; 藉由絲焊第一導線至底部晶粒之複數個第一焊墊,以及 至承載基座頂側上相對應之第一引缭 1、、果而電連接底部晶粒 土承載基座; 形成一黏著性材料之珠粒於底部晶 日曰杈頂面上介於周邊區 域與中央區域之間,其中該珠粒具有一預定高度· 以黏著性材料珠粒附著-頂部晶粒的—底^底部晶粒 的一頂面,其中該珠粒造成該頂部::晶粒與底部晶粒分隔, 以致該頂部晶粒不會接觸該等第一導線;及 藉由絲焊該等第二導線至位於該頂 ^ 貝邯曰曰权的一頂面上的 第二焊墊以及至該承載基座頂側 W對應 < 罘二引線,而 電連接頂部晶粒至承載基座。 本發明也提供一種製造堆疊式多晶片封 日曰斤對裝艾万法,包括 下列步驟: : 附著一底部積體電路晶粒至 有一頂面與一底面,其中該底 頂側,且其中該底部晶粒頂面 域,該周邊區域包括複數個第 承.·載基座,該底部晶粒具 面係·附著至該承載基座的一 具有一中央區域與一周邊區 一焊墊; 藉由絲焊該等第一導線至該底部晶粒之複數個第一焊塾 以及至該承載基座頂側上相對應之第一引線,而電連接底 部晶粒至承載基座; 形成一黏著性材料之珠粒於該底·部晶粒頂面上介於周邊 區域與中央區域之間,其中該珠粒具有一預定高产. -11 - 1255020 發明說明續頁 (6) 以一黏著性材料填充該底部晶粒頂面上之中央區域,其 中該黏著性材料係為該珠粒所環繞; 附著該頂部晶粒的底面至該底部晶粒之頂面,其中該珠 * · 粒與黏著性材料固定頂部晶粒至底部晶粒,且其中該珠粒 造成頂部晶粒與底部晶粒分隔,以致該頂部晶粒不會接觸 該等第一導線; 藉由絲焊該等第二導線至位於該頂部晶粒之頂面上的第 二焊墊以及至該承載基座頂側上相對應之第二引線,而電 連接該頂部晶粒至該承載基座;而後封入該頂部與底部晶 粒、第一與第二導線與至少一部份之承載基座於一樹脂 内。 實施方式 ,.. 請參考圖3,顯示依據本發明之堆疊式多晶片封裝100之 放大侧視圖。堆疊式多晶片封裝100包括一承載基座或基 板102、一底部積體電路晶粒104與一頂部積體電路晶粒 106。基板102、底部晶粒104與頂部晶粒106均係熟知此項 技術者已知的型式。 ·’ · 底部晶粒104與頂部晶粒106較佳羌具有實質上相同之長 度與寬度尺寸。然而,頂部晶粒、06可稍大或稍小於底部 晶粒1 04。例如,典型之底部與頂部晶粒尺寸可介於4毫米 x4毫米至12毫米X 12毫米範圍間。底部與頂部晶粒104、106 也可具有相同之厚度,然而此並非必需。視最終封裝外形 之厚度而定,底部與頂部晶粒104、106具有之厚度可介於 約6毫吋至約2 1毫吋間。 -12 - 1255020 (7) 發明說明續頁 基板102具有一頂側108與一底側11〇。底部晶粒104具有 一底面112與一相對的第二頂面114。底部晶粒104之底面1 u 係附著至基板1〇2之頂側1〇8。較佳是底部晶粒104以第一黏 著性材料層11 6附著至基板1 02。第一黏著性材料層1 1 6可為 任何適合之黏著性材料,諸如一膠帶、熱塑性黏著物、一 環氧樹脂材料或其類似物。適用於附著一積體電路晶粒至 一基板之黏著物係熟知此項技術者·已知。
如圖4顯示,底部晶粒1〇4之頂面114具有包括複數個第一 焊墊118與一中央區域120的一周邊區域。再參考圖3,底部 晶粒104係以第一導線122電連接至基板102上之引線(未顯 示)。更特別的是,第一導線122之一端係電連接至底部晶 粒1〇4頂面1H上之焊墊118,而第一導線122之相對端係絲 焊至基板102頂面108上之引線。適用之焊接導線通常包含 導電金屬,諸如銅或金。 ·
請參考圖3與圖4,一珠粒124係形成於底部晶粒104頂面 114上介於周邊區域與中央區域12〇之間。當頂部晶粒1〇6係 如圖3所π附著至底部晶粒1〇4時,珠粒124之尺寸可提供底 P曰曰紅104興頂4印粒1〇6間適當之空隙,以致當頂部晶粒 Π)6附著至底部晶粒1〇4時,第一導線122之絲彈】
壞。例如,該珠粒124且;έτ 士 ώ . L 、 $以4八有又向度可為約100微米。珠粒 較佳是包含一可硬化之黏芏 · <黏耆性材料.,諸如環氧樹脂,以 珠粒124維持頂部晶粒1〇6盥 兴展邵晶粒104及絲焊點一預疋 離,但也固定頂部晶粒〗M s十、 土底部晶粒1〇4。然而,珠粒 可由其他材料形成,嗜‘ r/7 ^ 劣如矽或材料之混合物。在圖中, -13 - 1255020 (8) · 發明說明續頁 粒124大體上係呈方形。 諸如圓形、卵形、矩來 然而,珠粒124可具有其他形狀, 或其類似物。珠粒124可以熟知此 成 樹 項技術者已知的—缸κ ° 針與注射器或環氧樹脂屏障塗佈機形 於底部晶粒1 〇 4卜。 珠粒124之高度與寬度可視散佈環氧 脂或珠粒材料於底部晶粒104上之針的尺寸而變化。 在一較佳具體實施例中,一黏著性材料126係形成於底 4 EJ曰粒104頂面114上之中央區域_12〇,使該黏著性材料126 被珠124環繞。頂邵晶粒1〇6係以珠粒ι24與黏著性材料I% 附著至底部晶粒1〇4。較特別的是,頂部晶粒1〇6的一底面 係經由珠粒124與黏著性材料126附著至底部晶粒ι〇4頂面 114之中央區域12〇。如先前的討論,珠粒124之尺寸與形狀 可維持底部晶粒104與頂部晶粒106間的一預定空隙,以致 當頂部晶粒1⑽附著至底部晶粒1〇4時,第一導線122之絲焊 不致損壞。 · 黏著性材料126可包含與珠粒lh相同型式之材料,例如 在本文較佳具體實施例中,珠粒丨2 4包含具有第一黏性之 環氧樹脂,而黏著性材料126包含具有較低之第二黏性的 一環氧樹脂。例如,珠粒124通常具有之黏性介於600 Kps 至1300 Kps之範圍間,而黏著性材料126具有之黏性介於0.15 Kps至1〇〇 Kps之範圍間。然而,熟知此項技術者應瞭解黏 著性材料126之黏性與使用材料之密度與尺寸有很大之關 聯。 · 頂部晶粒106包括複數個位於該頂.面一周邊區域的第二 焊墊(未顯示)。頂部晶粒106以第二導線128電連接至承載 •14- l255〇2〇 (9) -—- 發明說明績頁 基厓102。第二導線128具有電連接·至該第二焊墊之第一端, =電連接至該承載基座1〇2上第二:引線(未顯示)之第二端。 弟二導線128較佳是絲坪至該第二焊塾與該第二引線。 -封裝材丨3〇(諸如樹脂)覆蓋第一與第二晶粒1〇4、1〇6、 第一與第一寸、’泉122、128與承載基座1〇2至少一部份的頂 側。 請參考圖5,顯示一種依據本發明製作堆疊式多晶片封 裝之方法。在第一步驟140中,一第一或底部晶粒(諸如底 邵晶粒104)將附著至一承載基座(諸如承載基座1〇2)。如先 前討論,底部晶粒104可用一已知方式(諸如一膠帶或一環 氧樹脂)附著至基板102。較特別的是,底部晶粒1 〇4之第一 或底面係附著至承載基座10 2的一頂面。 在底部晶粒1 〇 4附著至承載基座1 〇 2後,底部晶粒1 〇 4在第 一絲焊步驟142中,經由絲焊電連接至承載基座1〇2。如已 知,底部晶粒10 4之頂面具有沿其周邊分佈之複數個焊整。 第一焊接導線122係絲焊至此等複蓼個洋墊以及至承載基 座102上相對應之複數個引線。 : 在附著頂部晶粒106至底部晶粒104前,珠粒124在步驟144 將形成於底邵晶粒1 頂面114上介於底部晶粒烊整與一中 央區域之間,如圖4所示。珠粒124較佳是包含一高黏性環 氧樹脂。環氧樹脂可用針散佈於頂面114上。珠粒材料之 黏性可加以控制’以致當珠粒形成後’該材料不會在可能 千擾絲焊或絲焊製程之底部晶粒周邊區域流動。意即,如 第一絲焊步驟142係在珠粒形成之步驟144前施.行,則珠粒 -15- (10)1255020 發明說明續頁 ' 、’、 ♦ 材料具有《黏性使珠粒124形成時,材料不會流到絲焊點。 另-選擇是’如果珠粒124係在絲焊步驟⑷前形成,則珠 粒材料務必不能流到坪塾上。如果珠粒材料黏性不夠高而 當頂部晶粒106隨後附著至底部曰 n攸I仃考土版4日日缸1〇4(諸如藉由壓配〕 時,頂部晶粒1〇6不會壓到絲焊點。意即,珠粒124可維持 介於底部晶粒104與頂部晶粒1〇6間的—預定空隙,例如對 於尺寸為4.5毫米x4.5毫米χ11毫吋之晶粒,珠粒124具有之 高度可約為1〇〇微米而寬度約為〇·3毫米。 材料流到卜烊塾上、m塾須在施行n焊步驟 m2前加以清理。形成之珠粒124會具有—預定高度,以致 在步驟146中,—黏著物或黏著性材料126係置放於底部 晶粒104頂面114之中央區域,以致頂部晶粒1〇6可附著至底 部晶粒104。珠粒124形成一屏障,使添加之黏著性材料 可散佈於其中。雖然並非其主要目的,珠粒124或屏障可 防止添加之黏著性材料126流到絲焊與第一焊塾上。較佳 是添加之黏著性材料126包含一低黏性環氧樹脂。添加之 黏著性材料126可用習知方式以一散佈針施加於中央區 域。例如,珠粒124可在散佈該添加之黏著性材料前, 以環氧樹脂形成且允許藉由諸如置放一預定時間、加熱或 施加一紫外線燈使其開始硬化。 在步驟148中,頂部晶粒106的一底面係使用珠粒124與添 加4黏著性材料126附著至底部晶粒104,以固定頂部晶_ 106至底邵晶粒104。意即,頂部晶粒106較佳是在珠粒材料 124已硬化至其一有效黏著點前固定於底部晶粒1〇4。除了 1255020 發明說明績頁 (ii) 協助固定頂部晶粒106至底部晶粒104,珠粒124會造成頂部 晶粒106與底部晶粒104分隔,以致頂部晶粒106不會接觸第 一導線122 〇 頂部晶粒106較佳是具有大體上與底部晶粒104相同或較 大之尺寸。意即,底部與頂部晶藏104、106具有實質上相 同之長度與寬度,或是頂部晶粒ί〇6可具有比底部晶粒104 較大之長度及/或寬度。例如典型之底部與頂部晶粒尺寸 可介於4毫米χ4毫米至12毫米χ12毫米之範圍間。底部與頂 部晶粒104、106也可具有相同之厚度,然而此並非必要。 視最終封裝外形厚度而定,底部與頂部晶粒104、106具有 之厚度可介於約6毫吋至約2 1毫吋。 頂部晶粒106於是可在第二絲焊.步.驟150經由絲焊而電連 接至基板102。第二導線}28係以辞焊至頂部晶粒106之焊墊 與承載基座102上相對應乏引線(未顯示)。 最後,在步騾152中,底部與頂部·晶粒104與106、第一與 第二導線122、128以及至少一部份之承載基座102將以一封 裝材覆蓋。產生之堆疊式多晶片封裝具有二個幾乎相同尺 寸之堆疊式晶粒,然而整體封裝高度係小於先前技術中包 括一無效間隔晶粒之堆疊式晶粒封’裝的封裝高度。因為無 須一無效晶粒以及無須附者該無效晶粒之步驟,堆®式多 晶片封裝之成本也得以降低。 . ·: 已提供之本發明較佳具體實施例:係用於示範與說明之目 的,惟不希望被視為是毫無遺漏4限制本發明為所揭示之 型式。應瞭解將可由熟知此項技術人士對以上說明之具體 -17- 1255020 (12) 發明說明續頁 實施例加以改變,而不脫離本發明:廣義之觀念。例如,本 發明不限於具有二堆疊式晶粒之封裝,而是可以應用至多 個堆疊式晶粒之封裝。再者,本發明將不限於任何單一絲 焊技術或特定之封裝。意即,本發明係可應用於所有導線 焊接封裝型式,包括但不限於BGA、QFN、QFP、PLCC、 CUEBGA、TBGA與TSOP。此外,晶粒大小與步驟中之尺寸 可加以變化以符合封裝設計之要求。因此,應瞭解本發明 不限於特定具體實施例,而是涵蓋屬於如隨附的申請專利 範圍中所界定之本發明範疇及精神的修改。 圖式簡單說明 當配合附圖詳讀前面的發明内容及上文中的本發明具體 實施例詳細說明時,將可更明白本發明。基於解說本發明 的目的,圖式中顯示本發明較佳具體實施例。然而,應明 白本發明不限定於如圖所示的精確配置及機構。於圖式 中: 圖1係弟一習知堆聲式多晶片封裝·的一放大側視圖, 圖2係第二習知堆疊式多晶片封裝•的一放大側視圖; 圖3係依據本發明第一具體實施例之堆疊式多晶片封裝 的一攻大側視圖; 圖4係圖3之堆疊式多晶片封裝一底部晶粒與珠粒的一放 大頂视圖;及 圖5係示範形成圖3之堆疊式多晶片封裝的步驟流程圖。 圖式代表符號說明 夕晶片封裝 -18- 1255020 發明說明績頁 (13) 12 頂部晶粒 14 水載基座 16 黏著層 18 頂部晶粒 20 黏著層 22 導線 24 導線 26 端子 28 樹脂 30 多晶片封裝 32 底部晶粒 34 基板 36 黏著層 38 第一導線 40 間隔件 42 黏著層 44 頂部晶粒 46 黏著層 48 第二導線 50 焊球端子 52 封裝材 100 多晶片封裝 102 承載基座 104 底部積體電路晶粒 -19- 1255020 (14) 頂部積體電路晶粒 頂側 底側 底面 頂面 第一黏著性材料層 中央區域 第一導線 珠粒 黏著性材料 第二導線 封裝材 發明說明續頁 106 108 110 112 114 116 120 122 124 126 128 130 -20-
Claims (1)
1255020 拾、申請專利範圍 > 1. 一種堆疊式多晶片封裝,其包含: 一承載基座,其具有一頂側與一底側; 一底部積體電路晶粒,其具有附著至該承載基座頂側 的一底面與一相對之頂面,該頂面具有包括複數個第一 焊墊與一中央區域的一周邊區域; 一珠粒,其在該周邊區域與該中央區域之間形成於該 底邵晶粒之該頂面上,及 一頂部積體電路晶粒,其具有一底面,其中該頂部晶 粒位於該底部晶粒上,而該頂部晶粒之該底面係經由該 珠粒附著至該底部晶粒之該頂面,其中該珠粒維持介於 該底部晶粒與該頂部晶粒間的一預定空隙。 2. 如申請專利範圍第1項之堆疊式多晶片封裝,其中該底 部晶粒係以一第一黏著性材料層附著至該承載基座。 3. 如申請專利範圍第1項之堆疊式多晶片封裝,其中該頂 部晶粒與該底部晶粒係相同尺寸與形狀。 4. 如申請專利範圍第1項之堆疊式多晶片封裝·_:/其中該頂 部晶粒係大於該底部晶粒。 . 5. 如申請專利範圍第1項之堆疊式多晶片封裝,其中該珠 粒包含環氧樹脂。 6. 如申請專利範圍第1項之堆疊式多晶片封裝,其進一步 包含一黏著性材料,形成於該底部晶粒之該頂面上的該 中央區域内,該黏著性材料為該珠粒環繞,.其中該黏著 性材料固定該頂部晶粒至該底部晶粒。 1255020 7. 如申請專利範圍第6項之堆疊式多晶片封 粒包含環氧樹脂。 . 8. 如申請專利範圍第7項之堆疊式多晶片封 著性材料包含環氧樹脂。 9. 如申請專利範圍第6項之堆疊式多晶片封 部晶粒係以第一導線電連接至該承載基座 線具有電連接至該等第一焊墊之第一端, 承載基座之該頂側之第一引線的第二端。 10. 如申請專利範圍第9項之堆疊式多晶片封 部晶粒包括位於該頂部晶粒一頂面上的一 複數個第二焊墊,且其中該頂部晶粒係以 接至該承載基座,該等第二導線具有電連 焊墊之第一端,與電連接至該承載基座之 引線之第二端。 11. 如申請專利範圍第10項之堆疊式多晶片封 包含一封裝材覆蓋該等第一與第二晶粒、 二導線與該承載基座之至少一部份之該頂 12. —種堆疊式多晶片封裝,其包含: 一承載基座,其具有一頂側與一底側, 數個第一引線與複數個第二引線; 一底部積體電路晶粒,其具有附著至該 的一底面與一相對之頂面,該頂面具有包 焊墊與一中央區域的一周邊區域,其中該 第一導線電連接至該承載基座,該等第一 申請專利範圍績頁 裝,其中該珠 裝,其中該黏 裝.‘,其中該底 ,該等第一導 與電連接至該 裝,其中該頂 周邊區域内之 第二導線電連 接至該等第二 該頂側上第二 裝,其進一步 該等第一與第 側。 該頂側包括複 承載基座頂側 括複數個第一 底部晶粒係以 導線具有電連 1255020 申請專利範圍績頁 接至該等第一焊墊之第一端,與電連接至該等第一引線 的第二端; 一珠粒,其在該周邊區域與該中央區域之間形成於該 底部晶粒的該頂面上; 一黏著性材料,其形成於該底部晶粒之該頂面上的該 中央區域内,該黏著性材料係由該珠粒環繞; 一頂部積體電路晶粒,其具有/底面,其中該頂部晶 粒位於該底部晶粒上方’且該頂邵晶粒之該底面係經由 該珠粒與該黏著性材料附著至該底部晶粒之該頂面上, 且該珠粒維持介於該底部晶粒與該頂部晶粒間的一預定 空隙,而其中該頂部晶粒包括複數個位於一頂面上一周 邊區域上的複數個第二焊墊,且其中該頂部晶粒係以第 二導線電連接至該承載基座,該等第二導線具有電連接 至該等第二焊墊之第一端,與電連接至該等.第二引線之 —二山 · ηχ 弟— 一封裝材,其覆蓋該第一與該第二晶粒、該等第一與 該等第二導線及該承載基座之至少一部份之該頂側。 13. 如申請專利範圍第12項之堆疊式多晶片封裝,其中該底 部晶粒係以一第一黏著性材料層附著至該承載基座。 14. 如申請專利範圍第13項之堆疊式j晶片封裝,其中該頂 部晶粒與該底部晶粒為相同之尺寸‘與形狀。 15. 如申請專利範圍第13項之堆疊式多晶片封裝,其中該頂 部晶粒係大於該底部晶粒。 * 16. 如申請專利範圍第13項之堆疊式多晶片封裝,其中該珠 1255020 粒包含環氧樹脂。 17. 如申請專利範圍第16項之堆疊式多晶片封裝,其中該黏 著性材料包含環氧樹脂。 18. 如申請專利範圍第13項之堆疊式多晶片封裝,其中由該 珠粒維持介於該頂部晶粒與該底部晶粒之該預定空隙, 其係足以保護介於該等第一導線與該等第一焊墊間之電 連接,避免當附著該頂部晶粒至該底部晶^i時造成損 壞。 · · 19. 一種製造堆疊式多晶片封裝之方法,其包含下列步驟: 附著一底部積體電路晶粒至一承載基座,該底部晶粒 具有一頂面與一底面,其中該底面係附著至該承載基座 的一頂側,且其中該底部晶粒頂面具有一中央區域與一 周邊區域,該周邊區域包括複數個第一焊墊; 藉由絲焊第一導線至該底部晶粒之該等複數個第一焊 墊,以及至該承載基座頂側相對應之第一引線,而電連 接該底部晶粒至該承載基座; · . 形成黏著性材料的一珠粒於該底部晶粒之該頂面上介 於該中央區域與該周邊區域之間,其中該珠粒具有一預 定高度; 以該黏著性材料珠粒附著一頂部晶粒的一底面至該底 部晶粒之該頂面,其中該珠粒造成該頂部晶粒與該底部 晶粒分隔,以致該頂部晶粒不接觸該等第一導線;及 藉由絲焊第二導線至位於該頂部晶粒的一頂面上的第 二焊墊,以及至該承載基座上相#應之該等第二引線, 1255020 _ 申請專利範圍續頁 而電連接該頂部晶粒至該承載基座·。 20. 如申請專利範圍第1 9項之製造一 $疊式多晶片封裝之方 法,其中該底部與頂部晶粒具有實質上相同之長度與實 質上相同之寬度。 21. 如申請專利範圍第19項之製造一堆疊式多晶片封裝之方 法,其中該頂部晶粒係大於該底部晶粒。 22. 如申請專利範圍第19項之製造一堆疊式多晶片封裝之方 法,進一步包含以一黏著性材料填充該底部晶粒之該頂 面上的該中央區域之步驟,其中該黏著性材料係由該珠 粒所環繞,且其中該珠粒與該黏/著性材料固定該頂部晶 粒至該底部晶粒。 23. 如申請專利範圍第22項之製造一堆疊式多晶片封裝之方 法,其中用以形成該珠粒之材料具有比該黏著性材料較 高之黏性。 24. 如申請專利範圍第23項之製造一堆疊式多晶片封裝之方 法,該珠粒與該黏著性材料包含環氧樹脂。 25. 如申請專利範圍第19項之製造一堆疊式多晶劣封裝之方 法,進一步包含封入該頂部與該底‘部晶粒:該等第一與 第二導線與至少一部份之該承載基座於一樹脂内之步 驟。 26. —種製造一堆疊式多晶片封裝之方法,其包括下列步 驟: 附著一底部積體電路晶粒至一承載基座,該底部晶粒 具有一頂面與一底面,其中該底面.係附著至該承載基座 1255020 申請專利範圍績頁 的一頂側,且其中該底部晶粒頂面具有一中央區域與一 周邊區域,該周邊區域包括複數個第一焊墊; 藉由絲焊該等第一導線至該底部晶粒之該等複數個第 一焊墊以及至該承載基座之該頂側上相對應之第一引 線,而電連接該底部晶粒至該承載基座; 形成一黏著性材料之珠粒於該底部晶粒的該頂面上介 於該周邊區域與該中央區域之間,其中該珠粒具有一預 定高度; 以一黏著性材料填充該底部晶粒之該頂面上的該中央 區域,其中該黏著性材料係由該珠粒所環繞; 附著一頂部晶粒的一底面至該底部晶粒之該頂面,其 中該珠粒與該黏著性材料固定該頂部晶粒至該底部晶 粒,且其中該珠粒造成該頂部晶粒與該底部晶粒彼此分 隔,以致該頂部晶粒不接觸該等第一導線; 藉由絲焊第二導線至位於該頂部晶粒的一頂面上之第 二焊墊以及至該承載基座頂側上相對應之第二引線,而 電連接該頂部晶粒至該承載基座;及 封入該等頂部與底部晶粒、該等第一與第二導線與至 少一部份之該承載基座於一樹脂内。 27. 如申請專利範圍第26項之製造一堆疊式多晶片封裝之方 法,其中用以形成該珠粒之材料具有比該黏著性材料較 南之黏性。 28. 如申請專利範圍第27項之製造一堆疊式多晶片封裝之方 法,該珠粒與該黏著性材料包含環氧樹脂。
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-
2002
- 2002-02-28 US US10/085,869 patent/US6885093B2/en not_active Expired - Lifetime
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2003
- 2003-02-07 KR KR10-2004-7013484A patent/KR20040089685A/ko not_active Application Discontinuation
- 2003-02-07 JP JP2003573701A patent/JP2005519471A/ja active Pending
- 2003-02-07 EP EP03707785A patent/EP1479107A2/en not_active Withdrawn
- 2003-02-07 WO PCT/US2003/003761 patent/WO2003075348A2/en active Application Filing
- 2003-02-07 CN CNB038048086A patent/CN100390990C/zh not_active Expired - Fee Related
- 2003-02-07 AU AU2003209057A patent/AU2003209057A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
WO2003075348B1 (en) | 2004-07-08 |
KR20040089685A (ko) | 2004-10-21 |
WO2003075348A2 (en) | 2003-09-12 |
AU2003209057A1 (en) | 2003-09-16 |
US7211466B2 (en) | 2007-05-01 |
JP2005519471A (ja) | 2005-06-30 |
TW200303607A (en) | 2003-09-01 |
US6885093B2 (en) | 2005-04-26 |
WO2003075348A3 (en) | 2004-04-22 |
EP1479107A2 (en) | 2004-11-24 |
US20030160312A1 (en) | 2003-08-28 |
US20050127491A1 (en) | 2005-06-16 |
CN100390990C (zh) | 2008-05-28 |
CN1647277A (zh) | 2005-07-27 |
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