CN107994004A - 堆叠式管芯半导体封装体 - Google Patents

堆叠式管芯半导体封装体 Download PDF

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Publication number
CN107994004A
CN107994004A CN201711257276.8A CN201711257276A CN107994004A CN 107994004 A CN107994004 A CN 107994004A CN 201711257276 A CN201711257276 A CN 201711257276A CN 107994004 A CN107994004 A CN 107994004A
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China
Prior art keywords
encapsulation
group
semiconductor element
semiconductor devices
aerial lug
Prior art date
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Pending
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CN201711257276.8A
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English (en)
Inventor
邱书楠
贡国良
徐雪松
庞兴收
阎蓓悦
李颖会
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Vlsi Technology Co Ltd
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Vlsi Technology Co Ltd
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Application filed by Vlsi Technology Co Ltd filed Critical Vlsi Technology Co Ltd
Priority to CN201711257276.8A priority Critical patent/CN107994004A/zh
Publication of CN107994004A publication Critical patent/CN107994004A/zh
Pending legal-status Critical Current

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Abstract

本公开涉及堆叠式管芯半导体封装体。一种半导体封装体以及组装半导体封装体的方法，包括包封堆叠于第二半导体管芯之上并且与第二半导体管芯互连的第一预封装的半导体管芯。第一封装半导体管芯相对于引线框以临时性的载体(例如带)来定位和固定。第二半导体管芯被附接于第一封装半导体管芯和引线框并且与它们直接互连。互连的第一封装半导体管芯和第二半导体管芯，以及引线框被包封以形成半导体封装体。可以形成不同类型的半导体封装体，例如方形扁平无引脚(QFN)型封装、球栅阵列(BGA)型封装，这提供了增加的输入/输出(I/O)总数和功能。

Description

堆叠式管芯半导体封装体
本申请是申请日为2011年7月22日且发明名称为“堆叠式管芯半导体封装体”的中国专利申请No.201110205715.7的分案申请。
技术领域
本发明一般地涉及半导体器件封装，并且更特别地涉及堆叠式管芯半导体封装体。
背景技术
半导体封装体是用于集成电路和器件的容器。半导体封装体包括与集成电路和器件一起的包封的半导体管芯。半导体封装体具有用来在例如半导体封装体被安装于印制电路板(PCB)时使半导体管芯与外部电路互连的露出的输入/输出(I/O)引脚。管芯可以封装于许多不同的载体或封装结构中，例如，方形扁平无引脚(QFN)、球栅阵列(BGA)等。此类半导体封装体保护管芯以及与管芯的互连，并且允许各种型外部I/O。
对具有提高的速度和功能的，具有更小的封装占用面积和厚度的半导体封装体有着持续的需求。在增加功能的尝试中，一些半导体封装体包括多于一个的半导体管芯。例如，一些半导体封装体包括一个叠在另一个上地堆叠的两个或更多的管芯。其他堆叠式管芯封装包括堆叠于已经封装的(包封的)管芯之上的管芯。但是，此类管芯堆叠于已封装管芯之上的半导体封装体仅限于一定类型的半导体封装体，并且从半导体封装体露出的I/O引脚的数量是有限的。另外，在此类管芯堆叠于已封装管芯之上的半导体封装体的管芯和已封装管芯之间的互连在半导体封装体的外部于外部电路内进行。这增加了另外的设计考虑、处理步骤，以及安装具有外部电路的半导体封装体所增加的成本。而且，更高功率的器件生成主要经由管芯载体散发的更高的热能，但是，当前的BGA堆叠式管芯封装在热方面受限并且被设计以应用于较低功率的器件和应用中。存在解决或至少缓解以上问题中的一些问题的需求。
发明内容
本发明的一方面是所封装的半导体器件，包括：具有第一引线框的第一封装半导体管芯，第一引线框含有从所封装的半导体管芯露出的第一引脚，第一封装半导体管芯具有第一表面；固定于第一封装半导体管芯的第一表面的第二半导体管芯；用于为具有第一封装半导体管芯和第二半导体管芯的封装半导体器件提供到外部电路的输入和输出的第二引线框；使第一管芯与第二管芯互连的第一连接器；使第一管芯与第二引线框互连的第二连接器；以及覆盖第一封装半导体管芯、第二半导体管芯、第一连接器、第二连接器、第一引线框和第二引线框的包封材料。
在一种实施例中，第二引线框的一部分是露出的。第一引线框的一部分可以是露出的。第一引线框的一部分可以从第一封装半导体管芯突出。第二引线框的一部分可以在另一平面上与该引线框的另一部分偏移。第二引线框的偏移部分可以是第二引线框的引脚并且由包封材料所包封。第一封装半导体管芯可以是方形扁平无引脚(QFN)型封装器件。第一封装半导体管芯可以是功率方形扁平无引脚(PQFN)型封装器件。所封装的半导体器件可以是方形扁平无引脚(QFN)型封装器件。所封装的半导体器件可以是球栅阵列(BGA)型封装器件。
本发明的一方面是一种封装所封装的半导体的方法，包括：将第一封装半导体管芯和第二引线框固定于载体，第一封装半导体管芯具有含有从所封装的半导体管芯露出的第一引脚的第一引线框，第一封装半导体管芯具有第一表面；将第二半导体管芯固定于第一封装半导体管芯的第一表面，第二引线框用于为具有第一封装半导体管芯和第二半导体管芯的封装半导体器件提供到外部电路的输入和输出；互连第一连接器以使第一管芯与第二管芯互连；互连第二连接器以使第一管芯与第二引线框互连；用包封材料来包封以覆盖第一封装半导体管芯、第二半导体管芯、第一连接器、第二连接器、第一引线框和第二引线框；以及去除载体以形成所封装的半导体。
在一种实施例中，载体是带。第一引线框的一部分可以是露出的以及第二引线框的一部分可以是露出的。第一引线框的一部分可以从第一封装半导体管芯突出。第一封装半导体管芯可以是方形扁平无引脚(QFN)型封装器件。第一封装半导体管芯可以是功率方形扁平无引脚(PQFN)型封装器件。所封装的半导体器件可以是方形扁平无引脚(QFN)型封装器件。所封装的半导体器件可以是球栅阵列(BGA)型封装器件。互连可以通过导线接合(wire bonding)来进行。焊料球可以形成于第二引线框的表面之上。
附图说明
在此所并入的并且形成本说明书的一部分的附图示出了本发明的几个方面并且与说明书一起用来解释本发明的原理。虽然本发明将结合一些实施例来描述，但是并没有意图将本发明限定于所描述的那些实施例。相反，意图涵盖包含于由所附权利要求所界定的本发明的范围之内的所有替代方案、修改和等同物。在附图中：
图1是根据本发明的一种实施例的第一封装半导体管芯的简化截面图；
图2是根据本发明的一种实施例的附接于带的引线框的顶视图；
图3是从根据本发明的一种实施例的附接于带的引线框的图2的虚线1-1截取的截面图；
图4是根据本发明的一种实施例附接于图2和图3的带的图1的第一封装半导体管芯的截面图；
图5是根据本发明的一种实施例附接施加于图4的第一封装半导体管芯的顶部的管芯的截面图；
图6是根据本发明的一种实施例固定于附接在图5的第一封装半导体管芯的顶部的管芯的第二管芯的截面图；
图7是根据本发明的一种实施例附接到图6的第二管芯及引线框的导线接合的截面图；
图8示出了根据本发明的一种实施例附接到图7的第二管芯及引线框的导线接合的顶视图；
图9是根据本发明的一种实施例包封图7和图8的导线接合、第二管芯、引线框及第一封装半导体的模制材料的截面图；
图10示出了根据本发明的一种实施例具有第一封装半导体的封装半导体器件，其中第一封装半导体与第二管芯互连并包封，含有方形扁平无引脚(QFN)型封装半导体器件内的露出连接器；
图11示出了根据本发明的一种实施例的图10的封装半导体器件的底视图；
图12是示出根据本发明的一种实施例的一种封装所封装的半导体器件的方法的流程图；
图13是根据本发明的一种实施例的第一封装半导体管芯的简化截面图；
图14是根据本发明的一种实施例的图13的第一封装半导体管芯以及附接于带的引线框的截面图；
图15是根据本发明的一种实施例附接于图14的第一封装半导体管芯的顶部的第二管芯的截面图；
图16是根据本发明的一种实施例附接到图15的第二管芯及引线框的导线接合的截面图；
图17是根据本发明的一种实施例包封图16的导线接合、第二管芯、引线框和第一封装半导体的模制材料的截面图；
图18示出了根据本发明的一种实施例具有第一封装半导体的封装半导体器件，第一封装半导体与第二管芯互连并包封，含有球栅阵列(BGA)型封装半导体器件内的外部连接器；
图19示出了根据本发明的一种实施例的图18的封装半导体器件的底视图；
图20是根据本发明的一种实施例的第一封装半导体器件的截面图；
图21示出了根据本发明的一种实施例具有图20所示的第一封装半导体的封装半导体器件，其中第一封装半导体与第二管芯互连并包封；
图22示出了根据本发明的一种实施例的具有球栅阵列(BGA)型封装半导体器件内的外部连接器的图21的封装半导体器件；
图23示出了根据本发明的一种实施例具有图20所示的第一封装半导体的封装半导体器件的截面图，第一封装半导体与第二管芯互连并包封；
图24是示出根据本发明的一种实施例具有第一封装半导体的封装半导体器件的截面图，第一封装半导体与第二管芯互连并包封，含有方形扁平无引脚(QFN)型封装半导体器件内的露出连接器；以及
图25示出了根据本发明的一种实施例的图24的封装半导体器件的底视图。
具体实施方式
本发明的一方面是所封装的半导体器件，包括：具有第一引线框的第一封装半导体管芯，第一引线框含有从所封装的半导体管芯露出的第一引脚，第一封装半导体管芯具有第一表面；固定于第一封装半导体管芯的第一表面的第二半导体管芯；用于为具有第一封装半导体管芯和第二半导体管芯的封装半导体器件提供到外部电路的输入和输出的第二引线框；使第一管芯与第二管芯互连的第一连接器；使第一管芯与第二引线框互连的第二连接器；以及覆盖第一封装半导体管芯、第二半导体管芯、第一连接器、第二连接器、第一引线框和第二引线框的包封材料。
在一种实施例中，第二引线框的一部分是露出的。第一引线框的一部分可以是露出的。第一引线框的一部分可以从第一封装半导体管芯突出。第二引线框的一部分可以在另一平面上偏移与该引线框的另一部分。第二引线框的偏移部分可以是第二引线框的引脚并且由包封材料所包封。第一封装半导体管芯可以是方形扁平无引脚(QFN)型封装器件。第一封装半导体管芯可以是功率方形扁平无引脚(PQFN)型封装器件。所封装的半导体器件可以是方形扁平无引脚(QFN)型封装器件。所封装的半导体器件可以是球栅阵列(BGA)型封装器件。
本发明的一方面是一种封装所封装的半导体的方法，包括：将第一封装半导体管芯和第二引线框固定于载体，第一封装半导体管芯具有第一引线框，第一引线框含有从所封装的半导体管芯露出的第一引脚，第一封装半导体管芯具有第一表面；将第二半导体管芯固定于第一封装半导体管芯的第一表面，第二引线框用于为具有第一封装半导体管芯和第二半导体管芯的封装半导体器件提供到外部电路的输入和输出；互连第一连接器以使第一管芯与第二管芯互连；互连第二连接器以使第一管芯与第二引线框互连；用包封材料来包封以覆盖第一封装半导体管芯、第二半导体管芯、第一连接器、第二连接器、第一引线框和第二引线框；以及去除载体以形成所封装的半导体。
在一种实施例中，载体是带。第一引线框的一部分可以是露出的以及第二引线框的一部分可以是露出的。第一引线框的一部分可以从第一封装半导体管芯突出。第一封装半导体管芯可以是方形扁平无引脚(QFN)型封装器件。第一封装半导体管芯可以是功率方形扁平无引脚(PQFN)型封装器件。所封装的半导体器件可以是方形扁平无引脚(QFN)型封装器件。所封装的半导体器件可以是球栅阵列(BGA)型封装器件。互连可以通过导线接合来进行。焊料球可以形成于第二引线框的表面之上。
本发明公开了半导体封装体以及封装该半导体封装体的方法：包封堆叠于第二半导体管芯之上并且与第二半导体管芯互连的第一预封装的半导体管芯。第一预封装的半导体管芯相对于无焊盘的引线框以临时性的载体(例如带)来定位和固定。第二半导体管芯与第一封装半导体管芯的第一表面(例如上表面)和引线框附接并且直接互连。互连的第一封装半导体管芯和第二半导体管芯，以及引线框被包封，形成具有互连的堆叠管芯和封装管芯的半导体封装体。以这种布局和方法，不同类型的半导体封装体(例如方形扁平无引脚(QFN)型封装、球栅阵列(BGA)型封装)可以由堆叠管芯和封装管芯型器件形成，增加了半导体封装体的输入/输出(I/O)总数以及功能和应用。
图1-11示出了根据本发明的一种实施例以互连的堆叠管芯和封装管芯进行半导体封装体的组装或封装工艺的不同阶段；
现在参考图1，图中示出了根据本发明的一种实施例的第一封装半导体管芯10的简化截面图。在该实施例中所封装的半导体管芯10是方形扁平无引脚(QFN)型半导体封装体。应当意识到，封装半导体可以是不同类型的封装，例如：方形扁平无引脚(QFN)、功率方形扁平无引脚(PQFN)、小外形集成电路(SOIC)、方形扁平封装(QFP)和其他引脚封装。这些封装具有突出引脚以提供与其他电路(例如第二管芯)的互连。第一封装半导体管芯10包括：第一引线框12；以及引线框管芯支撑或吸盘14，其用于支撑以粘合剂或管芯接合材料16接合至吸盘(paddle)14的半导体管芯18。半导体管芯18通过管芯接合材料16或管芯附接层固定于吸盘14。半导体管芯18通过导线20与引线框12的引脚导线接合。包封材料22，例如塑料等，覆盖并保护半导体管芯18、导线20、引线框12等。包封材料22形成第一封装半导体管芯10的上表面24。第一引线框12的引脚从第一封装半导体10延突出。具有突出或露出的引脚的半导体封装体类型是与单体化型QFN相对的冲压型QFN。由于所封装的半导体在一种实施例中可以具有管芯支撑或吸盘，因而该实施例利用铜或其他金属或者金属合金的高热导率，这为高功率器件提供了优良的热导率。
图2示出了根据本发明的一种实施例具有附接于临时性载体(例如带34)的引脚32的第二引线框30的顶视图。处于示例性的目的，第二引线框30可以是广泛使用于工业中的任意材料，例如铜合金等。图3是从根据本发明的一种实施例附接于带34的图2的引线框30的虚线1-1截取的截面图。载体或带34可以采用不同于带的形式。例如，载体可以是含有具有高粘性的粘合材料的基膜的带。应当意识到，带34能够耐得住诸如250℃的高温。引线框30在该实施例中是具有方形结构的无吸盘型引线框。应当意识到，引线框可以具有不同的形状和引脚结构及布局。
图4是根据本发明的一种实施例附接于载体(例如图2和3的带34)的图1的第一封装半导体管芯10的截面图50。所封装的半导体管芯10在带上布置于由引线框的引脚所形成的中间区域内。应当意识到，引线框和封装管芯可以具有不同的形状及结构并且可以布置于不同的取向上，例如引线框的引脚在封装半导体管芯10被布置于带上之后可以完全(如图所示)或部分延伸于封装半导体管芯10的周围。在此所示出和讨论的实例仅出于示例性的目的而提供。第一封装半导体管芯10被稳固地附接于带34上以防止模制材料78渗到管芯吸盘14或引线框引脚12之下。
图5和6示出了根据本发明的一种实施例施加于图4的第一封装半导体管芯10的顶部的管芯附接材料52和芯片或半导体管芯54的截面图。半导体管芯54具有上表面56。在该实施例中，半导体管芯54具有小于第一封装半导体管芯10的上表面的尺寸。
图7是具有附接到引线框引脚32的导线60以及附接到第一封装半导体管芯10的伸出或突出的引脚64的导线62的导线接合的截面图。连接在伸长的引脚64与导线62之间的连接点进行。导线的材料可以是典型使用于工业中的任意材料，例如金(Au)、铜(Cu)等。导线从管芯54的顶面56，从导线接合焊盘(没有示出)接合至第一管芯封装的突出引脚64。图8示出了根据本发明的一种实施例附接到图7的第二管芯及引线框的导线接合的顶视图70。导线62使附接到在第一封装管芯10的顶部的导线接合焊盘72的第二管芯52经由突出引脚64来互连，以及导线60使第二管芯52从在第一封装管芯10的顶部的导线接合焊盘74互连至第一引线框的引脚12的突出部分64，形成封装半导体的输入/输出(I/O)以一旦布置于例如印制电路板(PCB)之上时与外部电路(没有示出)电互连。导线60、62可以按任意顺序或者在单一处理步骤中同时地导线接合。
图9是根据本发明的一种实施例包封图7和图8的导线接合60和62、第二管芯54、导线接合焊盘、引线框30及第一封装半导体10的第二模制材料78的截面图。包封剂过模材料78、液体顶部包封等被传递模制等以完全包封及保护半导体封装体的脆弱的部件。模制材料形成保护罩以保护部件免受诸如水分、应变、冲击、振动、灰尘等外部及环境条件的影响。模制材料可以是环氧树脂、塑料等，并且被选择以满足特定应用的规格要求。封装半导体器件的第二模制或包封剂材料78可以是与第一封装半导体器件的第一模制或包封剂材料22相同或不同的材料。
图10和11示出了根据本发明的一种实施例具有含有第二管芯的互连并包封的第一封装半导体的封装半导体器件。图10是封装半导体器件的截面图80以及图11是封装半导体器件的底视图90。所示出的是在带34被去除并且封装半导体器件被锯切之后的封装半导体器件。
图12是示出根据本发明的一种实施例封装所封装的半导体器件的方法100的流程图。该方法包括制备102、104第一封装半导体器件10和引线框。将引线框12和第一封装半导体管芯10粘贴106、108于带。应当意识到，引线框和第一封装半导体管芯的粘贴可以按任意顺序或者在单一处理步骤中同时进行。将第二管芯54附接110于第一封装半导体管芯10的上表面。经由第一封装半导体管芯10的引线框的突出引脚64将第二管芯54导线接合112至第一管芯，并且将第二管芯54导线接合至引线框的引脚32。应当意识到，导线60、62可以接任意顺序或者在单一处理步骤中同时来导线接合。包封或模制116封装半导体的部件，包括互连的第二管芯54和第一封装半导体管芯10，导线接合60、62，引线框32以及突出引脚64。如果多个封装半导体管芯正如图10和11所示的那样进行处理，则去除118带并且锯切120部件。可以处理外部的互连或输入/输出(I/O)连接器(例如球栅阵列(BGA))以使所处理的半导体与外部电路(没有示出)互连。
图13-19示出了根据本发明的一种实施例封装具有互连的堆叠管芯及封装管芯的半导体封装体的不同阶段。
图13是根据本发明的一种实施例的第一封装半导体管芯150的简化截面图。第一封装半导体管芯150与参考图1到图12所讨论的第一封装半导体管芯10相似，但是图13所示的封装半导体管芯150是袋状功率方形扁平无引脚(PQFN)型封装半导体器件，包括具有引脚的引线框152、引线框管芯支撑154、管芯接合材料156层、芯片或管芯158、使管芯与引线框的引脚互连的导线160、通过横过管芯顶部来使PQFN功率管芯和功率引脚连接的铝(Al)导线161以及保护性第一包封剂模制材料162。
图14是根据本发明的一种实施例附接于带174的图13的第一封装半导体管芯150及引线框172的截面图。引线框和带可以与参考图2和图3所讨论的引线框相似。
图15是根据本发明的一种实施例使第二管芯178附接于图14的第一封装半导体管芯150的上表面179的接合材料层176的截面图。
图16是根据本发明的一种实施例附接到图15的第二管芯及引线框的导线接合的截面图。导线180、182的导线接合工艺与图7的导线接合工艺相似。第一导线180经由导线接合焊盘将第二管芯178连接至引线框172的引脚。第二导线182经由第一封装半导体管芯150的引线框的引脚152的突出引脚部分184使第一管芯158与第二管芯178互连。
图17是根据本发明的一种实施例包封图16的导线接合180和182、第二管芯178、引线框172及第一封装半导体的模制材料186的截面图。模制材料186相当于图9的模制材料78。图18示出了根据本发明的一种实施例从含有第二管芯的互连并包封的第一封装半导体150去除了带174的封装半导体器件190的截面图。还示出的是形成封装半导体190的连接器的焊料球192。焊料球192在带174被去除之后被附接或者被成组电镀(gang dip)于在引线框172的底部上的焊料焊盘(没有示出)。焊料焊盘和焊料球的图形可以形成任意数目的图形的球栅阵列。图19示出了根据本发明的一种实施例的图18的封装半导体器件的底视图200，其中球栅阵列被示出沿着封装半导体190的周边。应当意识到，球栅阵列的图形、间距和尺寸可以采用不同的结构和形式。所示出的尺寸、形状和图形只是为了示例性的目的而提供的实例。在图13-19中示出的这种实施例是包封堆叠于封装PQFN上的第二管芯178的球栅阵列(BGA)型的封装半导体。由于封装半导体在一种实施例中可以具有管芯支撑或吸盘，因而该实施例利用纯铜或者其他金属或金属合金的更高的热导率，并且将金属引线框作为管芯载体来应用以及为高功率器件提供优良的热导率。该实施例还允许使具有大的导线部分和平行的导线连接的高电流电路成为可能的铝导线，以使高功率器件成为可能。
图20-22示出了根据本发明的一种实施例具有BGA型半导体封装体的带有互连的堆叠管芯及封装管芯的半导体封装体的不同视图。封装具有互连的堆叠管芯及封装管芯的这种半导体封装体的不同阶段相当于参考图1-19所讨论的实施例并且因此仅示出图20-22的半导体封装体的视图。
图20示出了具有引线框222、管芯焊盘224、管芯附接层226、第一管芯228、导线230以及形成第一封装半导体220的顶面或上表面234的包封材料232的封装半导体器件220的截面区视图。引线框222具有：处于与管芯焊盘区224相同的平面内的一部分236；以及处于导线230附接于(自)第一管芯228之上的导线焊盘(没有示出)的不同平面内的另一部分。
图21示出了根据本发明的一种实施例具有含有第二管芯的互连并包封的图20的第一封装半导体220的封装半导体器件240的截面区视图。封装半导体器件240包括第二引线框242、管芯附接层244、第二管芯246、将第二管芯连接至引线框242的引脚以至外部电路的导线248、将第二管芯246连接至第一管芯228的引脚222并且使第二管芯246与第一管芯228互连的导线250，以及保护封装半导体器件240的部件的包封剂材料252。形成封装半导体器件220的处理步骤相当于图1到图12所示的关于封装半导体器件90的处理步骤以及图13-19所示的关于封装半导体器件190的处理步骤。图22示出了具有与外部电路互连形成BGA型封装半导体器件的诸如焊料球262的互连的封装半导体器件260的截面图。图22示出了形成嵌入BGA型封装260之内的QFP的封装类型的封装半导体器件260的截面图。
图23示出了根据本发明的一种实施例具有与第二管芯互连并包封的图20所示的第一封装半导体220的封装半导体器件270的截面图。封装半导体器件270包括第二引线框272、管芯附接层274、第二管芯276、将第二管芯连接至引线框272的引脚的导线278、使第二管芯276与第一管芯228连接的导线280，以及保护封装半导体器件270的部件的包封剂材料282。形成封装半导体器件270的处理步骤与图1-12所示的关于封装半导体器件80、90的处理步骤以及图13-19所示的关于封装半导体器件190、200的处理步骤一致。图23示出了形成嵌入QFN型封装270之内的QFP的封装类型的封装半导体器件270的截面图。
图24和25示出了根据本发明的一种实施例具有互连的堆叠管芯及封装管芯的半导体封装体300的不同视图。封装具有互连的堆叠管芯及封装管芯的这种半导体封装体的不同阶段与参考图1-19所讨论的实施例一致并且因此仅示出图24和25的半导体封装体的视图。更特别地，形成封装半导体器件300的处理步骤与图1到图12所示的关于封装半导体器件80、90的处理步骤以及图13-19所示的关于封装半导体器件190、200的处理步骤一致。所封装的第一管芯包括具有突出引脚的第一引线框302、第一引线框的管芯焊盘区304、管芯附接层306、第一管芯308、将第一管芯308从管芯焊盘(没有示出)连接至引线框的引脚302的导线310，以及形成第一管芯308的顶面或上表面314并且保护所封装的第一管芯的部件的包封材料312。半导体封装体器件300还包括具有在与第一引线框302的管芯焊盘区304的平面不同的平面上的引脚部分318的第二引线框316、管芯附接层320、第二管芯322、从第二管芯322的表面的导线接合(没有示出)附接到第二引线框316的引脚324的导线324、从第二管芯322的表面的导线接合(没有示出)到第一引线框的突出引脚302的导线326，以及保护封装半导体器件300的部件的包封剂材料328。
具有在不同于引线框的另一部分的平面上的不同高度处或偏移的引脚318的第二引线框316被示出并且与第一封装半导体管芯一起施加于诸如带的载体(没有示出)上。在处理了接合层320，接合了第二管芯322，将导线324从第二管芯292的接合焊盘(没有示出)导线接合至引线框316的引脚318，将导线326从在第二管芯之上的接合焊盘(没有示出)导线接合至第一引线框的突出引脚302之后，以模制材料来模制各部件。在模制之后，带被去除。
图25示出了根据本发明的一种实施例的图24的封装半导体器件300的底视图340。示出在去除临时性的载体(例如带)之后，第一和第二引线框302、304、316的引脚的露出表面的下表面以及第一引线框的管芯支撑304或管芯焊盘区的下表面。
应当意识到，具有含有不同集成电路和器件的不同类型的管芯、不同类型的第一封装半导体以及包括不同材料的其他结构可被构想出。所示出及所讨论的实施例作为实例来提供。在此已经描述了本发明的实施例，包括本发明人所知道的用于实施本发明的最好模式。在阅读前面的描述时，这些优选的实施例的变化对本领域技术人员而言会变得明显。本发明人预期本领域技术人员适当地使用此类变化，并且本发明人意图使本发明以除了在此所具体描述的方式之外的方式来实施。因此，如同适用的法律所允许的，本发明包括在附于此的权利要求所述的主题的所有修改和等同物。而且，上述元件在其所有可能的变化中的任意结合由本发明所包含，除非在此另有说明或者上下文明显矛盾。
虽然在前面的描述中已经描述了本发明的实施例，但是本领域技术人员应当理解，在不脱离由所附权利要求所界定的本发明的范围或界限的情况下可以在设计或构造的细节方面进行许多改变或修改。在此已经描述了本发明的实施例，包括本发明人所知道的用于实施本发明的最好模式。在阅读前面的描述时，这些优选的实施例的变化对本领域技术人员而言会变得明显。本发明人预期本领域技术人员适当地使用此类变化，并且本发明人意图使本发明以除了在此所具体描述的方式之外的方式来实施。因此，如同适用的法律所允许的，本发明包括在附于此的权利要求所述的主题的所有修改和等同物。而且，上述元件在其所有可能的变化中的任意结合由本发明所包含，除非在此另有说明或者上下文明显矛盾。

Claims (15)

1.一种封装半导体器件，包括：
第一栅阵列型封装，具有(i)第一半导体管芯；(ii)第一组外部连接器；(iii)覆盖所述第一半导体管芯的第一包封剂；以及(iv)第一表面；
第二半导体管芯：(i)经由所述第一表面固定于所述第一栅阵列型封装；并且(ii)具有第一组管芯焊盘；
第二栅阵列型封装，具有第二组外部连接器，以为所述封装半导体器件提供到外部电路的输入和输出；
使所述第一组管芯焊盘中的第一管芯焊盘与所述第二组外部连接器中的外部连接器互连的第一连接器；
覆盖所述第一连接器、所述第二半导体管芯和所述第一栅阵列型封装的第二包封剂。
2.根据权利要求1所述的封装半导体器件，还包含：
所述第一表面上的管芯附接材料的层；
其中所述第二半导体管芯直接接合至所述管芯附接材料的层。
3.根据权利要求1所述的封装半导体器件，其中：
所述第一组管芯焊盘为导线接合焊盘；并且
所述第一连接器为导线接合。
4.根据权利要求3所述的封装半导体器件，其中：
所述第二组外部连接器为焊料焊盘；并且
所述第一连接器提供所述第一组管芯焊盘中的第一管芯焊盘与所述第二组外部连接器中的外部连接器之间的电连接。
5.根据权利要求3所述的封装半导体器件，其中：
所述第二组外部连接器为引线框上的引线；并且
所述第一连接器提供所述第一组管芯焊盘中的第一管芯焊盘与所述第二组外部连接器中的外部连接器之间的直接物理连接。
6.根据权利要求1所述的封装半导体器件，其中：
所述第二组外部连接器为焊料焊盘；并且
所述第一连接器提供所述第一组管芯焊盘中的第一管芯焊盘与所述第二组外部连接器中的外部连接器之间的电连接。
7.根据权利要求1所述的封装半导体器件，其中：
所述第二栅阵列型封装为球栅阵列；并且
所述第二组外部连接器为焊料焊盘。
8.根据权利要求1所述的封装半导体器件，其中：
所述第二半导体管芯与所述第二包封剂直接接触；
所述第二包封剂为模制材料；并且
所述第二半导体管芯具有的横向尺寸比所述第一半导体管芯小。
9.根据权利要求1所述的封装半导体器件，其中：
所述第二半导体管芯与所述第二包封剂直接接触；
所述第二包封剂为模制材料；并且
所述第二半导体管芯具有的横向尺寸比所述第一半导体管芯大。
10.根据权利要求1所述的封装半导体器件，其中：
所述第一表面是所述第一栅阵列型封装的上表面；
所述第一半导体管芯具有第二组管芯焊盘；
所述第一组管芯焊盘位于所述第二半导体管芯的上表面上；并且
所述第二组管芯焊盘位于所述第一半导体管芯的上表面上。
11.根据权利要求1所述的封装半导体器件，其中：
所述第一组外部连接器由所述第二组外部连接器的范围环绕；并且
所述第一栅阵列型封装具有的横向尺寸比所述第二栅阵列型封装小。
12.根据权利要求1所述的封装半导体器件，其中：
所述第一组外部连接器由所述第二组外部连接器环绕。
13.根据权利要求1所述的封装半导体器件，还包含：
使所述第一组管芯焊盘中的第二管芯焊盘与所述第一组外部连接器中的外部连接器互连的第二连接器；
其中所述第二包封剂覆盖所述第二连接器；并且
其中所述第二组外部连接器为焊料焊盘。
14.根据权利要求13所述的封装半导体器件，其中：
所述第一组管芯焊盘为导线接合焊盘；
所述第一连接器为第一导线接合；并且
所述第二连接器为第二导线接合。
15.根据权利要求14所述的封装半导体器件，其中：
所述第二组外部连接器为焊料焊盘；并且
所述第一连接器提供所述第一组管芯焊盘中的第一管芯焊盘与所述第二组外部连接器中的外部连接器之间的电连接。
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