CN101232012A - 堆栈式半导体封装结构 - Google Patents

堆栈式半导体封装结构 Download PDF

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CN101232012A
CN101232012A CNA2008100810516A CN200810081051A CN101232012A CN 101232012 A CN101232012 A CN 101232012A CN A2008100810516 A CNA2008100810516 A CN A2008100810516A CN 200810081051 A CN200810081051 A CN 200810081051A CN 101232012 A CN101232012 A CN 101232012A
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洪松井
黄文彬
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Advanced Semiconductor Engineering Inc
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Abstract

本发明是关于一种堆栈式半导体封装结构，其包括一载体、一第一半导体组件、一第二半导体组件、数条第一导线及数条第二导线。该载体具有数个电性连接处。该第一半导体组件具有数个第一焊垫。该第二半导体组件具有数个第二焊垫，该第二半导体组件是迭设于该第一半导体组件之上。所述第一导线电性连接该第一半导体组件的所述第一焊垫及该载体的所述电性连接处。所述第二导线电性连接该第二半导体组件的所述第二焊垫及该载体的所述电性连接处，其中所述第二导线的外径是大于所述第一导线的外径。藉此，可以减少导线材料的使用，进而减少制造成本。

Description

堆栈式半导体封装结构
技术领域
本发明是关于一种堆栈式半导体封装结构，详言之，是关于一种具有不同粗细的导线的堆栈式半导体封装结构。
背景技术
参考图1，显示习知堆栈式半导体封装结构的俯视示意图，其中省略了封胶材料。参考图2，显示习知堆栈式半导体封装结构的剖视示意图。该堆栈式半导体封装结构1包括一基板11、一第一晶粒12、一第二晶粒13、数条第一导线14、数条第二导线15及一封胶材料16。
该基板11的上表面具有数个手指111、一接地区112及一电源区113。所述手指111、该接地区112及该电源区113是环绕该第一晶粒12及该第二晶粒13。该第一晶粒12的下表面是利用一黏胶17黏附于该基板11的上表面。该第一晶粒12的上表面具有数个第一焊垫121。所述第一导线14是电气连接所述第一焊垫121至该接地区112或该电源区113。
该第二晶粒13的下表面是利用一黏胶18黏附于该第一晶粒12的上表面。该第二晶粒13的上表面具有数个第二焊垫131。所述第二导线15是电气连接所述第二焊垫131至所述手指111、该接地区112或该电源区113。该封胶材料16是包覆该基板11的上表面、该第一晶粒12、该第二晶粒13、所述第一导线14及所述第二导线15。
该习知半导体封装结构1的缺点为，所述第一导线14及所述第二导线15的外径皆相同，而导致导线材料的浪费，尤其现今所述导线的材质多为金，其会增加更多的制造成本。此外，所述第一导线14无法设定较低的弧度，否则容易发生球颈撕裂的情况，但是如果所述第一导线14的弧度过高，可能会有碰到所述第二导线15的风险。
因此，有必要提供一种创新且具进步性的堆栈式半导体封装结构，以解决上述问题。
发明内容
本发明的主要目的在于提供一种堆栈式半导体封装结构，其包括一载体、一第一半导体组件、一第二半导体组件、数条第一导线及数条第二导线。该载体具有数个电性连接处。该第一半导体组件具有数个第一焊垫。该第二半导体组件具有数个第二焊垫，该第二半导体组件是迭设于该第一半导体组件之上。所述第一导线电性连接该第一半导体组件的所述第一焊垫及该载体的所述电性连接处。所述第二导线电性连接该第二半导体组件的所述第二焊垫及该载体的所述电性连接处，其中所述第二导线的外径是大于所述第一导线的外径。
藉此，可以减少导线材料的使用，进而减少制造成本。此外，所述第一导线的外径较小，因此可以有效地降低弧高，而不易发生球颈撕裂的情况。
附图说明
图1显示习知堆栈式半导体封装结构的俯视示意图，其中省略了封胶材料；
图2显示习知堆栈式半导体封装结构的剖视示意图；
图3显示本发明堆栈式半导体封装结构的实例1的俯视示意图，其中省略了封胶材料；
图4显示本发明堆栈式半导体封装结构的实例1的剖视示意图；
图5显示本发明堆栈式半导体封装结构的实例2的俯视示意图，其中省略了封胶材料；
图6显示本发明堆栈式半导体封装结构的实例3的俯视示意图，其中省略了封胶材料；
图7显示本发明堆栈式半导体封装结构的实例4的俯视示意图，其中省略了封胶材料；
图8显示本发明堆栈式半导体封装结构的实例4的剖视示意图；
图9显示本发明堆栈式半导体封装结构的实例5的俯视示意图，其中省略了封胶材料；及
图10显示本发明堆栈式半导体封装结构的实例5的剖视示意图。
具体实施方式
本发明是关于一种堆栈式半导体封装结构，其包括一载体、第一半导体组件、一第二半导体组件、数条第一导线及数条第二导线。
该载体具有数个电性连接处。在本发明中，该载体可以是一基板(Substrate)或是一导线架(Leadframe)的形式。当该载体是基板时，该第一半导体组件是直接黏附于该基板上表面，且该第二半导体组件是迭设于该第一半导体组件之上。此时，所述电性连接处是数个为手指(Finger)、一接地区或一电源区。
当该载体是导线架时，其具有一晶粒承座，而该第一半导体组件则黏附于该晶粒承座上，且该第二半导体组件是迭设于该第一半导体组件之上。此时，所述电性连接处为数个引脚(Lead)、一接地区或一电源区。
该第一半导体组件具有数个第一焊垫。较佳地，该第一半导体组件为一第一晶粒。所述第一焊垫的面积可以皆相同，或是其具有不同的尺寸。此外，所述第一焊垫也可以排列成一列或是多列。该第二半导体组件具有数个第二焊垫。较佳地，该第二半导体组件为一第二晶粒。所述第二焊垫的面积可以皆相同，或是其具有不同的尺寸。此外，所述第二焊垫也可以排列成一列或是多列。
所述第一导线电性连接该第一半导体组件的所述第一焊垫及该载体的所述电性连接处。所述第二导线电性连接该第二半导体组件的所述第二焊垫及该载体的所述电性连接处，其中所述第二导线的外径是大于所述第一导线的外径。举例而言，所述第一导线的外径为所述第二导线的外径的0.9倍以下，惟该第一导线外径的选择考虑，是以依其导线强度在封装时仍不受封装胶体模流的影响为主。较佳地，所述第二导线的长度是大于所述第一导线的长度，且所述第二导线所接触的第二焊垫的面积是大于所述第一导线所接触的第一焊垫的面积。
本发明的优点为，所述第二导线的外径不同于所述第一导线的外径，因此可以减少导线材料的使用，进而减少制造成本。此外，所述第一导线的外径较小，因此可以有效地降低弧高，而不易发生球颈撕裂的情况。
兹以下列实例予以详细说明本发明，唯并不意味本发明仅局限于此等实例所揭示的内容。
实例1：
参考图3，显示本发明堆栈式半导体封装结构的实例1的俯视示意图，其中省略了封胶材料。参考图4，显示本发明堆栈式半导体封装结构的实例1的剖视示意图。该堆栈式半导体封装结构2包括一基板21、一第一晶粒22、一第二晶粒23、数条第一导线24、数条第二导线25及一封胶材料26。
该基板21的上表面具有数个手指211、一接地区212及一电源区213。所述手指211、该接地区212及该电源区213是环绕该第一晶粒22及该第二晶粒23。该第一晶粒22的下表面是利用一黏胶27黏附于该基板11的上表面。该第一晶粒22的上表面具有数个第一焊垫221。所述第一导线24是电气连接所述第一焊垫221及该接地区212或该电源区213。
该第二晶粒23的下表面是利用一黏胶28黏附于该第一晶粒22的上表面。该第二晶粒23的上表面具有数个第二焊垫231。所述第二导线25是电气连接所述第二焊垫231及所述手指211或该电源区213。所述第二导线25的长度是大于所述第一导线24的长度，且所述第二导线25的外径是大于所述第一导线24的外径。
该封胶材料26是包覆该基板21的上表面、该第一晶粒22、该第二晶粒23、所述手指211、该接地区212、该电源区213、所述第一导线24及所述第二导线25。
实例2：
参考图5，显示本发明堆栈式半导体封装结构的实例2的俯视示意图，其中省略了封胶材料。本实例的半导体封装结构2A与实例1的半导体封装结构2大致相同，不同处仅在于，在本实例中，所述第一焊垫221的面积小于所述第二焊垫231的面积。
实例3：
参考图6，显示本发明堆栈式半导体封装结构的实例3的俯视示意图，其中省略了封胶材料。该堆栈式半导体封装结构3包括一基板31、一第一晶粒32、一第二晶粒33、数条第一导线34、数条第二导线35、数条第三导线36及一封胶材料(图中未示)。
该基板31的上表面具有数个手指311、一接地区312及一电源区313。所述手指311、该接地区312及该电源区313是环绕该第一晶粒32及该第二晶粒33。该第一晶粒32的下表面是利用一黏胶(图中未示)黏附于该基板31的上表面。该第一晶粒32的上表面具有数个第一焊垫321。所述第一导线34是电气连接所述第一焊垫321及该接地区312。所述第三导线36是电气连接所述第一焊垫321及该电源区313。
该第二晶粒33的下表面是利用一黏胶黏附于该第一晶粒32的上表面。该第二晶粒33的上表面具有数个第二焊垫331。所述第二导线35是电气连接所述第二焊垫331及所述手指311。所述第二导线35的长度是大于所述第三导线36的长度，所述第三导线36的长度是大于所述第一导线34的长度。所述第二导线35的外径是大于所述第三导线36的外径，所述第三导线36的外径是大于所述第一导线34的外径。可以理解的是，在本实例中，所述第三导线36也可以电气连接所述第二焊垫331及该电源区313。
实例4：
参考图7，显示本发明堆栈式半导体封装结构的实例4的俯视示意图，其中省略了封胶材料。参考图8，显示本发明堆栈式半导体封装结构的实例4的剖视示意图。该堆栈式半导体封装结构4包括一基板41、一第一晶粒42、一第二晶粒43、一第三晶粒44、数条第一导线45、数条第二导线46、数条第三导线47及一封胶材料48。
该基板41的上表面具有数个手指411、一接地区412及一电源区413。所述手指411、该接地区412及该电源区413是环绕该第一晶粒42、该第二晶粒43及该第三晶粒44。该第一晶粒42的下表面是利用一黏胶491黏附于该基板41的上表面。该第一晶粒42的上表面具有数个第一焊垫421。所述第一导线45是电气连接所述第一焊垫421及该接地区412。
该第二晶粒43的下表面是利用一黏胶492黏附于该第一晶粒42的上表面。该第二晶粒43的上表面具有数个第二焊垫431。所述第二导线46是电气连接所述第二焊垫431及该电源区413。该第三晶粒44的下表面是利用一黏胶493黏附于该第二晶粒43的上表面。该第三晶粒44的上表面具有数个第三焊垫441。所述第三导线47是电气连接所述第三焊垫441及所述手指411。
所述第三导线47的长度是大于所述第二导线46的长度，所述第二导线46的长度是大于所述第一导线45的长度。所述第三导线47的外径是大于所述第二导线46的外径，所述第二导线46的外径是大于所述第一导线45的外径。
该封胶材料48是包覆该基板41的上表面、该第一晶粒42、该第二晶粒43、该第三晶粒44、所述手指411、该接地区412、该电源区413、所述第一导线45、所述第二导线46及所述第三导线47。
在本实例中，所述第一焊垫421、所述第二焊垫431及所述第三焊垫441的面积是相同。可以理解的是，所述第一焊垫421的面积可以小于所述第二焊垫431的面积，且所述第二焊垫431的面积可以小于所述第三焊垫441的面积。
实例5：
参考图9，显示本发明堆栈式半导体封装结构的实例5的俯视示意图，其中省略了封胶材料。参考图10，显示本发明堆栈式半导体封装结构的实例5的剖视示意图。该堆栈式半导体封装结构5包括一导线架(Leadframe)51、一第一晶粒52、一第二晶粒53、数条第一导线54、数条第二导线55及一封胶材料56。
该导线架51具有一晶粒承座(Die Pad)511及数个引脚(Lead)512。所述引脚512是环绕该晶粒承座511。该第一晶粒52的下表面是利用一黏胶57黏附于该晶粒承座511的上表面。该晶粒承座511具有一接地区513，其是环绕该第一晶粒52。该第一晶粒52的上表面具有数个第一焊垫521。所述第一导线54是电气连接所述第一焊垫521及该接地区513。
该第二晶粒53的下表面是利用一黏胶58黏附于该第一晶粒52的上表面。该第二晶粒53的上表面具有数个第二焊垫531。所述第二导线55是电气连接所述第二焊垫531及所述引脚512。所述第二导线55的长度是大于所述第一导线54的长度，且所述第二导线55的外径是大于所述第一导线55的外径。
该封胶材料56是包覆该导线架51的该晶粒承座511、该第一晶粒52、该第二晶粒53、所述引脚512、该接地区513、所述第一导线54及所述第二导线55。
惟上述实施例仅为说明本发明的原理及其功效，而非用以限制本发明。因此，习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求所列。

Claims (10)

1.一种堆栈式半导体封装结构，包括：
载体，具有数个电性连接处；
第一半导体组件，具有数个第一焊垫；
第二半导体组件，具有数个第二焊垫，该第二半导体组件是迭设于该第一半导体组件之上；
数条第一导线，电性连接该第一半导体组件的所述第一焊垫及该载体的所述电性连接处；及
数条第二导线，电性连接该第二半导体组件的所述第二焊垫及该载体的所述电性连接处，其中所述第二导线的外径是大于所述第一导线的外径。
2.如权利要求1所述的堆栈式半导体封装结构，其中该载体为一基板，所述电性连接处包括数个手指，该第一半导体组件为第一晶粒，该第二半导体组件为第二晶粒。
3.如权利要求2所述的堆栈式半导体封装结构，其中所述电性连接处更包括接地区及电源区。
4.如权利要求3所述的堆栈式半导体封装结构，其中所述第一导线电性连接所述第一焊垫及该接地区与该电源区，所述第二导线电性连接所述第二焊垫及所述手指。
5.如权利要求1所述的堆栈式半导体封装结构，其中该载体为导线架，更具有晶粒承座，所述电性连接处包括数个引脚，该第一半导体组件为第一晶粒，该第二半导体组件为第二晶粒
6.如权利要求5所述的堆栈式半导体封装结构，其中所述电性连接处更包括接地区及电源区。
7.如权利要求5所述的堆栈式半导体封装结构，其中所述第一导线电性连接所述第一焊垫及该接地区与该电源区，所述第二导线电性连接所述第二焊垫及所述引脚。
8.如权利要求1所述的堆栈式半导体封装结构，其中所述第一焊垫的面积小于所述第二焊垫的面积。
9.如权利要求1所述的堆栈式半导体封装结构，其中所述第一导线的长度小于所述第二导线的长度。
10.如权利要求1所述的堆栈式半导体封装结构，更包括第三半导体组件及数条第三导线，该第三半导体组件是迭设于该第二半导体组件之上，且其具有数个第三焊垫，所述第三导线电性连接该第三半导体组件的所述第三焊垫及该载体的所述电性连接处，其中所述第三导线的外径不同于所述第一导线及所述第二导线的外径。
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CN102522391A (zh) * 2011-12-31 2012-06-27 天水华天科技股份有限公司 一种具有接地环的e/LQFP堆叠封装件及其生产方法
CN102891123A (zh) * 2011-07-22 2013-01-23 飞思卡尔半导体公司 堆叠式管芯半导体封装体

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CN100336221C (zh) * 2002-11-04 2007-09-05 矽品精密工业股份有限公司 可堆栈半导体封装件的模块化装置及其制法
CN2617038Y (zh) * 2003-03-24 2004-05-19 立卫科技股份有限公司 多层芯片堆栈式封装结构

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CN102891123A (zh) * 2011-07-22 2013-01-23 飞思卡尔半导体公司 堆叠式管芯半导体封装体
CN107994004A (zh) * 2011-07-22 2018-05-04 超大规模集成电路技术有限责任公司 堆叠式管芯半导体封装体
CN102522391A (zh) * 2011-12-31 2012-06-27 天水华天科技股份有限公司 一种具有接地环的e/LQFP堆叠封装件及其生产方法
CN102522391B (zh) * 2011-12-31 2014-11-05 天水华天科技股份有限公司 一种具有接地环的e/LQFP堆叠封装件及其生产方法

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