JP4976284B2 - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
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Description
この場合、上側に積層される半導体素子(第2の半導体素子という)が既に基板上に搭載されている半導体素子(第1の半導体素子という)よりも小さいときには、第1の半導体素子のワイヤ部分が積層により損なわれることはないが、同程度又はそれ以上に大きいときには、このワイヤ部分が積層により損なわれる問題がある。
例えば、スペーサー構造を採用した半導体装置がある。第2の半導体素子と第1の半導体素子の間に厚みの大きなスペーサーを挟むことで、第2の半導体素子と第1の半導体素子の間に一定の間隔が確保され、第2の半導体素子の形状及び大きさに関わらず、第1の半導体素子のワイヤ部分が損なわれることなく第2の半導体素子を積層することができる。しかし、その間隔を確保するために、十分な厚みを有するスペーサーを用いる必要があり、パッケージの薄型化には不向きであった。
同様な例として、樹脂層が3層からなる半導体装置もあり、中間層に一定の硬度を持ったポリイミドを介挿させ、保護材として機能させている(特許文献3参照。)。
上記のいずれの例においても、従来のスタックドパッケージの製造工程が簡略化され、低コスト化が実現されている。
他方、ポリイミドのような硬度の大きなフィルム(絶縁層)を第2の半導体素子と第1の半導体素子の間に介挿させる場合においても、フィルムを接着層と貼り合せ、多層化する工程が必要となり、また、フィルムと接着層を空隙なく貼り合せる技術が求められる。フィルムと接着層の間に発生する空隙は、信頼性試験の吸湿リフロー時に界面剥離、クラック等を生じる原因となる。
該第1の半導体素子上に該第2の半導体素子を積層するに際し、シリカ含有量が50〜80質量%であるエポキシ樹脂組成物を、粘度が1〜60Pa・sの範囲にある半溶融状態で、50〜200μmの厚み範囲で該第1の半導体素子と該第2の半導体素子の間に介在させて接着層となし、該接着層により、該第1の半導体素子と該第2の半導体素子とを結合させるとともに、該第1の半導体素子に接続されるワイヤーの一部を被覆し、その後、該接着層を加熱により硬化させること、第2の半導体素子の幅が第1の半導体素子の幅の90〜300%であること、基板と第1の半導体素子、及び第1の半導体素子と第2の半導体素子を、それぞれ同一組成のエポキシ樹脂組成物の接着層により結合させること、及び基板と第1の半導体素子を接着層により仮圧着し、ついで該接着層を熱により硬化させることを特徴とする。
半導体装置10は、基板(配線基板)12上に接着層14を介して搭載され、ワイヤボンディング方式によりワイヤ16で基板12と接続されたフェイスアップ状態の第1の半導体素子18上に、接着層20を介して第2の半導体素子22を積層した構造を有する。ここで、接着層20は、シリカ、エポキシ樹脂を必須成分とし、シリカ含有量が50〜80質量%であるエポキシ樹脂組成物からなる。このエポキシ樹脂組成物は熱硬化されることによって、硬化された接着層となる。この接着層の厚みは、10〜300μmの範囲である。
本発明の半導体装置の製造方法によれば、ワイヤボンディング方式により基板12と電気的に接続されたフェイスアップ状態の第1の半導体素子18上に、第2の半導体素子22を積層し、基板上に少なくとも2つの積層された半導体素子を構成部品として有する半導体装置が得られる。
ここで、絶縁被覆は、第1の半導体素子に接続されるワイヤの一部、言い換えれば第1の半導体素子上に配置されるワイヤ部分のみに設けてもよいが、第1の半導体素子と基板とを接続するワイヤ全体に設けると、より好適である。
これにより、ワイヤと第2の半導体素子間の接触を回避することができ、第1の半導体素子と第2の半導体素子の間に介在される接着層の厚みも更に薄くでき、半導体装置の薄型化を実現することができる。
半導体装置10は、基板(配線基板)12上に接着層(熱硬化性接着層)14を介して搭載され、ワイヤボンディング方式により金線16で基板12と接続されたフェイスアップ状態の第1の半導体素子18上に、接着層(熱硬化性接着層)20を介して第2の半導体素子22を積層した構造を有する。図1中、参照符号24は、基板12等の表面に形成されるワイヤボンディング電極パターンを示す。
接着層20は、エポキシ樹脂、シリカフィラーを主成分とし、シリカフィラーが高充填された熱硬化性フィルム状接着剤である。なお、接着層14は、接着層20と同様の構成であってもよく、また、他の構成としてもよい。本実施例では、シリカフィラーを70質量%含有するエポキシ樹脂組成物を厚さ90μmの熱硬化性フィルム状接着剤として使用した。なお、この熱硬化性フィルム状接着剤は、硬化後、線膨張係数が20ppm/K、ガラス転移温度が170℃、弾性率が16000MPaであった。接着層20の厚みは、用いたワイヤループの高さにより異なるが、ここでは、90μmとした。
まず、周知の方法により、ウエハに接着層14を貼付け、これをダイシングテープ へ貼付けた後、 ダイシングし個片化により第1の半導体素子18を作製した。
裏面に接着層14を貼付けた第1の半導体素子18は、図3に示すように、基板12にダイマウントにより仮圧着し、150℃〜180℃で1時間、接着層14を硬化させた。
この際、接着層14の厚みは半導体パッケージの薄型化のために、できる限り薄くすることが望ましい。
半導体装置10aは、ワイヤボンディングに用いる金線16、16aが例えば絶縁性のポリウレタン樹脂からなる絶縁被覆層26で被覆されたものである。半導体装置10aは、半導体素子22と金線16aとの接触を懸念する必要がないため、接着層20aの厚みは、より薄くでき、例えば100μm以下とすることができる。
Claims (2)
- ワイヤボンディング方式により基板と接続されたフェイスアップ状態の第1の半導体素子上に、第2の半導体素子を積層し、ワイヤボンディングによって第2の半導体素子を基板と接続して基板上に少なくとも2つの積層された半導体素子を構成部品として有する半導体装置の製造方法において、
該第1の半導体素子上に該第2の半導体素子を積層するに際し、シリカ含有量が50〜80質量%であるエポキシ樹脂組成物を、粘度が1〜60Pa・sの範囲にある半溶融状態で、50〜200μmの厚み範囲で該第1の半導体素子と該第2の半導体素子の間に介在させて接着層となし、該接着層により、該第1の半導体素子と該第2の半導体素子とを結合させるとともに、該第1の半導体素子に接続されるワイヤーの一部を被覆し、その後、該接着層を加熱により硬化させること、第2の半導体素子の幅が第1の半導体素子の幅の90〜300%であること、基板と第1の半導体素子、及び第1の半導体素子と第2の半導体素子を、それぞれ同一組成のエポキシ樹脂組成物の接着層により結合させること、及び基板と第1の半導体素子を接着層により仮圧着し、ついで該接着層を熱により硬化させることを特徴とする半導体装置の製造方法。 - 第1の半導体素子が、絶縁被覆されたワイヤにより基板と接続される請求項1記載の半導体装置の製造方法。
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