TWI382521B - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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Publication number
TWI382521B
TWI382521B TW095110567A TW95110567A TWI382521B TW I382521 B TWI382521 B TW I382521B TW 095110567 A TW095110567 A TW 095110567A TW 95110567 A TW95110567 A TW 95110567A TW I382521 B TWI382521 B TW I382521B
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semiconductor element
semiconductor
semiconductor device
substrate
adhesive layer
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TW095110567A
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TW200703615A (en
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Minoru Morita
Kouji Nakamura
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Nippon Steel Chemical Co
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Publication of TW200703615A publication Critical patent/TW200703615A/zh
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Publication of TWI382521B publication Critical patent/TWI382521B/zh

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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Description

半導體裝置的製造方法及半導體裝置
本發明係有關一種具有藉由積層搭載複數個半導體元件，以提高安裝密度的封裝構造的半導體裝置(以下，將此稱為疊層封裝體)的製造方法及半導體裝置。
近年來，藉由在單一封裝體內撘載複數個半導體元件，而謀求半導體裝置的小型化、高性能化。例如有：藉著組合具有信號的高速處理功能的元件、和具有記憶功能的元件，而對於搭載於攜帶型電子機器等的記憶體給予附加價值，或係為了增大記憶容量，而積層搭載複數個半導體元件而搭載的疊層封裝體等。
半導體裝置有使用任一手法將半導體元件和基板電性連接的需要。現在，藉由打線接合的方式，以金屬線連接兩者為主流。
此時，當積層於上側的半導體元件(稱為第2半導體元件)比搭載於基板上的半導體元件小(稱為第1半導體元件)時，雖然第1半導體元件的金屬線部份，不因為積層而損失，但是當為相同程度或係大於此以上時，該金屬線部份有因為積層而損失的問題。
為了解決這種問題，而提案實現有各種有關半導體元件的積層的構造以及其製造方法。
例如，有採用間隔件構造的半導體裝置。在第2半導體元件和第1半導體元件之間，藉著挾持厚度大的間隔件，而可在第2半導體元件和第1半導體元件之間確保一定的間隔，與第2半導體元件的形狀及大小無關，而不會造成第1半導體元件的金屬線部份損失，而可積層第2半導體元件。但是，為了確保其間隔，必須使用具有足夠厚度的間隔件，而不利於封裝體的薄型化。
因應這種封裝體的薄型化的問題，而實現一種無間隔件的疊層封裝體。專利文件1所示的半導體裝置，藉由斜切而使第1半導體元件的元件形成面的緣部形成傾斜狀。該半導體元件不使用間隔件，而具有上側半導體元件的接著層，覆蓋下側半導體元件配線面上的中心襯墊以及金屬線的一部份而固定化的構造，與間隔件構造相比可實現薄型化。
又，有藉著多層化上側半導體元件的樹脂層，而避免半導體元件和金屬線的接觸之例。例如，有介插於上側半導體元件和下側半導體元件間的樹脂層，係由接著層和絕緣層等2層所構成的半導體裝置(參照專利文獻2)。使用15至30 μ m的厚度的聚亞醯胺作為絕緣層。藉由該2層構造的樹脂層，避免與上側半導體元件和下側半導體元件的金屬線部份的接觸。
同樣的例，亦有由3層樹脂層構成的半導體裝置，於中間層介插具有一定硬度的聚亞醯胺，作為保護材的功能(參照專利文獻3)。
即使在上述任一種例子中，亦可簡略化以往的疊層封裝體的製造步驟，可實現低成本化。
[專利文獻1]日本特開2004－282056號公報[專利文獻2]日本特開2002－222913號公報[專利文獻3]日本特開2004－72009號公報
然而，藉由上述斜切手法，將半導體元件端部形成傾斜狀時，除了一般的步驟之外，另增加有：1)藉由斜切手法研削第1半導體元件端部的步驟，以及2)除去接著層的一部份的步驟，而有成本上升的問題。又，在研削半導體元件時，亦有導致半導體裝置的功能降低之疑慮。
另外，即使將聚亞醯胺一般硬度大的薄膜(絕緣層)介插於第2半導體元件和第1半導體元件之間時，亦需要將薄膜與接著層接合而多層化的步驟，而要求沒有空隙地接合薄膜和接著層的技術。在薄膜和接著層之間所產生的空隙，在信賴性試驗的吸濕回銲時，會導致產生界面剝離、裂縫等的原因。
本發明係有鑑於上述課題和研創者，目的在於提供一種步驟簡略且成本低廉的無間隔件疊層封裝體型的半導體裝置製造方法以及半導體裝置。
有關本發明的半導體裝置的製造方法，係於藉由打線接合方式與基板連接的面朝上狀態之第1半導體元件上，積層第2半導體元件，在基板上至少具有兩個已積層的半導體元件作為構成零件，其特徵為，在該第1半導體元件上積層該第2半導體元件時，將氧化矽、環氧樹脂作為必要成份，在黏度為1至60Pa．s的範圍的半溶融狀態下，且在10至300μm的厚度範圍內，使氧化矽含有量為50至80質量%之環氧樹脂組成物，介存於該第1半導體元件和該第2半導體元件之間，作為接著層，藉由該接著層，在使該第1半導體元件和該第2導體元件結合之同時，覆蓋與第1半導體元件連接的金屬線的一部分，然後，藉由加熱使該接著層硬化。
在此，第1半導體元件藉由已被絕緣覆蓋的金屬線與基板連接為佳。又，第2半導體元件的寬度係第1半導體元件的寬度的90至300%為佳。
在該半導體裝置的製造方法中，藉由接著層暫時壓接基板和第1半導體元件，接著藉由熱使該接著層硬化為佳。又，以分別實質上藉由相同組成的接著層，使基板和第1半導體元件、以及第1半導體元件和第2半導體元件結合為佳。
又，本發明之半導體裝置，係於藉由打線接合方式與基板連接的面朝上狀態之第1半導體元件上，積層第2半導體元件，在基板上至少具有兩個已積層的半導體元件作為構成零件，其特徵為，在該第1半導體元件和該第2半導體元件之間，以氧化矽、環氧樹脂作為必要成份，在10至300 μ m的厚度範圍內，形成由氧化矽含有量為50至80質量%之環氧樹脂組成物的硬化物所構成的接著層。
前述專利文獻1所記載的半導體裝置，如第2圖所示，藉由接著層1a搭載於中介層2的第1半導體元件3a的元件形成面的緣部，藉由斜切形成傾斜狀a。藉由該構成，從第1半導體元件3a的中心襯墊4延伸於中介層2上的銲線5，可降低因為第1半導體元件3a的緣部所受的損傷。又，該半導體裝置之第2半導體元件3b和第1半導體元件3a之間所設置的接著層1b，形成為小於第1半導體元件3a，藉此，由於在第1半導體元件3a和第2半導體元件3b之間有間隙，因此可防止銲線5和第2半導體元件3b的干涉。
藉由第1圖說明本發明半導體裝置之一例的剖面圖。半導體裝置10係藉由接著層14搭載於基板(配線基板)12上，藉由打線接合方式，以金線16和基板12連接的面朝上狀態的第1半導體元件18上，具有藉由接著層20而積層第2半導體元件22的構造。在此，接著層20係以氧化矽、環氧樹脂為必須成分。而由氧化矽含有量為50至80質量%之環氧樹脂組成物所構成。該環氧樹脂組成物藉由熱硬化而成為已經硬化之接著層，該接著層的厚度為10至300 μ m的範圍。
本發明之半導體裝置，藉著在第1半導體元件和第2半導體元件之間，介存比較厚的熱硬化性之接著層，而在第1半導體元件和第2半導體元件之間，可設置與第1半導體元件連接的金屬線不與第2半導體元件之背面接觸的程度之相當的距離。設置在第1半導體元件和第2半導體元件之間的接著層由一層所構成，不需要如以往的技術般，設置硬度高的絕緣層，而可實現步驟的簡略化。
參照第3圖、第4圖及第5圖說明本發明的半導體裝置之製造方法之一例。
根據本發明的半導體裝置之製造方法，在藉由打線接合方式和基板12電性連接的面朝上狀態的第1半導體元件18上積層第2半導體元件22，而獲得具有於基板上至少積層2個半導體元件作為構成零件的半導體裝置。
在此，使用於打線接合的金線16雖沒有特別限定，但以金線為佳。又，搭載半導體元件的基板12雖沒有特別限定，但以積層基板為佳，又，亦可為由單一層所構成的基板。又，半導體元件18、22無特別限定，可為二極體、電晶體、IC等。
積層於第1半導體元件上的半導體元件，不僅限於第2半導體元件，更可於第2半導體元件上積層第3半導體元件，更可積層第4以後的半導體元件。此等半導體元件與第1半導體元件的情況相同，雖藉由打線接合可設為與基板電性連接的構造，但不限定於此。
於第1半導體元件上積層第2半導體元件時，設置介存於第1半導體元件與第2半導體元件之間的接著層20。該接著層20以氧化矽、環氧樹脂為必須成分，在黏度為1至60Pa．S的範圍的半溶融狀態下，在10至300 μ m的厚度範圍內，將氧化矽含有量為50至80質量%之環氧樹脂組成物接著於第1半導體元件而形成。該環氧樹脂組成物為50℃以上，更以60℃至120℃溶融或半溶融，而表示上述黏度較為理想。然後，亦可為120℃以上、或在150℃至200℃內加熱0.5至3小時，使之硬化。
在此，接著層20由於確保表示搭載後的半導體元件之平坦性的BLT(Bond lone Thickness，介面厚度)的穩定，而以由薄膜狀環氧樹脂組成物構成的薄膜狀接著劑為佳。此外，薄膜狀接著劑除了環氧樹脂成分之外，以含有硬化劑為佳，這種熱硬化性的薄膜狀接著劑具有在硬化後穩定的尺寸穩定性和耐熱性。具體而言，硬化後的接著層20的線膨脹係數為10至50ppm/K，玻璃轉移溫度為150℃至170℃，彈性率為7000至17000MPa的範圍內為佳。接著層20的厚度雖為10至300 μ m的範圍，但以50至200 μ m的範圍為佳。
此時，以覆蓋配置於和第1半導體元件連接的金線16的一部份，換言之，即以覆蓋配置於第1半導體元件上的金屬線的部份之方式，設置接著層20。然後，藉由加熱使接著層硬化。再者，藉由打線接合，使第2半導體元件和基板電性連接。更於第2半導體元件上積層半導體元件時，反覆以下相同的步驟。
該接著層20係以氧化矽高充填，由於溶融黏度低，因此在高溫的半溶融狀態下，藉著與第1半導體元件接著，而不會對於金屬線施加負荷，可覆蓋金屬線的一部份。如此，由於可容易地確保半導體裝置的絕緣性，因此亦可容易地製造由複數個半導體元件所構成的疊層封裝體的製造。
在本發明之半導體裝置之製造方法中，第1半導體元件至少一部份藉由絕緣覆蓋的金屬線與基板連接較為理想。此外，以第2半導體元件為開始與第3以後的半導體元件連接的金屬線，亦可為相同的構成。
在此，絕緣覆蓋係僅於與第1半導體元件連接的金屬線的一部份，即僅設置於配置在第1半導體元件上的金屬線部份亦可，但當設置於連接第1半導體元件和基板的金屬線全體時更為理想。
絕緣覆蓋材料雖然可以使用例如：聚氨酯樹脂、聚酯樹脂、聚亞醯胺、酯醯胺樹脂、酯亞醯胺樹脂、環氧樹脂等絕緣性樹脂，但並不限定於此，絕緣覆蓋的厚度，雖亦依存於金屬線的條件，但例如為5至40 μ m左右。
藉此，可避免金屬線和第2半導體元件間的接觸，而可以使介存於第1半導體元件和第2半導體元件之間的接著層的厚度更薄，而可實現半導體裝置的薄型化。
然後，第2半導體元件的寬度以前述第1半導體元件的寬度的90至300%較為理想。半導體元件雖然一般為具有某厚度的四邊形狀，但此時所謂的寬度係縱或橫的長度。在此，縱及橫的寬度的任一方、更佳係為兩方均滿足上述值為佳。藉此，擴大配線面的大小之自由度，特別是確保寬廣範圍，而維繫半導體裝置的高功能化。
在半導體裝置之製造方法中，藉由接著層14暫時壓接基板和第1半導體元件，然後以其他步驟，藉由熱使接著層硬化為佳。藉此，以暫時壓接(衝模安裝步驟)沒有孔隙地將接著層搭載於基板上，然後經過加硫步驟，達成接著層的高彈性率，使所積層的第1半導體元件成為強固的基礎，在積層第2半導體元件之際，亦可承受需要的特定的荷重。
結合基板和第1半導體元件的接著層14所使用的接著劑，與由使用在接著層20的環氧樹脂組成物所構成的接著劑實質上為相同組成即可。此時，雖然可使用設為薄膜狀的接著劑，但厚度亦可比使用在接著層20的薄膜接著劑薄。而更以設為其之10至70%的厚度為較佳。由環氧樹脂組成物所構成的接著劑，由於在硬化前表示接著性，因此雖可暫時壓接，但熱硬化後則固接。藉此，可簡略化從晶圓製作第1半導體元件及第2半導體元件的步驟。
舉出實施例，說明本發明。此外，本發明不限定以下所說明之實施例。
[實施例1]
第1圖係藉由本發明之半導體裝置之製造方法所製造的半導體裝置之剖面圖。
半導體裝置10係隔著接著層(熱硬化性接著層)14搭載於基板(配線基板)12上，藉由打線接合方式，於以金線16與基板12連接的面朝上狀態的第1半導體元件18上，具有隔著接著層(熱硬化性接著層)20而積層第2半導體元件22的構造。第1圖中，參照符號24係表示形成於基板12等的表面的打線接合電極圖案。
接著層20係以環氧樹脂、氧化矽填料為主成分，氧化矽填料為高充填的熱硬化性薄膜狀接著劑。此外，接著層14亦可為與接著層20相同的構成，又，亦可為其他構成。在本實施例中，使用含有70質量%的氧化矽填料的環氧樹脂組成物，作為厚度90 μ m的熱硬化性薄膜狀接著劑。此外，該熱硬化性薄膜狀接著劑在硬化後，線膨脹係數為20ppm/K，玻璃轉移溫度為170℃，彈性率為16000MPa。接著層20的厚度依據所使用的金屬環高度而不同，在此設為90 μ m。
參照第3至5圖，說明半導體裝置10的製造方法。首先，根據周知的方法，於晶圓黏貼接著層14，而將其黏貼於切割膠帶之後，藉由切割個片化製作第1半導體元件18。
在背面黏貼接著層14的第1半導體元件18，如第3圖所示，藉由衝模安裝暫時壓接於基板12，而在150℃至180℃內，1小時硬化接著層14。
此時，接著層14的厚度為了半導體封裝體的薄型化，而儘可能限制在最薄為理想。
然後，如第4圖所示，藉由打線接合，以金線16連接第1半導體元件18的配線面上的打線接合電極圖案24b與基板12的表面的打線接合電極圖案24a。
然後，如第5圖所示，於與第1半導體元件18相同的方法製作的背面連接接著層20的第2半導體元件22，在80℃至200℃內，進行10秒左右的熱處理，接著層的黏度以位於1至600Pa．s的範圍的狀態下，暫時壓接於第1半導體元件18，而使之硬化。在高溫狀態下，接著層20為液狀化，而對於第1半導體元件的配線面上的金線不會施加負荷而覆蓋。在暫時壓接之後，於150℃至180℃內，一小時硬化接著層20。
最後，藉由打線接合以金線16連接形成於第2半導體元件22表面的打線接合電極圖案24、和基板12的表面的打線接合電極圖案24，獲得第1圖所示的半導體裝置10。此外，因應需要，半導體裝置10更可進行樹脂密封等，以保護各半導體元件。
在上述步驟中，作為接著層14及接著層20的環氧熱硬化性薄膜狀接著劑以環氧樹脂、氧化矽填料為主成分。例如，日本特開2001-49220號公報所示，以3根輥子使氧化矽填料高分散化而製造。此時，在氧化矽含有量未滿50質量%，將導致薄膜接著性、線膨脹係數增大之問題，較不理想。又，超過80質量%時，作為黏合劑功能的樹脂成分不足，而觀察到組成物黏度上升，而導致薄膜變脆。因此，所含有的氧化矽填料期望在50質量%至80質量%。又，根據氧化矽填料的含有率、環氧配合量，可調整融溶黏度。
[實施例2]
根據第6圖，說明本發明其他構造的半導體裝置之剖面圖。
半導體裝置10a係將使用於打線接合的金線16、16a例如由絕緣性的聚氨酯樹脂構成的絕緣覆蓋層26予以覆蓋。半導體裝置10a由於不需要顧慮半導體元件22和金線16a的接觸，而可使接著層20a的厚度更薄，例如可為100 μ m以下。
[產業上利用的可能性]
本發明之半導體裝置的製造方法、以及本發明之半導體裝置，由於使接著層介存於第1半導體元件和第2半導體元件之間，因此與第1半導體元件連接的金屬線可設置在不與第2半導體元件之背面接觸的足夠距離。藉此，可簡略化半導體裝置的製程，可實現低成本化。又，本發明的半導體裝置之製造方法，由於以半融溶狀態，將接著層積層於第1半導體元件上，因此可減輕施加於金屬線的負荷。
10、10a．．．半導體裝置
12．．．基板
14、20、20a．．．接著層
16、16a．．．金線
18．．．第1半導體元件
22．．．第2半導體元件
24．．．打線接合電極圖案
第1圖係本發明之半導體裝置的剖面圖。
第2圖係以往的半導體裝置的剖面圖。
第3圖係說明本發明之半導體裝置的各步驟的圖。
第4圖係說明本發明之半導體裝置的各步驟的圖。
第5圖係說明本發明之半導體裝置的各步驟的圖。
第6圖係說明本發明之其他例的半導體裝置的剖面圖。
10．．．半導體裝置
12．．．基板
14、20．．．接著層
16．．．金線
18．．．第1半導體元件
22．．．第2半導體元件
24．．．打線接合電極圖案

Claims (5)

  1. 一種半導體裝置的製造方法，係於藉由打線接合方式與基板連接的面朝上狀態之第1半導體元件上，積層第2半導體元件，在基板上至少具有兩個已積層的半導體元件作為構成零件，其特徵為，在該第1半導體元件上積層該第2半導體元件時，在黏度為1至60Pa．s的範圍的半溶融狀態下，且在10至300μm的厚度範圍內，使氧化矽含有量為50至80質量%之環氧樹脂組成物，介存於該第1半導體元件和該第2半導體元件之間，作為接著層，藉由該接著層，在使該第1半導體元件和該第2導體元件結合之同時，覆蓋與該第1半導體元件連接的金屬線的一部分，然後，藉由加熱使該接著層硬化，第2半導體元件的寬度係第1半導體元件的寬度的90至300%。
  2. 如申請專利範圍第1項之半導體裝置的製造方法，其中，第1半導體元件係藉由已被絕緣覆蓋的金屬線與基板連接。
  3. 如申請專利範圍第1項之半導體裝置的製造方法，其中，藉由接著層暫時壓接基板和第1半導體元件，接著藉由熱使該接著層硬化。
  4. 如申請專利範圍第1項之半導體裝置的製造方 法，其中，分別實質上藉由相同組成的接著層，使基板和第1半導體元件、以及第1半導體元件和2半導體元件結合。
  5. 一種半導體裝置，係於藉由打線接合方式與基板連接的面朝上狀態之第1半導體元件上，積層第2半導體元件，在基板上至少具有兩個以上的已積層的半導體元件作為構成零件，其特徵為，在該第1半導體元件和該第2半導體元件之間，在10至300μm的厚度範圍內，形成由氧化矽含有量為50至80質量%之環氧樹脂組成物的硬化物所構成的接著層，第2半導體元件的寬度係第1半導體元件的寬度的90至300%。
TW095110567A 2005-03-30 2006-03-27 Semiconductor device manufacturing method and semiconductor device TWI382521B (zh)

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JP4881044B2 (ja) * 2006-03-16 2012-02-22 株式会社東芝 積層型半導体装置の製造方法
TWI314775B (en) * 2006-11-09 2009-09-11 Orient Semiconductor Elect Ltd A film and chip packaging process using the same
JP5222508B2 (ja) * 2007-09-07 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5160380B2 (ja) * 2008-11-12 2013-03-13 新日鉄住金化学株式会社 フィルム状接着剤、それを用いた半導体パッケージ及びその製造方法
JP5571045B2 (ja) * 2011-08-19 2014-08-13 株式会社東芝 積層型半導体装置

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US20010035587A1 (en) * 2000-04-26 2001-11-01 Mitsubishi Denki Kabushiki Kaisha Resin-sealed chip stack type semiconductor device
JP2004072009A (ja) * 2002-08-09 2004-03-04 Fujitsu Ltd 半導体装置及びその製造方法

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