JP5222508B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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Description
(a)第1表面、前記第1表面に形成された第1配線パターン、前記第1表面に形成された第1パッド、および前記第1表面とは反対側の第1裏面を有する第1半導体チップを準備する工程;
(b)第2表面、前記第2表面に形成された第2配線パターン、前記第2表面に形成された第2パッド、前記第2表面とは反対側の第2裏面、および前記第2裏面に形成された第1接着用フィルムを有する第2半導体チップを、前記第1パッドが前記第1接着用フィルムで覆われないように、かつ前記第2裏面が前記第1表面と対向するように、前記第1接着用フィルムを介して前記第1半導体チップの前記第1表面上に搭載する工程;
(c)前記第1半導体チップおよび前記第2半導体チップを、複数のフィラーを含有する樹脂材料で封止する工程;
ここで、
前記第2半導体チップは、半導体ウエハの裏面に接着用フィルムを貼り付けてから、前記半導体ウエハを個片化することで取得され、
前記第1接着用フィルムは、前記半導体ウエハの裏面に貼り付けられた前記接着用フィルムの一部であり、
前記(b)工程では、熱が加えられており、
前記(a)および(b)工程後、かつ前記(c)工程前の前記接着用フィルムの厚みである第1の厚みは、前記複数のフィラーのフィラー径よりも大きく、
前記フィラー径は、前記樹脂材料中に含有される前記複数のフィラーの平均粒径である。
本発明の一実施の形態の半導体装置およびその製造方法(製造工程)を図面を参照して説明する。
2 配線基板
2a 上面
2b 下面
3,4,5,6,7 半導体チップ
3a,4a,5a,6a,7a 表面
3b,4b,5b,6b,7b 裏面
8 ボンディングワイヤ
9,9b 封止樹脂
9a 樹脂材料
11a,11b,11c,11d,11e,11f,11g ダイアタッチフィルム
12 電極
13 接続端子
14 端子
15 基材層
21 配線基板
21a 上面
21b 下面
22 半導体装置領域
23 半導体ウエハ
23a 半導体チップ
24a,24b 加熱用ステージ
25 半導体チップ
26a 第1金型
26b 第2金型
26c キャビティ
27 封止体
31 ダイアタッチフィルム
32,33 半導体チップ
32a 表面
33b 裏面
34 フィラー
35 空間
37 保護膜
38 配線パターン
131 ダイアタッチフィルム
132,133 半導体チップ
132a 表面
133b 裏面
134 フィラー
135 空間
136 クラック
137 保護膜
138 配線パターン
L1,L2 距離
R1 フィラー径
R2 平均粒径
R3 最大粒径
t1,t2,t3,t4,t5,t6 厚み
Claims (12)
- 以下の工程を含むことを特徴とする半導体装置の製造方法:
(a)第1表面、前記第1表面に形成された第1配線パターン、前記第1表面に形成された第1パッド、および前記第1表面とは反対側の第1裏面を有する第1半導体チップを準備する工程;
(b)第2表面、前記第2表面に形成された第2配線パターン、前記第2表面に形成された第2パッド、前記第2表面とは反対側の第2裏面、および前記第2裏面に形成された第1接着用フィルムを有する第2半導体チップを、前記第1パッドが前記第1接着用フィルムで覆われないように、かつ前記第2裏面が前記第1表面と対向するように、前記第1接着用フィルムを介して前記第1半導体チップの前記第1表面上に搭載する工程;
(c)前記第1半導体チップおよび前記第2半導体チップを、複数のフィラーを含有する樹脂材料で封止する工程;
ここで、
前記第2半導体チップは、半導体ウエハの裏面に接着用フィルムを貼り付けてから、前記半導体ウエハを個片化することで取得され、
前記第1接着用フィルムは、前記半導体ウエハの裏面に貼り付けられた前記接着用フィルムの一部であり、
前記(b)工程では、熱が加えられており、
前記(a)および(b)工程後、かつ前記(c)工程前の前記第1接着用フィルムの厚みである第1の厚みは、前記複数のフィラーのフィラー径よりも大きく、
前記フィラー径は、前記樹脂材料中に含有される前記複数のフィラーの平均粒径である。 - 請求項1記載の半導体装置の製造方法において、
前記樹脂材料中に含有される前記複数のフィラーは、1〜10μmの粒径のフィラーを含んでいることを特徴とする半導体装置の製造方法。 - 請求項1または2記載の半導体装置の製造方法において、
前記樹脂材料中では、前記平均粒径と同じサイズの粒径を有するフィラーの数よりも、前記第1の厚みと同じサイズの粒径を有するフィラーの数が少ないことを特徴とする半導体装置の製造方法。 - 請求項1または3記載の半導体装置の製造方法において、
前記樹脂材料中に含有される前記複数のフィラーが、前記平均粒径近傍にピークを有する粒度分布を有していることを特徴とする半導体装置の製造方法。 - 請求項1または4記載の半導体装置の製造方法において、
前記(a)工程後、かつ前記(b)工程前に、上面および前記上面とは反対側の下面を有する配線基板の前記上面に、前記第1半導体チップの前記第1裏面が前記配線基板の前記上面と対向するように、前記(b)工程で使用する前記第1接着用フィルムの厚さよりも薄い第2接着用フィルムを介して搭載することを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1の厚みと前記平均粒径との差が、前記第1の厚みの1/4以上であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1の厚みと前記平均粒径との差が、5μm以上であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記樹脂材料中に含有される前記複数のフィラーの形状は、球状であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記樹脂材料中に含有される前記複数のフィラーは、酸化シリコンの粒子により形成されていることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)および(b)工程後、かつ前記(c)工程前に、前記(b)工程で使用する前記第1接着用フィルムの第1端部が、前記第2半導体チップの前記第2裏面の第2端部から第1の距離だけ前記第2半導体チップの前記第2裏面の内側方向に後退しており、
前記第2半導体チップの前記第2端部は、前記第1半導体チップの上方に位置しており、
前記第1の距離が、前記第1の厚みの1/2以上であることを特徴とする半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程後、かつ前記(b)工程前に、上面および前記上面とは反対側の下面を有する配線基板の前記上面に、前記第1半導体チップを搭載し、
前記(b)工程の後、かつ前記(c)工程の前に、前記第1パッドおよび前記第2パッドのそれぞれと前記配線基板とを複数のワイヤを介してそれぞれ電気的に接続することを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記複数のワイヤを介して前記第1パッドおよび前記第2パッドのそれぞれと前記配線基板とをそれぞれ電気的に接続する工程では、熱を加えていることを特徴とする半導体装置の製造方法。
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JP2010245412A (ja) | 2009-04-09 | 2010-10-28 | Renesas Electronics Corp | 半導体集積回路装置の製造方法 |
JP5433506B2 (ja) * | 2010-06-17 | 2014-03-05 | ラピスセミコンダクタ株式会社 | 半導体メモリ装置 |
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JP2001308262A (ja) * | 2000-04-26 | 2001-11-02 | Mitsubishi Electric Corp | 樹脂封止bga型半導体装置 |
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