TWI248649B - Method for fabricating a MOSFET having a very small channel length - Google Patents

Method for fabricating a MOSFET having a very small channel length Download PDF

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TWI248649B
TWI248649B TW091104389A TW91104389A TWI248649B TW I248649 B TWI248649 B TW I248649B TW 091104389 A TW091104389 A TW 091104389A TW 91104389 A TW91104389 A TW 91104389A TW I248649 B TWI248649 B TW I248649B
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gate layer
gate
width
layer
dielectric
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Ludwig Dittmar
Annalisa Cappellani
Dirk Schumann
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Infineon Technologies Ag
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Description

1248649 A7 B7 五、發明説明(彳 發明領域 本發明係關於一種製造金屬氧化物半導體場效電晶體 (MOSFET)的方法,該M0SFET具有一預定之極短通道:度
的閘極通道。 X 發明背景 就傳統的技術而言,其唯一的困難在於閘極通道長度低 於100 nm的電晶體,所謂次範圍(subrange)中的短通道電晶 體之可精確製造到符合所需的電操作參數。一高效能電晶 體的前提係為,例如,具有一低功率消耗之高操作電流以 及同時在關閉狀態中只有低洩漏電流。另外,閘極電阻與 諸如Miller電容的寄生效果的設計則越小越好。 於是需要利用一序列許多製程步驟所形成的電晶體在尺 寸與比例上達到尺寸上的精確。這使得目前τ-型閘極層堆 豐的製造尤其困難,因為根據理想的通道長度,其下層與 閘極層堆疊的上層比起來非常窄。 為了製造Τ-閘極電晶體,已提出許多不同的方法。因此 ’例如在預先形成的多晶矽閘極上接著沉積金屬層的丁_閘 極製造已眾所皆知。然而,由於疊層間的位置錯誤,為了 確保電晶體的操作即使在錯位的情況下也能完全令人滿意 ,因而必須增加源極/汲極接點與閘極間的距離。不過,卻 造成源極/沒極電阻增加。 短通道電晶體的說明例如由Ghani、Ahmed等人發表於 1999年國際電子裝置會議(IEdm 99),第415頁。另外,D· Hisamoto等人(發表於1997年,IEEE(電氣與電子工程師協 -4 - 本纸張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)
裝 訂
五、發明説明G 〇 ’先異向蝕刻閘極層堆疊 從而使其圖樣化。如此形成的 閘極比預定的通道長度還是寬很多。 與傳統的方法對昭之下 ,w _ ’根據本發明’並不需要先形成 長度—樣的下方閘極層,而是先製造比較 兄3隹且因此可藉助於傳統之便宜微影步驟來形 成。這使得本方法特別符合成本效益。 首先’第一閘極層的被逆置古4曰甘办 ^ p 攸‘罩方式疋其寬度大於預定的通 道長度;亦即其遮罩的勃件e 士 +幻钒仃方式是在以下第一蝕刻步驟之 後,製造一疊層堆疊包令坌 旦is第一與第二閘極層,且其寬度大 於預定的通道長度。 為了達到相當於預定通道長度的短問極長度,接下來則 錯由隨後從侧邊蝕刻下方閘極層來執行閘極層堆疊的進一 步處理。 根據本發明’為了達到這個目的,會執行第二個蝕刻步 驟。為了到達為第二閘極層所隱蔽的第一閘極層,第二姓 刻係以等向來執行。由於此等向性,第二蝕刻會引起第一 P甲層的橫向緊縮,使第—閘極層按—控制的方式縮減到 預疋的通道長度。在這種情況下,因此而獲得的短通道閘 極便是藉助於熟知之簡單製程的步驟來製造,無須採用複 雜的方法。 為了利用第二閘極層的寬度及在第二閘極層底下之第一 閘極層的控制橫向底切持續期間來控制第一閘铎層的寬度 ,因而提供一較佳具體實施例。在最簡單的情況中,蝕刻 劑濃度與其他底切參數維持固定不變,因此只有此餘刻的 1248649 A7 B7 五、發明説明(4 ) 寺、’只時間可決定下方閘極的長度。在這種情況下,第一閘 極層的預定寬度最好等於預定的通道長度。 本發明提供一項發展可提供在藉助於蝕刻劑濃度來底切 的期間控制第一閘極層的寬度。在這種情況下,濃度值在 蝕刻期間可設定為固定不變,或是在蝕刻的過程中改變。 第一閘極層的預定寬度最好等於預定的通道長度。換句 活况,在長度與寬度兩個方向上誤差丨〇%仍在本發明的範疇 之内。 最好提供第二與第一閘極層的異向蝕刻繼績直到達到介 電質為止。結果在等向蝕刻期間所形成的側壁會變得特別 均句致。換句話說,第一等向蝕刻也可以結束於下方閘 極層之内,而第二等向蝕刻則可從此處開始。在這種情況 下’要等到第二蝕刻期間才會到達介電質。 最後,提供第一閘極層係為就第二閘極層來選擇性等向 才只向底切。結果’得以保留閘極線的上方尺寸,因而可以 更簡單的方式連接接點。 底切最好藉助於等向電漿蝕刻步驟來執行。在這種情況 下,這意謂著傳統之具有感應的或其他耦合的乾式蝕刻室。 最好使用鹵化氫(hydrogen halide)當作等向蝕刻的蝕刻氣 體’尤其疋溴化氫(hydrogen bromide),因其對金屬具有良 好的選擇性而特別有幫助。 就所製造的T-閘極尺寸而言,提供較佳具體實施例之第 二閘極層的寬度係介於12〇與300 nm之間,而第一閘極層的 寬度則介於30與150 nm之間。因此,最好製造一通道長度 -7- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) A7 B7
1248649 五、發明説明(5 為30至1 50 nm的電晶體。 閘極介電質最好含有二氧化矽。 第二閘極層比第一閘極層具有一較高的導電率。妗果 可增加問極的整體導電率。第二閘極層最好包含金=鎢j 其可由鎮所組成。 本發明的一項發展提供就第二閘極層預定寬度到達第— 閘極層的邊緣下,提供引進源極/汲極植入及其擴散。在這 種情況下,較寬的下方閘極層形成一部份光罩,使得口 = 在下方閘極層到介電質的一定距離下,才會引進植入到曰曰 圓。隨後控制植入之散熱的方式使得雜質除了覆蓋間隔$ 寬度之外,也覆蓋第二與第一閘極層寬度間的差距,亦即 預定短通道長度的路徑。 根據本發明的MOSFET最好是DRAM或一邏輯電路的—部 份。 ° 圖式簡單說明 以下參考圖1至3說明本發明,圖中根據本發明顯示閉 極電晶體之製造之不同的方法階段。 較佳具體實施例之詳細說明 根據圖1,複數個一序列的閘極層沉積於以閘極氧化物2 (最好由二氧化矽製成)覆蓋的矽基板1上。因此而製造的間 極層堆疊實質上包含由多晶矽製成的一第一閘極層3以及覆 蓋的第二閘極層5。在極微小尺寸的情況下,第二閘極層5 可用來增進閘極的導電率,因此最好由金屬,尤其是鎢所 組成。 -8 -
裴 訂
線 本紙張尺度適用中國國家標準(CNS) Α4規格(210 χ 297公釐) 1248649
孔的階段中’而第-閘極層3則只有部份穿孔。在這種情況 第閘極層3在第二钱刻步驟中,完全穿孔到介電質2 ,說明如下。 ' 一根據圖2,在接下來等向蝕刻的步驟中,對基板等向供應 第#刻氣體A2。冑肖的意思是說等向程度高到蝕刻氣 體足以到達及底切下方閘極層3的側壁。 々 J必須就介電質2來選擇性執行。第二蝕刻就介電 質的選擇性越大,預防介電質的穿孔也就越可靠。 在第#刻的過程中,並不—定需要到達介電質;如果 f極結構的初始寬度,亦即上方閘極層5的寬度夠大的話, 樣在到達下方閘極層3之後,只有第二蝕刻露出介電 笛氧體A2的選擇方式最好使得第二㈣也可以就位於 ΙήΓΓ3上的第二閘極層5(如果合適的話,並且就介於 編中間層)來選擇性執行。在這種情況下,所製造的Τ. i閘極結構在$成的導電金屬上方部份上,·维持其於第一 姓刻之後所形成的較寬橫截面,同時只有下方第」、閉極層3 咸。結果,使得上方問極層5可以更簡單的方式來連 如果第二姓刻未就上方閘極層來 . 的丁刑心“ Ί鞭層來選擇,雖然可製造熟知 的T-i閘極結構,但在這種情況下,卻仍然可以達成同樣 減少的初始閘極長度。此外,如果二 , 足夠的厚度,為了確保閘極足夠 曰2積具有 罪地進仃接觸,在㈣刻之後,同樣保留該層足夠的材 -10-
1248649 五、發明説明( 料 最好使用齒化氫作為用於等向執 Τ- (ΗΒΓ)^ ^ ^ ^ t Τμ,Ι t 第-閘極層)的選擇性良好,尤其非常適合。 (作為 =及2t為了將成型時藉由㈣ a 同等向程度說明得更清楚,L7汰丄e 7如響的不 鄰接電容it㈣極層堆疊。5的ί鄰接比例來顯示 相反地,圖3卻只顯示一個單一製造的I型層堆疊、 ,其上已橫向覆蓋著間隔7。間隔可用來就引 極植入S/D橫向絕緣閘極通道。 氣 植入S/D係於間隔7之外,從介電質2植入到基板的區域8 。在隨後的熱處理期間,熱作用之溫度與持續期間的控制 方式使得離子輪廓6正好延伸於上方閘極層5的下方直到下 方閘極層3 ’亦即進人區域6a。假定原來閘極層堆疊的寬产 為200 nm,則在閘極每—側上之相當於底切的額外離子^ 散為50 nm便足以形成具有一通道長度1〇〇⑽的電曰曰日體。最 好從-閘極寬度12〇 nm進行到3〇〇 nm時,源極/沒極植入最 好互相進行到最好是3〇至丨5〇 nm(相當於理想的通道長度)。 然而’根據本發明,所製造的M〇SFET可以是任何理想、甚 至更短的通道長度β 利用根據本發明的方法,這種電晶體的製造可藉助於傳 統的微影方法。 本發明可製造自我對準的多層閘極,其中專門採用傳統 的製造安裝與製程步驟。因此本方法既簡單又符合成本效 -11 - 本紙張尺度適用中國國家標準(CNS) Αί^(210X 297公釐) 1248649 A7 B7 五、發明説明(9 ) 切之故, 益,而所製造之電晶體的閘極長度由於控制的 在尺寸上更是特別精確。 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)

Claims (1)

1248649ι 1 1 ; 第〇ll〇4389號專利申請案L—.…;一— Is 中文申請專利範圍替換本(92年12月)_______ 六、申請專利範圍 L 一種用於製造一金屬氧化物半導體場效電晶體 (MOSFET)的方法,該MOSFET具有一預定之極短通道長 度的一閘極通道,該方法具有以下步驟: -在一半導體基板(1)上製造一介電質(2), -將包含多晶矽之一第一閘極層(3)施加至該介電質 (2) 上, -於該第一閘極層上形成一中間層(4 ),該中間層 (4 )係用來作為擴散障壁, -施加包含一金屬之一第二閘極層(5), -遮罩該第二閘極層(5)的方式是使該第二閘極層(5) 的該寬度比該預定的通道長度還大, -異向姓刻該第二閘極層(5 )、該中間層(4 )與該第 一閘極層(3),以及 •按達成該第一閘極層(3)之一預定寬度的控制方式, 就δ玄介電質(2)、該中間層(4 ),及該第二閘極層選擇 性等向橫向底切在該第二閘極層(5)之下的該第一閘極層 (3) ;而該第一閘極層(3)的寬度小於該第二閘極層(5)的 寬度,且相應於該預定的通道長度。 2. 如申請專利範圍第1項之方法, 其特徵在於 藉由該第二閘極層(5)的該寬度及藉由在該第二問極層 (5)底下之該第一閘極層(3)的該橫向底切該持續期間來 控制該第一閘極層(3)的該寬度。 、’ 3. 如申請專利範圍第1或2項之方法, 1248649 A8
其特徵在於 ▲在藉助於一蝕刻劑(A2)的該濃度在該底切的期間控制 該第一閘極層(3)的寬度。 4·如申請專利範圍第1至2項之其令一項之方法, 其特徵在於 該第-閘極層(3)的該狀寬度等於該财的通道長度。 5·如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 該第二(5)與第一閘極層(3)的異向蝕刻繼續直到達到 該介電質(2)為止。 6·如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 X第閘極層(3)係為就該第二閘極層(5)來選擇性等 向橫向底切。 7. 如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 該底切藉助於一等向電漿蝕刻步驟來執行。 8. 如申請專利範圍第7項之方法, 其特徵在於 該等向姓刻的執行係藉助於化氬,尤其是漠化氣。 9. 如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 該第二閘極層(5)的該寬度介於120與300 nm之間。 10. 如申請專利範圍第1至2項之其中一項之方法, A B c D 1248649 ^、申清專利範圍 其特徵在於 該第一閘極層(3)的該寬度介於30與150 nm之間。 11·如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 該閘極介電質(2)包含二氧化矽。 12·如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 該第二閘極層(5)比該第一閘極層(3)具有一較高的導 電率。 13·如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 就該第二閘極層(5)的該預定寬度到達該第一閘極層 (3)的該邊緣下,引進源極/沒極植入s/d及該植入的擴散。 14·如申請專利範圍第1至2項之其中一項之方法, 其特徵在於 s亥第二閘極層(5)包含該金屬嫣。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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