TW402749B - Field effect transistor with self-aligned T-type gate - Google Patents

Abstract

A method for manufacturing a field effect transistor with self-aligned T-type gate is provided for self-aligned process. Utilizing the planarization process to form a conductor deposition layer which is composed of polysilicon, silicide compound, or other conductor layer on a polysilicon gate, or utilize the application of selective deposition to form a conductor layer on the top and sidewall of said polysilicon gate; a T-type gate conductor area is formed to reduce the parasitic capacitance between the transistor and source/drain. Moreover, an air spacer is formed at the extension area between the underlayer of the stack conductor layer and the said source/drain area in the T-type gate structure of the present invention. Thus it could reduce the parasitic capacitance between the transistor and source/drain and could apply to high-speed operation integrated circuit and high frequency integrated circuit.

Description

5. Description of the invention (1) The present invention relates to the use of extremely field-effect transistor elements, which can be used to reduce the parasitic capacitance of the transistor. With the advancement of semiconductor technology, the gate parasitic resistance and characteristics of the integrated body of the components. After the mainstream of deep sub-micron CMOS wireless communication technology, components will be able to meet the high parasitics of the gates of these components, which must be overcome. A self-manufacturing method with an air gap 'its process is new, simple and practical, and its parasitic resistance between the gate and source / drain electrodes and its progress' process technology-increasing to the depth of the sub-micron, and the size is also With the reduction, the parasitic capacitance of the transistor has also begun to transfer the components. The 9 pieces and circuits are expected to become in the next few years, because when the line width of the components is less than 0.25 micrometers, the operation is required, and its low cost. However, the problem of the side of the resistor and its parasitic capacitance is the current method to reduce the parasitic resistance, which mainly includes self-aligned metal silicide process. However, this method has its limitations and affects its application. When the process technology is further reduced to the deep sub-micron, when the self-aligned metal silicidation process is used to form a very thin line width conductive line, the sheet resistance of the conductive line will increase rapidly (called the narrow line width effect, narrow 1 ine -width effect). In addition, agglomeration effects due to heat can make integration of the process more difficult. In terms of ways to reduce parasitic capacitance, Togo et al. Disclosed in "A Gate-side Air-gap Structure (GAS) to Reduce the parasitic Capacitance in MOSFETs; 1 996 Symposium on VLSI Technology Digest of Technical Papers" Use several times to grow the spacer and selective system of different materials

Page 4 2000. 04.15. 004 V. Description of the invention (1) The present invention relates to the use of an extremely field effect transistor element, which can be used to reduce the parasitic capacitance of the transistor. With the advancement of semiconductor technology, the gate parasitic resistance and characteristics of the integrated body of the components. After the mainstream of deep sub-micron CMOS wireless communication technology, components will be able to meet the high parasitics of the gates of these components, which must be overcome. A self-manufacturing method with an air gap 'its process is new, simple and practical, and its parasitic resistance between the gate and source / drain electrodes and its progress' process technology-increasing to the depth of the sub-micron, and the size is also With the reduction, the parasitic capacitance of the transistor has also begun to transfer the components. The 9 pieces and circuits are expected to become in the next few years, because when the line width of the components is less than 0.25 micrometers, the operation is required, and its low cost. However, the problem of the side of the resistor and its parasitic capacitance is the current method to reduce the parasitic resistance, which mainly includes self-aligned metal silicide process. However, this method has its limitations and affects its application. When the process technology is further reduced to the deep sub-micron, when the self-aligned metal silicidation process is used to form a very thin line width conductive line, the sheet resistance of the conductive line will increase rapidly (called the narrow line width effect, narrow 1 ine -width effect). In addition, agglomeration effects due to heat can make integration of the process more difficult. In terms of ways to reduce parasitic capacitance, Togo et al. Disclosed in "A Gate-side Air-gap Structure (GAS) to Reduce the parasitic Capacitance in MOSFETs; 1 996 Symposium on VLSI Technology Digest of Technical Papers" Use several times to grow the spacer and selective system of different materials

Page 4 2000. 04.15. 004 1Q2749 5. Description of the invention (2) process to obtain an air lining. Because of the oxide layer (dielectric constant 4) or nitriding ^ used for air eight a, the constant is 1, which can reduce the parasitic capacitance more traditionally. However, T0g0 has a low dielectric constant 7), so it has a complicated manufacturing process (so the cost is high), and it needs to be used quite, so the effect of reducing parasitic capacitance is limited. Parasitic resistance. In addition, it can not effectively improve. In addition, the Republic of China patent No. 32 7241, T-shaped pole to reduce parasitic resistance, and then CVD == shape: the formation of air gaps to reduce the dagger layer. The use of micro-shirt The etching step defines the silicon nitride layer to form an opening, ... = ί " ... forms a polycrystalline silicon 'and uses a lithographic etching step to define a polycrystalline silicon gate with a width larger than the opening in the opening, so that both ends are covered. Part of this silicon nitride layer ". Therefore, it is necessary to use at least two photomasks to form a τ-type gate, which is not a self-aligned process and increases the cost of manufacturing. Moreover, consideration must be given to the design It is necessary to increase the width of the side of the T-gate. This will increase the parasitic capacitance and reduce the advantage of using air gaps. In view of this, the main purpose of the present invention is to provide a self-aligned T-type A method for manufacturing a gate field effect transistor. In addition to reducing the parasitic resistance between the gate and source / drain of the transistor, the field effect transistor can effectively solve the problem of the narrow line width effect described above. And reduce the parasitic capacitance between the gate and source / drain, and the process is simple, the number of photomasks is less than the above patent 'low cost, it is compatible with the traditional process, so it can be easily applied to a general production line.

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In order to achieve the above object, the present invention provides a method for manufacturing a polarized field effect transistor electrical element, 'Self-shaped gate V. Description of the invention (3) _ forming an air gap, which includes the following steps to further provide a gate side The semiconductor substrate is sequentially formed by a 1-second dielectric layer and a third dielectric layer; = :. Dielectric layer: can be selected from borophosphosilicate glass, phosphosilicate glass, borosilicate glass, and selenium :, and the electrical layer is selected. The first dielectric layer is a pad oxide layer 0S ::-or silicon. The above-mentioned dielectric layer is nitrogen, which defines the third, second, and first etching.

D to expose the semiconductor substrate. β, forming an opening, forming a gate oxide layer on the opening ... 1 spread. A conductive layer is deposited on and above the openings. And the third dielectric layer uses, for example, CMP in order to planarize the first twilight-conducting layer existing only in the openings, and it is used as a conductive layer: the above-mentioned first conductive layer is, for example, a complex B ... -The electrode is used as an etchant such as hydrofluoric acid or BOE, a dielectric layer to expose the upper end portion of the gate electrode. μ; A first ion implantation was performed to form the first sides. The y-doped region forms a stacked conductive layer on the gate, and forms a gate structure with the gate and the gate; on the upper layer, the material is selected from polycrystalline silicon, silicon silicide, One of the titanium metals doped with a polycrystalline silicon broadcast layer. Japan 7 Tungsten, Cobalt, and

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A first impurity region is formed to serve as a source / drain ion region for the second ion implantation. From the selective etching, the above-mentioned second dielectric layer is removed. Above, an insulating layer is formed on the semiconductor substrate, and an air gap exists between the above-mentioned τ-type closed-pole structure under the stacked conductive layer and the above-mentioned doped region. There are two methods for forming the above-mentioned stacked conductive layers:-firstly deposit a conductive layer on the gate and the dielectric layer to anisotropically etch the conductive layer to form a conductive spacer on the upper side wall as the above The conductive layer is stacked to form a T-type interpolar structure. The silver engraving of the conductive layer is made of halogen, emulsion, halogen compound, hydrochloric acid, bromine-containing compound, or a mixture for anisotropic dry type. Etching. …, Tian Er used the selective deposition method for the above-mentioned gates to form the above-mentioned conductive layer on the above-mentioned gates and the dielectric layers, thereby the above-mentioned gate-type gate structure. According to the manufacturing method of the self-aligned T-gate field effect transistor according to the present invention, the manufacturing process is simple and can be integrated with the traditional manufacturing process. Since the T-gate MOS transistor manufactured by the present invention includes air gaps on both sides of the gate, the parasitic capacitance of the gate can be reduced. According to the present invention, the T-gate field-effect transistor is fabricated. Since a τ-type conductive gate is formed, the equivalent width of the gate becomes larger, so the sheet resistance value of the gate resistance can be effectively reduced. Brief description of t schema:

C: \ Program Files \ Patent \ 0522-3940-E.ptd Page 7 5 10W8 Understand the description of the invention (5), so that the above-mentioned objects, features, and advantages of the present invention can be more obvious. The preferred implementation drawings are detailed below as follows: σ / 'The following example is explained. Β Figure 1K is a cross-sectional view showing the flow chart of the first implementation of the manufacturing method according to the present invention; Figure 2A 2C Shows another option and choice of some steps of the first embodiment; and the 3A to 3D diagrams show the description of the first embodiment of the present invention: 12 semiconductor substrates; 2 to the first-dielectric layer (kraft beer layer); 3 Won I a ratified silicon layer); 4 to the third dielectric layer (TE0s); bow two openings; gate card 妯, said. 7 ~ the first conductive layer (open pole); 8 ~ the first Doped region (source / drain region) '9 ~ stacked conductive layer; 10 ~ second doped region (deep source / drain region); 1 upper oxide layer ... ~ air gap; 1S ~ stacked conductive layer. A Embodiment 1: Figures 1A to 1G are flow charts of the manufacturing method according to the present invention. The following is a part of a flowchart illustrating an example of the manufacturing steps of the present invention with drawings. The gate provides a semiconductor substrate 1 on which a first dielectric layer 24 is formed, as shown in FIG. 1A. The above substrate 1 is a general Shi Xi wafer, a second dielectric layer 3, and The third dielectric layer is the first dielectric layer 2 with a thickness of 50 ~ 200 angstroms (pad 0Xide); the second dielectric layer 3 is a silicon nitride layer formed using low (LPCVD) ; On _ 1. Show one; 丨 the electrical layer 4 can be borophosphosilicate

402749

The glass and phosphorous silicon underfilling example is selected by using one of the meteorological step 2, butterfly glass, and TE0S, and the TE0S obtained by the deposition method (CVD).

Opening 5 :: Lu Yi :: Describing the T-th body U-dielectric layer 'to form a dry body substrate 1' The results are shown in Figure 1B. ^ To avoid the short channel effect (^.), The substrate 1 that is routed out in 5 is used for necessary channel ion implantation. Step 3 The substrate of the gate oxide layer 6 in the opening 5 is formed on the substrate 1 by thermal oxidation as shown in FIG. 1c. Step 4: A first conductive layer 7 is deposited in the opening 5 and above the third dielectric layer 4, as shown in FIG. 1D. In this example, the first conductive layer 7 is polycrystalline silicon, and its thickness must be greater than half of the width of the opening 5 to ensure that the above-mentioned filling step 5 can be planarized using chemical mechanical polishing (CMP). The first conductive layer 7 allows the first conductive layer to exist only in the opening 5 as the gate electrode 7 ′. The result is shown in FIG. 1E. … Step 6 Use, for example, hydrofluoric acid or BOE to selectively etch the third dielectric layer 4 (TE0S) to remove the third dielectric layer $ and expose

C: \ Program Files \ Patent \ 0522_3940-E · ptd Page 9, 5, V. Description of Invention (7) '----- --- Part of the upper end of gate 7, as shown in Figure 1F. Step 7 Ion implantation is performed to form a first doped region 8 on the two of the above gates 7: as a source / drain region extension of the MOS transistor, as shown in (). In step 8, a second conductive layer is deposited in advance. The thickness of the gate electrode 7 and the second dielectric layer 3 is between 5000 and 2000 angstroms, and can be adjusted according to actual needs. In this embodiment, the thickness is 1 500. A. The second conductive layer D is anisotropic. Silver is engraved to form a stacked conductive layer spacer 9 on the side wall of the gate electrode 7 to form a T-gate with the gate electrode 7 The structure 'is shown in Figure 丨 H. The material of the second conductive layer is selected from one of polycrystalline silicon, silicided metal, doped polycrystalline silicon, tungsten, cobalt, and titanium, or a compound After the silicon is etched, a silicon silicide formed by a self-calibrating salicide process and a material with a good interface with the gate 3 are preferred. The conductive layer is etched with anisotropic dry etching using a halogen gas, a halide compound, hydrochloric acid, one of the bromine-containing compounds, or a mixture thereof, such as a mixed gas of Cl2 / HBr / SF6. Ions are implanted to form a second doped region 10 on both sides of the T-type gate, which serves as the deep source / drain region of the MOS transistor. Fabrication of gate-type field-effect transistor. The following steps 10 ~ 11 can be continued to form a T-gate MOSFET with air gap.

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V. Description of the invention (8) Step 10 is removed by selective etching to expose the T-type gate, and "= the second dielectric layer 3 (nitride stone layer), and there will be no nitride stone layer". Step 11 below the stacked conductive layer spacer 9 is shown in FIG. 1J. The layer thickness is between 40 ° " Angstrom oxide cap, in this embodiment, Γ oxidation; The stacked conductive sound structure of the T-type gate structure is 5500 angstroms. There is an air gap between the above. S and the source / drain region extension 8 in this embodiment, in (step eight) (can be After the first money and u are removed by wet coin engraving, (Figure 2A; the original step 10) u exposes the T-gate / drain region 10 (Figure 2B; the original 'ion π implanting') is formed. The deep source deposition method forms an oxide layer. After the above half, it is completely covered with a chemical vapor phase electrode (Part 2 (: Figure). Too: on the bulk substrate 1 '@ 将 Τ 型 开关 迹 2C shown ( The second part of the process that can be changed in this embodiment is as in the second embodiment: as in the method of the first embodiment above, seven, as shown in Figure 1G. From step to completion The step 8 is described as follows: the gate 7 is selectively attracted to the gate 7, and the layer 3 is formed on the gate 7 and the second dielectric layer 3 to form a stacked conductive structure to form a T-type electrode structure, as shown in FIG. The above 'and the above question 7

402749 V. Description of the invention (9) The material of the on-demand layer that is between Angstrom and Angstrom is selected from the compound crystal; ::: ί "] 50 ° Angstrom. One of the above conductive inscriptions and titanium It is better to use = metal, doped compound spar, crane, and quality. And the interface with the closed electrode 3 is in good condition. Step 9 Use Kun ion for ion preparation. = Pole = 2 as the depth of the M0s transistor. The τ-type idler M0SFET of the source field effect transistor's core gap. Steps ten to eleven, so as to form an air-to-air step, the wet exposed method is used to remove the second exposed T-type closed pole, and the T-type idler (~ 化 ㈣) There will be two rat fossil layers, and the result is shown in Figure 3C. Below 3, there will be no eleven steps to form a layer with a thickness of 4000 ~ 7 by chemical vapor deposition. 11 In the above guide, beauty; ^ Emulsified Yun, right Taiji completely cover the τ-type gate 1 In this example of bismuth, the thickness of the oxide layer is 5500 Angstroms. There is an air gap below the stacked conductive layer i 3 and between the above source / sink &extension; as shown in Figure 3D., ° ° The second embodiment is the same as the first embodiment As described in the example, the second dielectric layer can also be used afterwards, such as Shishen ion source / drain region 10. Material bismuth is implanted to form a deep C: \ Program Files \ Patent \ 0522-3940-E .ptd page 12 402749 V. Description of the invention (10) _ The traditional T-gate and source / drain are interposed, and the present invention is used to make dielectric layers and gaps, such as layers, from the chamber to the gas. The electric constant is smaller than oxygen (about 4 left and right). Therefore, the present invention makes two oxygen: parasitic lightning between the dielectric constants of the dagger layer. The performance of the gate and source / drain The performance is superior. According to the summary of the return speed transmission, according to the electrical component of the present invention, the automatic alignment system is used, and the cost is saved. In addition, the effective width becomes larger, so the air gap can be effectively used. The formation of the T-gate field-effect transistor can reduce the complexity of the T-shaped conductive gate formed in the process, so as to reduce the parasitic resistance between the gate and the electrode / source / Parasitic capacitance value between the drain electrodes Although the present invention has been disclosed above in two preferred embodiments, it is not limited The present invention, any Skilled persons, without departing from the spirit and scope of the present invention, it can still make cover modifications and variations, so as to define the attachment of the scope of the invention when view patent, whichever range.

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Claims (1)

6. The scope of applying for patents includes steps; a method for manufacturing self-aligned T-gate field-effect transistors, including the first definition, the third, and the third to expose the semiconductor substrate to form a gate oxidation sound. 1. On the substrate in the above-mentioned opening; deposit a first conductive mine at [_, +, and 3] ▼ An electrical layer is placed in the above-mentioned opening, and the above-mentioned third dielectric layer is raised ::: a conductive substrate, sequentially on it Forming a -th dielectric layer,-, an 'electric layer, and a third dielectric layer; the first dielectric layer is formed on top of the above: said first conductive layer' so that the above-mentioned first conductive layer exists only on In the upper opening, it serves as a gate; Ϊ Ϊ ί Three dielectric layers, exposing the upper end of the gate; Both sides are implanted with human ions to form a first doped region in the gate. The conductive layer is stacked on the gate and the second dielectric layer to form a T-type gate structure with the gate. The first ion implantation is performed. . The 掺杂 & doped region is used as a source / ^ method for forming a stack of conductive layers on each side as described in item 丨 of the scope of the patent application, as a first deposition-the second / < gate and the above dielectric layer On top of that, the cups are placed on the above y layer, and then anisotropic etching is used to define the etching to obtain the above-mentioned stacked conductive layer. 3. The Qin Zhi stack as described in item i of the scope of patent application The formation of the conductive layer is based on the use of selective Shen Zhongji / βπ C: \ ProgramFiles \ Patent \ 0522-3940-E_ptd page 14 402749 6. Application for a patent to form the stacked conductive layer on the gate and II. 4. The method of k-knowledge as described in item 2 and item 3 of the scope of the patent application, wherein the material of the above-mentioned conductive layer is selected from the group consisting of polycrystalline dream, dream metal, doped polycrystalline silicon, and tungsten Of cobalt, cobalt, and titanium. __ ^ 5. The method of manufacturing as described in item 2 of the scope of patent application 丨, wherein the first V electrical layer is selected from polycrystalline spar, and is self-calibrated after etching. Shi Xihua metal program to convert it to silicified metal. —_ 6. · such as力 The force described in item 2 of the patent scope: ¾¾ method, where the above = one, the etching of the electrical layer is performed using a halogen gas, a halogen compound, or a salt rhyme. Or an anisotropic dry method 7 The first scope of the patent is that the first -dielectric layer is a pad oxide layer, the above-mentioned "second installation method, where" and the third dielectric layer may be a boron-phosphorus-silicon electrical layer as a silicon nitride layer, one of glass and TEOS.选择, phosphosilicate glass, borosilicate glass 8. If the scope of the patent application is the i-th gate oxide layer in the above opening = method, the substrate in the above opening is ion implanted on the bottom 9. If applied The first conductive layer described in the patent scope item 1 is a polycrystalline silicon layer. ~ ^: 10. The method for planarizing the first conductive layer as described in the first scope of the patent application system is a method of making cymbals, wherein 11. Such as The method of applying patents for the mechanical polishing method of the item No.! In addition to the method of the third dielectric layer, the method is a method, in which the above-mentioned method is adapted by using fluoric acid or B0E. I make methods, where, on C: \ Program Files \ Patent \ 0522-3940-E.ptd page 15 6. Scope of patent application The third dielectric layer is selectively etched. 12. According to the ^ -type gate and source / drain regions described in item 1 of the scope of the patent application, the more appropriate it is, J includes the following steps in forming the above-mentioned person to remove the above-mentioned brother: Two dielectric layers; and a stack of conductive layers forming an insulating layer on the semiconductor-based gate structure described above, which exists in the aforementioned τ air gap. Below the electrical layer and between the above-doped region, there is a hollow-shaped system described in the scope of patent application No. 1 on each side. A stacked conductive layer is formed on the above gate and the above-mentioned second dielectric: its in-gate structure After that, the above-mentioned second intermediary can be used to form τ to perform the first-blown impurity; Huaigu θ is removed first, i 仃 _ human ion implanted to form the source / drain region, and then 2 on the semiconductor substrate So that there is an air gap between the above-mentioned insulating layer and the above-mentioned first doped region. 7 The stacking guide C: \ Program Files \ Patent \ 0522-3940-E.ptd page 16