KR100402355B1 - 반도체 소자의 쇼트 채널 트랜지스터 제조 방법 - Google Patents
반도체 소자의 쇼트 채널 트랜지스터 제조 방법 Download PDFInfo
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- KR100402355B1 KR100402355B1 KR10-2001-0081784A KR20010081784A KR100402355B1 KR 100402355 B1 KR100402355 B1 KR 100402355B1 KR 20010081784 A KR20010081784 A KR 20010081784A KR 100402355 B1 KR100402355 B1 KR 100402355B1
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- forming
- film
- spacer
- nitride film
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 45
- 150000004767 nitrides Chemical class 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000007943 implant Substances 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000002347 injection Methods 0.000 claims abstract description 3
- 239000007924 injection Substances 0.000 claims abstract description 3
- 239000000126 substance Substances 0.000 claims abstract description 3
- 230000000694 effects Effects 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (12)
- 반도체 기판 위에 제 1 산화막을 형성하고 제 1 질화막, 제 2 산화막 및 제 2 질화막을 차례로 증착한 후 제 1 마스크를 이용하여 패턴을 형성하는 단계와,상기 결과물 상에서 건식식각으로 제 2a 질화막과 제 2a 산화막을 형성한 다음 제 1 스페이서 막을 증착한 후 전면식각으로 제 1 스페이서를 형성하는 단계와,상기 제 1 스페이서의 형성과 동시에 상기 제 1a 질화막을 형성한 후에 습식식각으로 상기 제 1a 산화막을 형성하는 단계와,상기 결과물 상에서 노출된 상기 반도체 기판 위에 게이트 절연막을 형성하고 게이트 전도체를 증착한 후 상기 제 2a 질화막을 화학기계적연마(CMP) 스톱 레이어(Stop Layer)로 이용하여 CMP 방법으로 게이트 전도체를 형성하는 단계와,상기 제 2a 질화막, 상기 제 1 스페이서, 제 2a 산화막, 제 1a 질화막을 습식식각 방법을 이용하여 제거하는 단계와,상기 결과물 상에서 주입 방법으로 LDD(Low Doped Drain) 임플런트를 만든 후에 제 2 스페이서 막을 증착한 후 전면식각 방법으로 제 2 스페이서를 형성하는 단계와,상기 결과물 상에서 주입 방법으로 소오스 및 드레인을 형성한 다음 습식식각으로 상기 제 1a 산화막을 제거하는 단계와,상기 게이트 전도체와 소오스 및 드레인 영역에 살리사이드를 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 제 1 스페이서 막은 산화막을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 제 1 스페이서 막은 질화막을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 제 1 스페이서 막의 폭을 조절하여 채널의 크기를 조절하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 제 2 질화막은 산화막을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 제 2 스페이서 막은 산화막을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 제 2 스페이서 막은 질화막을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 게이트 전도체는 폴리실리콘(Poly-Silicon)을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 게이트 전도체는 메탈(Metal)을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 제 2a 질화막은 산화막을 이용하는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 LDD 임플런트 시에 채널에서 떨어지게 형성한 후 후속 열처리에 의해서 채널에 오버랩(Overap)되게 하여 쇼트 채널 효과를 줄이는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
- 제 1 항에 있어서,상기 LDD 임플런트 시에 채널에서 떨어지게 형성한 후 후속 열처리에 의해서 채널에 오버랩(Overap)되게 하여 DIBL(Drain Induced Barrier Lowering)를 줄이는 것을 특징으로 하는 반도체 소자의 쇼트 채널 트랜지스터 제조방법.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0081784A KR100402355B1 (ko) | 2001-12-20 | 2001-12-20 | 반도체 소자의 쇼트 채널 트랜지스터 제조 방법 |
TW091136446A TWI231547B (en) | 2001-12-20 | 2002-12-17 | Short channel transistor fabrication method for semiconductor device |
US10/323,328 US6762105B2 (en) | 2001-12-20 | 2002-12-18 | Short channel transistor fabrication method for semiconductor device |
JP2002370141A JP3813577B2 (ja) | 2001-12-20 | 2002-12-20 | 半導体素子のショートチャンネルトランジスタの製造方法 |
CNB021400156A CN1249796C (zh) | 2001-12-20 | 2002-12-20 | 半导体元件的短沟道晶体管的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0081784A KR100402355B1 (ko) | 2001-12-20 | 2001-12-20 | 반도체 소자의 쇼트 채널 트랜지스터 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030050993A KR20030050993A (ko) | 2003-06-25 |
KR100402355B1 true KR100402355B1 (ko) | 2003-10-22 |
Family
ID=36121979
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR10-2001-0081784A KR100402355B1 (ko) | 2001-12-20 | 2001-12-20 | 반도체 소자의 쇼트 채널 트랜지스터 제조 방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6762105B2 (ko) |
JP (1) | JP3813577B2 (ko) |
KR (1) | KR100402355B1 (ko) |
CN (1) | CN1249796C (ko) |
TW (1) | TWI231547B (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100521369B1 (ko) * | 2002-12-18 | 2005-10-12 | 삼성전자주식회사 | 고속도 및 저전력 소모 반도체 소자 및 그 제조 방법 |
CN102263030B (zh) * | 2010-05-25 | 2013-04-10 | 北大方正集团有限公司 | 一种沟槽型功率器件的制备方法 |
US8901665B2 (en) * | 2011-12-22 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure for semiconductor device |
KR102328279B1 (ko) * | 2017-08-11 | 2021-11-17 | 삼성전자주식회사 | 반도체 소자 |
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US4636834A (en) * | 1983-12-12 | 1987-01-13 | International Business Machines Corporation | Submicron FET structure and method of making |
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US5571738A (en) | 1992-09-21 | 1996-11-05 | Advanced Micro Devices, Inc. | Method of making poly LDD self-aligned channel transistors |
FR2706354B1 (fr) | 1993-06-14 | 1995-09-01 | Aerospatiale | Procédé de réalisation d'objets creux en matériau composite par bobinage-dépose au contact sur un mandrin expansible et objets ainsi obtenus. |
US5545579A (en) * | 1995-04-04 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains |
US5965919A (en) * | 1995-10-19 | 1999-10-12 | Samsung Electronics Co., Ltd. | Semiconductor device and a method of fabricating the same |
US6417550B1 (en) * | 1996-08-30 | 2002-07-09 | Altera Corporation | High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage |
US5766998A (en) * | 1996-12-27 | 1998-06-16 | Vanguard International Semiconductor Corporation | Method for fabricating narrow channel field effect transistors having titanium shallow junctions |
US6025635A (en) * | 1997-07-09 | 2000-02-15 | Advanced Micro Devices, Inc. | Short channel transistor having resistive gate extensions |
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US6087208A (en) * | 1998-03-31 | 2000-07-11 | Advanced Micro Devices, Inc. | Method for increasing gate capacitance by using both high and low dielectric gate material |
US5998288A (en) * | 1998-04-17 | 1999-12-07 | Advanced Micro Devices, Inc. | Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate |
US6169006B1 (en) * | 1998-07-29 | 2001-01-02 | Advanced Micro Devices, Inc. | Semiconductor device having grown oxide spacers and method of manufacture thereof |
US6214677B1 (en) * | 1999-10-22 | 2001-04-10 | United Microelectronics Corp. | Method of fabricating self-aligned ultra short channel |
US6204133B1 (en) * | 2000-06-02 | 2001-03-20 | Advanced Micro Devices, Inc. | Self-aligned extension junction for reduced gate channel |
US6348385B1 (en) * | 2000-11-30 | 2002-02-19 | Chartered Semiconductor Manufacturing Ltd. | Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant |
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2001
- 2001-12-20 KR KR10-2001-0081784A patent/KR100402355B1/ko not_active IP Right Cessation
-
2002
- 2002-12-17 TW TW091136446A patent/TWI231547B/zh not_active IP Right Cessation
- 2002-12-18 US US10/323,328 patent/US6762105B2/en not_active Expired - Lifetime
- 2002-12-20 CN CNB021400156A patent/CN1249796C/zh not_active Expired - Fee Related
- 2002-12-20 JP JP2002370141A patent/JP3813577B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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KR20030050993A (ko) | 2003-06-25 |
CN1438683A (zh) | 2003-08-27 |
TWI231547B (en) | 2005-04-21 |
US20030119320A1 (en) | 2003-06-26 |
JP3813577B2 (ja) | 2006-08-23 |
JP2003209249A (ja) | 2003-07-25 |
US6762105B2 (en) | 2004-07-13 |
TW200411778A (en) | 2004-07-01 |
CN1249796C (zh) | 2006-04-05 |
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