TWI248197B - Semiconductor constructions, and methods of forming semiconductor constructions - Google Patents

Semiconductor constructions, and methods of forming semiconductor constructions Download PDF

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Publication number
TWI248197B
TWI248197B TW093133695A TW93133695A TWI248197B TW I248197 B TWI248197 B TW I248197B TW 093133695 A TW093133695 A TW 093133695A TW 93133695 A TW93133695 A TW 93133695A TW I248197 B TWI248197 B TW I248197B
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Taiwan
Prior art keywords
semiconductor material
semiconductor
pillars
dielectric
regions
Prior art date
Application number
TW093133695A
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English (en)
Other versions
TW200608558A (en
Inventor
Randal W Chance
Gordon Haller
Sanh D Tang
Steven Cummings
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Micron Technology Inc
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Publication of TWI248197B publication Critical patent/TWI248197B/zh
Publication of TW200608558A publication Critical patent/TW200608558A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1248197 導體材料之多個第一 第一介電材料在其中 形成多個介電材料列 區域而彼此分隔；該等溝槽具有一 ，在該等溝槽β的該帛—介電材料 12. 13. 14. 15. 丰半導體基板之上形成一第二半導體材料，該第二 ¥體材料延伸在該等第—介電材料狀上及也延伸跨 越該等第—介電材料列之間的該等第-區域之上； 形成多個開孔’該等開孔延伸通過該第二半導體材料 且到達該第一介電材料； 以-第二介電材料填滿該等開孔，以延伸該等介電材 列,：度至該第二半導體材料的一上表面；及 °亥等弟一及第二半導體材料被圖案化成為複數個支 柱’該等個別的支柱包括在該第一半導體材料之一片段 的該第—半導體材料之—片段’該等支柱沿著該等 I伸至y某些支柱列利用包括該等介電材料列中之 或夕歹·!之夕個第二區域而彼此分隔。 :請求項U的方法，其中該等第-及第二介電材料是組 成上彼此相同。 如請求項11的方法 成上彼此不同。 如請求項11的方法 晶矽組成，及該第 組成。 如請求項11的方法 本上由單晶石夕組成 96970-970313.doc 其中該等第一及第二介電材料是組 ’其中該第一半導體材料基本上由單 二半導體材料基本上由多晶或非晶矽 其中該等第一及第二半導體材料基 1248197 ，其中該第二半導體材料是從第一半 其中該第一介電材料包括二氧化矽。 ’其中該第一介電材料基本上由二氧 ’其中該第一介電材料由二氧化矽組 ’其中該等第一及第二介電材料包括 ’其中該等第一及第二介電材料基本 ’其中邊等第一及第二介電材料由二 16·如請求項15的方法 導體材料磊晶成長 17 ·如請求項11的方法 18·如請求項11的方法 化石夕組成。 19·如請求項11的方法 成。 2〇·如請求項11的方法 —氧化秒。 21 ·如請求項11的方法 上由二氧化矽組成 22·如請求項11的方法 氧化矽組成。 23.如請求項π的方法，其中該圖案化包括： 在該第二半導體材料上形成一經圖案化硬式遮罩丨及 從該經圖案化硬式遮罩經該第二半導體材料轉印一圖 案至該第一半導體材料。 24·如請求項23的方法，其中該經圖案化硬式遮罩包括氮化 秒。 25·如請求項23的方法，其中該經圖案化硬式遮罩基本上由 -氣化秒組成。 26·如請求項23的方法，其中該經圖案化硬式遮罩由二氮化 梦組成。 27. —種形成一半導體結構的方法，該方法包括： 96970-970313.doc 1248197 提供-半導體基板，該基板包括延伸在一第一半導體 材料内之複數個溝槽’該第一半導體材料包括在一第一 高度層級的—最上表面，㈣溝槽利用包括該第-半導 體材料的多個第一區域而彼此分隔； 以介電材料填滿該等溝槽； 減低該等溝槽内該介電材料的一層級，以在該等溝槽 :形f該等介電材料線，該等介電材料線具有在一低於 第一高度層級的第二高度層級上的最上表面； 減低該介電材料的層級後，在該半導體基板上形成一 第二半導體材料’該第二半導體材料延伸在該等介電材 料線上及也延伸跨越該等第一區域；及 該等第-及第二半導體材料被圖案化成為在該等第一 區域内的複數個支柱’該等個別的支柱包括在該第 ，體材料之-片段之上的該第二半導體材料之一片段， 該等支柱具有在一位在該第一高度層級 層級的最上表面。 的弟一间度 认如請求項27的方法，其中該介電材料是—第 料，及在圖宰化号τ笠筮 虹咕 电材 在Ώ案化㈣弟—及第二材料成為 刖，進一步包括·· 〜 形成多個開孔，該等開孔延伸通過該第二半導 且到達該第一介電材料丨及 ; 以一第二介電材料填滿該等開孔。 請求項糊方法，進—步包括，在圖案化該等第_及 -材枓成為該等支柱期間，圖案化包括該第二介電材 96970-970313.d( 1248197 料及。亥第一半導體材 柱之間，該等等線延伸在該等支 等區#_ 第二半導體材㈣多個區段，該 3〇 , ^ ^ ，丨電材枓的多個區域而彼此分隔。 30.如睛求項29的方法，進—步包括： 刀^ 在，等支柱與該等線之間形成閉極線材料； ;:支柱内形成多個第—源極/沒極區域；及 個Ϊ -I:/内的該第二半導體材料的該等區段内形成多 個弟一源極/汲極區 極線被閘控連接到^ 〉及極區域經該閑 h亥等弟二源極/汲極區域。 3 1 ·如δ青求項27的方、、么 jr , '，/、中該等支柱具有在約第二高度層 級的基底。 门沒屬 3 2 ·如清求項2 7的方法 3 3 ·如清求項2 7的方法 組成。 34. 35. 如請求項2 7的方法 如請求項27的方法 晶石夕組成，及該第 組成。 其中該介電材料包括二氧化矽。 其中該介電材料基本上由二氧化矽 其中έ亥介電材料由二氧化石夕組成。 ’其中該第一半導體材料基本上由單 —半導體材料基本上由多晶或非晶石夕 其中該等第一及第二半導體材料基 其中該第二半導體材料是從第一半 3 6 ·如請求項2 7的方法， 本上由單晶矽組成。 37.如請求項36的方法， 導體材料磊晶成長。 38_種形成半導體結構的方法，該方法包括： 半 提供-半導體基板，該基板包括延伸在一單晶第 96970-970313.doc 1248197 導體材料内之複數個溝槽的隔離區域，該等隔離區域利 用包括該第一半導體材料的多個第-區域而彼此分隔； 從該第一半導體材料蠢晶成長一第二半導體材料；及 圖案化該第二半導體材料成為在該等第一區域的複數 個支柱。 其中該等第一及第二半導體材料包 39·如請求項38的方法 括矽。 其中該等第一及第二半導體材料基 4〇·如請求項38的方法 本上由矽組成。 41·如=求項38的方法，其中該等溝槽的隔離區域具有-位 於-第-高度層級之最上表面，其中該第一半導體材料 具有-位於一第二高度層級之最上表面，及其中在該第 -半導體材料磊晶成長起始時該第一高度層級在第二高 度層級或之上。 如明求項38的方法’其中該等溝槽的隔離區域具有一位 於-弟-鬲度層級之最上表面，其中該第一半導體材料 具有一位於一第二高度層級之最上表面，及其中在該第 :半導體材料蟲晶成長起始時該第—高度層級在在第二 高度層級之下。 43. 如請求項38的方法’其中用來圖案化該第二半導體材料 之該圖案化也延伸至該第—半導體材料，以致該等支柱 包括在該第一半導體材料的多個片段上的該第二半導體 材料的多個片段。 44. 如請求項43的方法，其中該圖案化包括·· 96970-970313.doc 1248197 在該第二半導體材料上形成一經圖案化硬式遮罩；及 從該經圖案化硬式遮罩經該第二半導體材料轉印一圖 案至該第一半導體材料。 45. 如請求項44的方法，其中該經圖案化硬式遮罩包括氮化 石夕。 46. 如請求項38的方法，其中用來圖案化第二半導體材料圖 案之该圖案化不延伸至該第一半導體材料。 47·如請求項46的方法，其中該圖案化包括·· 在該第二半導體材料上形成一經圖案化硬式遮罩；及 從該經圖案化硬式遮罩轉印一圖案至該第二半導體材 料。 月求員47的方法，其中該經圖案化硬式遮罩包括氮^ 秒。 49· 一種半導體結構，包括： 一半導體基板，包括一單晶半導體材料； 複數個隔離區域’位於該半導體材料之内且沿著一定 義的縱方向延伸，該等隔離區域利用該軍晶半導體材料 的縱向延伸長條而彼此分隔； 複數個線’其實際上垂直於該等隔離區域延伸；該等 該等隔離區域上的多個介電區域及在該等：離 E域之間的多個半導體區段； 之：ΓΓ晶半導體材料延伸向上之多個支柱所組成 ㈣狀行係沿著該定義的縱方h及 之列係沿著實際上垂直於該定義的縱方向 96970-970313.doc 1248197 平方向’㈣列的該等行係位於該等隔離區域之間且^ 著該單晶半導體材料的料縱向延伸長條，該等支柱= 括從該等縱向延伸長條延伸向上的該單晶半導體材料的 台面； 一第一組源極/汲極區域 等； 其位於該等支柱的上部區域 其位於該等線的該等區 一弟一組該等源極/汲極區域 段内； 與弟二組源極/汲 組该·#通道區域，其位於該等第一 極區域之間；及 複數個該等閘極線列，其沿著定義的水平方向延伸； 該等閘極線列沿著該支柱陣列之該等列延伸；該等問極 線列、該等通道區域及該等第—與第二組源極/汲極區域 形成複數個電晶體裝置；個別該等電晶體裝置包括該第 一組源極/汲極區域中的一第一源極/汲極區域、該第二組 源極/及極區域中的一第二源極/汲極區域、從該第一源極 /汲極區域延伸到第二源極/汲極區域的一通道區域、及在 該問極線列之内且緊接的該通道區域的一閘極。 50. 51. 如明求項49的結構，其中該等支柱基本上由單晶半導體 材料的台面組成。 如明求項49的結構，其中該單晶半導體材料是一第一半 導體材料，及其中至少某些個別的該等支柱包括在該單 晶半導體材料之該台面上的該第二半導體材料之一片 段0 96970-970313.doc 1248197 52. 53. 54. 55. 56. 57. 58. 如請求項5 1的結構，其中該等半導體區段屬於該第二半 導體材料。 如請求項5 1的結構，其中該第二半導體材料是一單晶半 導體材料。 如請求項51的結構，其中該第二半導體材料是一多晶或 非晶半導體材料。 如請求項49的結構，其中水平上鄰近的該等支柱是相斜 彼此縱向地交錯。 如請求項49的結構，其中水平上鄰近的該等支柱是實際 上相對彼此非縱向地交錯。 如請求項49的結構，進一步包括： 一電容器，其電連接一電晶體裝置的兮 ^ i · 妁4苐二源極/汲極 一位元線， 區域。 一源極/汲極 其電連接該電晶體裝置的該第 一種電子裝置，包括如請求項57的結構。 96970-970313.doc
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