TW201630159A - 直立式互補式金氧半場效電晶體（ｃｍｏｓ）結構和方法 - Google Patents

直立式互補式金氧半場效電晶體（ｃｍｏｓ）結構和方法 Download PDF

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TW201630159A
TW201630159A TW104138324A TW104138324A TW201630159A TW 201630159 A TW201630159 A TW 201630159A TW 104138324 A TW104138324 A TW 104138324A TW 104138324 A TW104138324 A TW 104138324A TW 201630159 A TW201630159 A TW 201630159A
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gate
cylinder
upper portion
field effect
effect transistor
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TW104138324A
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TWI584449B (zh
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理查肯尼斯奧克蘭
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台灣積體電路製造股份有限公司
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Abstract

本發明揭露一種堆疊的互補式電晶體。使用選擇性沉積技術來形成一個直立柱體，下部包含一半導體的類型(例如鍺)，上部包含另一種類型的半導體(例如砷化銦)。垂直柱體下部提供一類型電晶體的通道區，上部提供另一類型電晶體的通道區。這提供一種佔據最小積體電路表面積的互補對。這種互補式電晶體可以使用於各種電路圖。以上敘述為互補式電晶體，下方電晶體為p型電晶體，上方電晶體為n型電晶體。

Description

直立式互補式金氧半場效電晶體 (CMOS)結構和方法
本發明主要和半導體裝置結構相關，在特定的實施例中，提供了直立式互補式電晶體和堆疊結構的方法。
為了在積體電路上放進更多的裝置，這在發明積體電路中的半導體製造上已經成為一重要目標。更高的電路密度可以製造更高效能的裝置並大幅降低基礎電晶體的費用。電路元件的傳統配置是水平分布於半導體基板的表面。這提供了製造上的簡易度和降低複雜度。然而，現今半導體設計工程師正在水平式裝置的眾多限制上掙扎。
最大的挑戰是光學微影的極限。我們藉由光學微影中，一層稱為光阻的感光材料塗覆在裝置上，然後光阻根據特定分層設計的樣式曝露在一光學圖案中。然而，積體電路中的組成已經小到尺寸和光阻曝光的光波長為同一級。儘管在各種合理的期待中使用各種技術來推展這個極限，從某一點來看，這個物理上的限制是無法克服的。
為了正視這項挑戰，工程師設計直立方向的裝 置。這些裝置在製造上很複雜，然而，它們掌握了提供小型化功能性裝置的前景，使用更多的半導體表面積卻不需使用光學微影中更小的樣式。其中一項直立式裝置就是環繞式閘極(VGAA)或奈米線(NW)裝置。
值得注意的是，先前的環繞式閘極或奈米線技術提供特定傳導類型的電晶體。在互補式金屬氧化半導體(CMOS)技術中，傾向於將每個n型金屬氧化物半導體連接到p型金屬氧化物半導體。這使互補式金屬樣化物半導體電路中的關閉狀態漏流降到最低。為了達成，使用先前的環繞式閘極技術必須提供分開的n型通道和p型通道區域，所以會佔據更多的積體電路表面積。
依據本發明其中一實施例，提供一種互補式電晶體結構。一柱體下部包含一半導電材料，例如鍺，形成於一基板上，該基板包含另一種半導體材料，例如矽。一第一閘極環繞柱體下部並與其絕緣。一柱體上部包含另一種半導電性材料，例如砷化銦。一第二閘極環繞柱體上部並與其絕緣。一電性接點連接柱體上部，該接點在第二閘極上；一第二電性接點連接上部和下部柱體，該接點在第一和第二閘極中間。
依據本發明另一實施例，提供形成互補式電晶體的方法。一第一半導體材料在一半導電性基板上形成柱體下部，該柱體下部包含一第二半導體材料。該第一半導電材 料可以使用一選擇性化學氣相沉積製程形成。形成一第一閘極環繞柱體下部並與其絕緣。形成一柱體上部，其包含一第三半導電材料。第三半導電材料使用一選擇性化學氣相沉積製程形成，以第一半導體材料為成核位置。形成一第二閘極環繞柱體上部並與其絕緣。再形成電性接點連接柱體上部，其中該接點在第二閘極上；以及形成電性接點連接柱體上部和下部，其中該接點在第一閘極和第二閘極中間。
本發明之實施例的優點是提供互補式電晶體，其中該電晶體使用一最小的積體電路表面積。
10‧‧‧矽晶體基板
12‧‧‧鍺奈米線
14‧‧‧砷化銦奈米線
16‧‧‧接點
18‧‧‧接點
20‧‧‧p型電晶體
22‧‧‧閘極
24‧‧‧閘極
26‧‧‧閘極絕緣體
28‧‧‧閘極絕緣體
30‧‧‧n型電晶體
32‧‧‧接點
34‧‧‧輸出接點
56‧‧‧閘極接點層
58‧‧‧金屬接點
60‧‧‧取代閘極介電層
112‧‧‧奈米線層
116‧‧‧虛擬閘極層
117‧‧‧閘極介電層
118‧‧‧開口
120‧‧‧閘極
122‧‧‧犧牲閘極層
124‧‧‧閘極
142‧‧‧介電層
143‧‧‧介電層
144‧‧‧共用接點層
42‧‧‧底部間隔層
44‧‧‧汲極接點金屬
46‧‧‧開口
48‧‧‧閘極介電層
50‧‧‧虛擬閘極材料
52‧‧‧介電層
54‧‧‧閘極接點孔洞
145‧‧‧介電層
146‧‧‧開口
147‧‧‧介電層
150‧‧‧虛擬閘極介電層
152‧‧‧虛擬閘極層
154‧‧‧介電層
156‧‧‧開口
158‧‧‧閘極介電層
160‧‧‧接點
162‧‧‧接點
為了更完整的了解本發明以及其優點，請搭配以下的文字和圖片當作參考，其中：第1圖繪示根據本發明一實施例之一對堆疊的互補式電晶體之側面示意圖。
第2圖繪示根據第1圖的實施例之等效電路圖。
第3圖繪示根據第1圖的實施例之平面示意圖。
第4A圖至第4V圖繪示一製程的平面示意圖，該製程包括本發明另一實施例以形成第1圖所示之實施例。
第5A圖至第5E圖繪示第4A圖至第4V圖的替代製程步驟，其中替代步驟包含本發明另一實施例。
第6A圖至第6W圖繪示根據本發明再一實施例之製程，該製程形成一對堆疊的互補式電晶體，其中包含本發明又一實施例。
以下將詳細討論本實施例的製造與使用，然而，應瞭解到，本發明提供實務的創新概念，其中可以用廣泛的各種特定內容呈現。底下討論的特定實施例僅為說明，並不能限制本發明的範圍。
以下將以特定的內容描述本發明的實施例，就是使用堆疊直立環繞式(VGAA)或奈米線(NW)電晶體當結構。儘管如此，本發明的創新概念並不侷限於特定結構的形成。事實上，本發明的創新概念也可用於其他結構形成。此外，即便本發明指向直立環繞式或奈米線電路的實施例，本發明的創新概念可用於其他類型的積體電路、電子結構以及其他相關。以下請參照圖示簡單說明的文字做調整：第1圖繪示根據本發明一實施例之側面示意圖。基板10是一矽晶體基板，其中摻雜係為提供導電性。鍺奈米線12形成於基板10的表面上並提供通道區給p型電晶體20。砷化銦奈米線14形成於奈米線12上，提供通道區給n型電晶體30。經由接點16提供一低參考電壓Vss至奈米線14的上方。經由接點18提供一高參考電壓Vdd至基板10。需要注意的是，不應該將Vdd分開於每個電晶體對。一接點如接點18可以提供Vdd至許多電晶體對。
閘極22和24分別作為電晶體20和30的閘極。閘極絕緣體26隔開閘極22和奈米線12。閘極絕緣體28隔開閘極24和奈米線14。在此實施方式中，接點32將閘極22和24相互連接。然而，在其他型態裡，為了允許不同的電路型態，閘極22和24可能有分開的接點。輸出接點34與奈米線14相 連，靠近於奈米線12和14中間的接點。這提供一輸出至反相器，該反向器由電晶體20和30形成。
第2圖繪示第1圖裝置之等效電路圖，其中相對標註各組件。第3圖繪示第1圖裝置之平面示意圖。
第4A圖至第4V圖繪示製程步驟之側面示意圖，該製程形成第1圖之實施例。一底部間隔層42設置於基板10上。基板10可由許多晶體半導電材料之一，例如矽晶體所形成。在基板10上植入摻雜物以提供導電性。間隔層42可以是氧化矽、氮化矽、類似材料或其組合。然後閘極接點金屬22沉積於間隔層42之上。閘極接點金屬22可以是多晶矽、氮化鈦、氮化鉭、鎢、鋁或類似材料或其組合。這提供了如第4A圖所示的結構。然後使用標準微影蝕刻技術圖案化閘極接點金屬22以提供如第4B圖所示的結構。
接著使用化學氣相沉積或類似的技術將一介電填充層加到間隔層42的外露部分。再使用一般的化學機械研磨(CMP)技術將複合層42平坦化，以提供如第4C圖所示的結構。介電填充層可以是氧化矽、氮化矽、類似材料或其組合。一額外的介電填充層再形成於複合層42之上，以提供如第4D圖所示的結構。此介電填充層使用標準沉積技術沉積後並使用標準化學機械研磨(CMP)平坦化，介電填充層可包含氧化矽、氮化矽或類似材料或其組合。形成此介電填充層的步驟可以是沉積後再化學機械研磨，或是沉積後化學機械研磨，並再次沉積。
第4E圖繪示下一步驟，其中使用標準金屬沉積 技術沉積汲極接點金屬44。汲極接點金屬44可以是鈦、氮化鈦、氮化鉭、鎢、鋁或類似材料或其組合。如第4F圖所示，然後使用標準微影與蝕刻技術圖案化汲極接點金屬44。如第4F圖所示，使用標準沉積和化學機械研磨技術擴充複合層42，以形成第二層奈米線電晶體30的底部間隔(見第1圖)。形成此介電層的步驟可以是沉積後再化學機械研磨，或是沉積後化學機械研磨，並再次沉積。此介電填充層可以是氧化矽、氮化矽、類似材料或其組合。
如第4H圖所示，蝕刻出一開口46，穿過介電層42、汲極接點金屬44和閘極接點金屬22直到基板10。可以使用反應式離子蝕刻或乾式蝕刻來蝕刻出開口46，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。如第4I圖所示，使用標準共形沉積技術來沉積一閘極介電層48。閘極介電層48可以是二氧化矽、二氧化鉿、三氧化二鋁、二氧化鋯或類似材料或其組合。閘極介電層48可能包含一高介電係數介電材料。此介電層厚度介於1~10nm。再使用非等向性蝕刻將閘極介電層48蝕刻出如第4J圖所示的型態。此非等向性蝕刻製程可以是反應式離子蝕刻或乾式蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。
如第4K圖所示，接著使用一選擇性磊晶技術，例如有機金屬化學氣相沉積(MOCVD)，以矽基板當成核位置沉積第一奈米線12。在一實施例中，奈米線12包含鍺晶 體。如第4L圖所示，閘極介電層48再額外蝕刻直到該閘極介電層48的頂端低於奈米線12的頂端約5~15nm。此蝕刻製程可以是反應式離子蝕刻或乾式蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合；或使用濕式蝕刻，蝕刻液使用氟化氫、氯化氫或其他類似化學品或其組合。
如第4M圖所示，使用選擇性磊晶技術，例如有機金屬化學氣相沉積，將第一奈米線區域12當作成核位置，沉積出第二奈米線通道區14。再一實施例中，第二奈米線14包含砷化銦晶體(一種III-V族化合物半導體)。
如第4N圖所示，接著使用原子層沉積(ALD)或化學氣相沉積(CVD)形成一光學虛擬閘極介電層50。虛擬閘極介電層可以是二氧化矽、氮化矽、二氧化鉿、二氧化鋯、三氧化二鋁或類似材料或其組合。此虛擬閘極介電層厚度介於1~10nm。如第4O圖所示，再沉積閘極金屬24。閘極金屬24可以是多晶矽、氮化鈦、氮化鉭、鎢、鋁、類似材料或其組合。閘極金屬24的厚度被蝕刻到如第4P圖所示，過程使用蝕刻或蝕刻搭配化學機械研磨。蝕刻步驟可以是反應式離子蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣或其他已知蝕刻氣體或其組合；或使用濕式蝕刻，其中蝕刻液使用氟化氫、氯化氫、四甲基氫氧化銨或其他類似化學品或其組合。接著使用標準微影蝕 刻技術將閘極金屬24形成如圖4Q所示的圖案。如第4R圖所示，再使用標準沉積和化學機械研磨技術形成一介電層52。介電層52可以是二氧化矽或氮化矽或類似材料或其組合。
如第4S圖所示，接著使用標準微影蝕刻技術形成一閘極接點孔洞54，再延伸孔洞深度如第4T圖所示。在此使用一種含兩個步驟的製程，其中使用高控制性的蝕刻來形成第4T圖所示的孔洞，再使用可蝕刻閘極金屬層22和24之更具侵蝕性的蝕刻。此蝕刻製程可以使用反應式離子蝕刻或乾式蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。
如第4U圖所示，使用標準選擇性沉積技術來沉積一閘極金屬接點層56。這閘極接點層提供導電性接點至閘極層22和24。閘極接點層56可以是氮化鈦、氮化鉭、鎢、鋁或類似材料或其組合。使用標準蝕刻製程將虛擬閘極材料50從奈米線通道上部的頂端移除。此蝕刻製程可以是反應式離子蝕刻或乾式蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣或其他已知蝕刻氣體或其組合；或使用濕式蝕刻，蝕刻液使用氟化氫、氯化氫或其他類似化學品或其組合。
如圖4V所示，沉積金屬接點58並使用標準微影蝕刻技術圖案化，這提供接點至閘極(輸入)、上部電晶體30 的源極(Vss)、輸出接點到汲極接點金屬44以及接點到基板。如第1圖所示，藉由控制鍺奈米線12的摻雜濃度和奈米線14中相對應的銦和砷的濃度，n型通道電晶體30及p型通道電晶體20形成一反相器。使用不同的摻雜物和/或相對濃度，電晶體30可以是p型通道，以及電晶體20可以n型通道。
在一替代性實施例中，從如第4S圖所示的結構開始，使用蝕刻製程移除閘極層24以及部分閘極層50，該部分閘極層50位於閘極層24和奈米線14中間。該蝕刻製程可以使用反應式離子蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣或其他已知蝕刻氣體或其組合；或使用濕式蝕刻，蝕刻液使用氟化氫、氯化氫、四甲基氫氧化銨或其他類似化學品或其組合。如第5A圖所示，使用一原子層沉積(ALD)技術形成一取代閘極介電層60。閘極介電層可以是二氧化矽、二氧化鉿、三氧化二鋁、二氧化鋯或類似材料或其組合，以及該閘極介電層厚度介於1~10nm。閘極介電層60包含一高介電係數介電材料。
如第5B圖所示，接著蝕刻開口54，將其延伸至閘極層22。該蝕刻製程可以使用反應式離子蝕刻或乾式蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。如第5C圖所示，使用如選擇性化學氣相沉積填滿開口54，以提供接點70並重新形成閘極層24。如第5D圖所示，利用蝕刻移除位於奈米線14上的部分虛擬閘極層50。該蝕刻製程可以使用反應式離子蝕刻，其中蝕刻氣體使用六氟化硫、四氯化 矽、八氟環丁烷、甲烷、氫氣或其他已知蝕刻氣體或其組合；或使用濕式蝕刻，蝕刻液使用氟化氫、氯化氫、四甲基氫氧化銨或其他類似化學品或其組合。
如圖5E所示，沉積金屬接點58並使用標準微影蝕刻技術圖案化，提供接點至閘極(輸入)、上部電晶體30的源極(Vss)、輸出接點到汲極接點金屬44以及接點至基板。如第1圖所示，藉由控制鍺奈米線12的摻雜濃度和奈米線14中相對應的銦和砷的濃度，n型通道電晶體30及p型通道電晶體20形成一反相器。使用不同的摻雜物和/或相對濃度，電晶體30可以是p型通道，以及電晶體20可以n型通道。
第6A圖至第6W圖繪示本發明另一實施例。在第6A圖中，形成一介電層142並圖案化於矽晶體基板110上。基板110可以是矽、砷化鎵、磷化銦、砷化銦或類似材料或任何其組合，其基板任意摻雜n型或p型(濃度為1x1016 to 5x1020cm-3)或半絕緣或任何其摻雜物組合。介電層可以是二氧化矽或氮化矽或類似材料或其組合。
如第6B圖所示，使用一磊晶技術例如MOCVD形成一奈米線層112。奈米線112可能包含鍺晶體。如第6C圖所示，一虛擬閘極層116形成於奈米線112和介電層142上，再形成一犧牲閘極層122於該虛擬閘極層116上。如第6D圖所示，使用蝕刻或蝕刻加上CMP將犧牲閘極層122回蝕。犧牲閘極層可能包含非晶矽、多晶矽、二氧化矽、氮化矽或類似材料或其組合。該蝕刻製程可以是反應式離子蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、 甲烷、氫氣或其他已知蝕刻氣體或其組合；或使用濕式蝕刻，其中蝕刻液使用氟化氫、氯化氫、四甲基氫氧化銨或其他類似化學品或其組合。如第6E圖所示，用標準光學微影技術在犧牲閘極層122上圖案化。
如第6F圖所示，使用標準沉積技術沉積一介電層143，再用CMP往下磨平。介電層143可以是二氧化矽、氮化矽或類似材料或其組合。如第6G圖所示，接著使用標準微影蝕刻技術形成一開口145使犧牲閘極層122外露。使用蝕刻製程移除犧牲閘極層122以及鄰近該犧牲閘極層122的部分虛擬閘極層116，形成一開口118。該道蝕刻製程可以使用如反應式離子蝕刻技術，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣或其他已知蝕刻氣體或其組合；或濕式蝕刻，使用氟化氫、氯化氫、四甲基氫氧化銨或其他類似化學品或其組合。最後形成的結構如第6H圖所示。
如第6I圖所示，使用ALD形成一閘極介電層117於開口118的表面上。閘極介電層117可包含二氧化矽、二氧化鉿、三氧化二鋁、二氧化鋯或類似材料或其組合，其厚度介於1~10nm。如第6J圖所示，使用標準共形沉積技術將開口118填滿，形成閘極120。閘極120金屬可為氮化鈦、氮化鉭、鎢、鋁或類似材料或其組合。
如第6K圖所示，使用標準微影技術沉積一介電層145並圖案化。形成介電層145的步驟可包含沉積後再CMP，或可包含沉積後使用CMP並再次沉積。介電層145 可包含二氧化矽或氮化矽或類似材料或其組合。如第6L圖所示，沉積一共用接點層144，使用標準微影蝕刻技術，其中可能包含CMP技術在該接觸層圖案化，形成一共用汲極接點144。該共用汲極接點144可能包含氮化鈦、氮化鉭、鎢、鋁或類似材料或其組合。如第6M圖所示，再沉積一介電層147。形成該介電層147的步驟可包含沉積後再CMP，或可包含沉積後使用CMP並再次沉積。介電層147可包含二氧化矽或氮化矽或類似材料或其組合。
如第6N圖所示，使用蝕刻圖案化形成一開口146，穿過介電層147和共用接點層144。如同形成開口146的部分步驟，從奈米線112的頂端和部分邊緣移除虛擬閘極層116。該蝕刻製程可包含反應式離子蝕刻或乾式蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。
如第6O圖所示，使用如MOVCD技術形成一奈米線114。在一實施例中，第二奈米線114包含一三五族晶體結構的砷化銦。如第6P圖所示，接著使用ALD或CVD形成一虛擬閘極介電層150，該虛擬閘極介電層可為二氧化矽、氮化矽、二氧化鉿、二氧化鋯、三氧化二鋁或類似材料或其組合。該虛擬閘極介電層的厚度介於1~10nm。如第6P圖所示，再沉積一虛擬閘極層152。該虛擬閘極層152可以是非晶矽、多晶矽或其他類似材料。再使用蝕刻或蝕刻加上CMP將虛擬層152回蝕到如第6Q圖所示的厚度。該蝕刻步驟可以是反應式離子蝕刻，其中蝕刻氣體使用六氟化硫、四 氯化矽、八氟環丁烷、甲烷、氫氣、其他已知蝕刻氣體或其組合；或濕式蝕刻，使用氟化氫、氯化氫、四甲基氫氧化銨或其他類似化學品或其組合。使用標準微影蝕刻技術於虛擬閘極層152形成圖案，以提供如第6R圖所示的結構。
如第6S圖所示，介電層154使用標準沉積技術沉積以及使用CMP技術平坦化。介電層154可以是二氧化矽或氮化矽或類似材料或其組合。接著，如第6T圖所示，使用標準微影蝕刻技術形成一開口156。再移除虛擬閘極152，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣或其他已知蝕刻氣體或其組合；或使用濕式蝕刻，蝕刻液使用氟化氫、氯化氫、四甲基氫氧化銨或其他類似化學品或其組合。所以部分虛擬閘極介電層150會外露，該外露部分會一起在這道製程裡被移除。再使用ALD技術沉積閘極介電層158，以提供如第6U圖所示的結構。閘極介電層158可以是二氧化矽、二氧化鉿、三氧化二鋁、二氧化鋯或類似材料或其組合，該閘極介電層158厚度可為1~10nm。如第6U圖所示，蝕刻至閘極120上部外露形成開口156，該開口156垂直延伸穿過閘極介電層158、介電層147和介電層145。該蝕刻製程可以是反應式離子蝕刻或乾式蝕刻，其中蝕刻氣體使用六氟化硫、四氯化矽、八氟環丁烷、甲烷、氫氣、氬或其他已知蝕刻氣體或其組合。
接著，使用標準選擇性CVD製程填滿開口156形成一閘極124，該開口區域是虛擬閘極152被移除時空出來的。閘極124可能包含氮化鈦、氮化鉭、鎢、鋁或類似材 料或其組合。最後的結構如第6V圖所示。再使用標準蝕刻技術移除虛擬閘極層150上部。再使用標準技術沉積接點160和162並圖案化，以提供如第6W圖所示最後的結構。未顯示的接點也會提供接點至共用接點144和基板110(Vdd)。
依據本發明其中一實施例，提供一種互補式電晶體結構。一柱體下部包含一半導電材料，例如鍺，形成於一基板上，該基板包含另一種半導體材料，例如矽。一第一閘極環繞柱體下部並與其絕緣。一柱體上部包含另一種半導電性材料，例如砷化銦。一第二閘極環繞柱體上部並與其絕緣。一電性接點連接柱體上部，該接點在第二閘極上；一第二電性接點連接上部和下部柱體，該接點在第一和第二閘極中間。
依據本發明另一實施例，提供形成互補式電晶體的方法。一第一半導體材料在一半導電性基板上形成柱體下部，該柱體下部包含一第二半導體材料。該第一半導電材料可以使用一選擇性化學氣相沉積製程形成。形成一第一閘極環繞柱體下部並與其絕緣。形成一柱體上部，其包含一第三半導電材料。第三半導電材料使用一選擇性化學氣相沉積製程形成，以第一半導體材料為成核位置。形成一第二閘極環繞柱體上部並與其絕緣。再形成電性接點連接柱體上部，其中該接點在第二閘極上；以及形成電性接點連接柱體上部和下部，其中該接點在第一閘極和第二閘極中間。
本發明之實施例的優點是提供互補式電晶體， 其中該電晶體使用一最小的積體電路表面積。
儘管本發明使用圖文參照來詳述實施例，但這些敘述不應解釋為限制意義。對於熟習此技藝的人可以透過參考本說明，明確地了解各種繪示實施例的改良和結合，以及了解本發明中其他的實施例。因此要附加說明專利範圍包含任何改良或實施例。
10‧‧‧矽晶體基板
12‧‧‧鍺奈米線
14‧‧‧砷化銦奈米線
16‧‧‧接點
18‧‧‧接點
20‧‧‧p型電晶體
22‧‧‧閘極
24‧‧‧閘極
26‧‧‧閘極絕緣體
28‧‧‧閘極絕緣體
30‧‧‧n型電晶體
32‧‧‧接點
34‧‧‧輸出接點

Claims (10)

  1. 一種互補式金氧半場效電晶體結構，包含：一柱體下部包含一第二半導電材料，該柱體下部形成於一基板上，其中該基板包含第一半導電材料；一第一閘極環繞及絕緣於柱體下部；一柱體上部包含一第三半導電材料；一第二閘極環繞及絕緣於柱體上部；一第一電性接點與該柱體上部連接，其中該第一電性接點位於第二閘極上；以及一第二電性接點與該柱體上下部連接，其中該第二電性接點在第一與第二閘極的中間。
  2. 如請求項1所述之互補式金氧半場效電晶體結構，其中柱體下部使用選擇性沉積形成。
  3. 如請求項1所述之互補式金氧半場效電晶體結構，其中柱體上部使用選擇性沉積形成。
  4. 一互補式金氧半場效電晶體結構，包含：一柱體下部包含鍺晶體，該柱體下部形成於矽基板上；一第一閘極環繞並絕緣於柱體下部；一柱體上部含砷化銦，該柱體上部形成於柱體下部上；一第二閘極環繞並絕緣於柱體上部； 一第一電性接點與柱體上部連接，其中該接點位於第二閘極上；以及一第二電性接點與柱體上下部連接，其中該接點在第一與第二閘極的中間。
  5. 如請求項4所述之互補式金氧半場效電晶體結構，其中柱體下部提供p型場效電晶體一通道區，以及柱體上部提供n型場效電晶體一通道區。
  6. 如請求項4所述之互補式金氧半場效電晶體結構，其中柱體下部提供n型場效電晶體一通道區，以及柱體上部提供p型場效電晶體一通道區。
  7. 如請求項4所述之互補式金氧半場效電晶體結構，其中第一閘極藉由高介電系數介電層與柱體下部絕緣。
  8. 如請求項4所述之互補式金氧半場效電晶體結構，其中第二閘極藉由高介電系數介電層與柱體上部絕緣。
  9. 一種製作互補式金氧半場效電晶體的方法，包含：一柱體下部包含一第二半導電材料，該柱體下部形成於一基板上，其中該基板包含一第一半導電材料； 一第一閘極環繞並絕緣於柱體下部；一柱體上部，其中包含一第三半導電材料；一第二閘極環繞並絕緣於柱體上部；一第一電性接點與柱體上部相連，其中該接點在第二閘極上；以及一第二電性接點與柱體上下部連接，其中該接點在第一和第二閘極中間。
  10. 如請求項9所述之形成互補式金氧半場效電晶體的方法，其中形成一柱體上部的步驟使用選擇性化學氣相沉積。
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