CN107068679A - 半导体装置与其形成方法 - Google Patents

半导体装置与其形成方法 Download PDF

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Publication number
CN107068679A
CN107068679A CN201710073636.2A CN201710073636A CN107068679A CN 107068679 A CN107068679 A CN 107068679A CN 201710073636 A CN201710073636 A CN 201710073636A CN 107068679 A CN107068679 A CN 107068679A
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CN107068679B (zh
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廖舜章
王淑慧
张世勋
廖家骏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供半导体装置及其形成方法。半导体装置包括：第一型沟道场效晶体管，包含具有第一栅极结构的第一第一型沟道场效晶体管，以及具有第二栅极结构的第二第一型沟道场效晶体管。第一第一型沟道场效晶体管的临界电压小于第二第一型沟道场效晶体管的临界电压。第一栅极结构包含第一功函数调整材料层，且第二栅极结构包含第二功函数调整材料层。第一功函数调整材料层与第二功函数调整材料层的厚度与材料中至少一者彼此不同。

Description

半导体装置与其形成方法
技术领域
本公开实施例涉及半导体装置的形成方法。
背景技术
当半导体产业进展至纳米技术工艺节点以达更高装置密度、更高效能、与更低成本时，来自制作与设计的双重挑战导致三维设计(如鳍状场效晶体管)与金属栅极结构搭配高介电常数材料的发展。金属栅极结构的形成方法通常为栅极置换技术。
发明内容
本公开一实施例提供的半导体装置，包括：第一型沟道场效晶体管，包含具有第一栅极结构的第一第一型沟道场效晶体管，以及具有第二栅极结构的第二第一型沟道场效晶体管，其中：第一第一型沟道场效晶体管的临界电压小于第二第一型沟道场效晶体管的临界电压，第一栅极结构包含第一功函数调整材料层，且第二栅极结构包含第二功函数调整材料层，以及第一功函数调整材料层与第二功函数调整材料层的厚度与材料中至少一者彼此不同。
本公开一实施例提供的半导体装置，包括：第一n型沟道场效晶体管，包含具有临界电压Vn1的第一栅极结构；第二n型沟道场效晶体管，包含具有临界电压Vn2的第二栅极结构；第三n型沟道场效晶体管，包含具有临界电压Vn3的第三栅极结构；第一p型沟道场效晶体管，包含具有临界电压Vp1的第四栅极结构；第二p型沟道场效晶体管，包含具有临界电压Vp2的第五栅极结构；以及第三p型沟道场效晶体管，包含具有临界电压Vp3的第六栅极结构，其中：Vn1<Vn2<Vn3且p1<Vp2<Vp3，第一栅极结构包含第一功函数调整材料层，第二栅极结构包含第二功函数调整材料层，第三栅极结构包含第三功函数调整材料层，第四栅极结构包含第四功函数调整材料层，第五栅极结构包含第五功函数调整材料层，且第六栅极结构包含第六功函数调整材料层，以及第一功函数调整材料层、第二功函数调整材料层、第三功函数调整材料层、第四功函数调整材料层、第五功函数调整材料层、与第六功函数调整材料层的厚度与材料中至少一者彼此不同。
本公开一实施例提供的半导体装置的形成方法，包括：形成栅极介电层于用于多个场效晶体管的每一沟道层上；形成第一导电层于栅极介电层上；形成功函数调整材料层于第一导电层上；以及形成第二导电层于功函数调整材料层上，其中：形成功函数调整材料层以用于至少一场效晶体管的步骤包含：形成一或多个导电层并蚀刻一或多个导电层，以露出第一导电层的第一步骤；以及形成导电层且不蚀刻导电层的第二步骤。
附图说明
图1至图6是本公开一实施例中，半导体装置的工艺中多种阶段的剖视图。
图7是对应图6的区域61的放大剖视图。
图8A至图8C与图9A至图9C是本公开多种实施例中，对应图6的区域61的多种晶体管的放大剖视图。
图10A至图10D是本公开一实施例中，依序形成金属栅极结构的工艺的多种阶段其剖视图。
图11A至图11H是本公开另一实施例中，依序形成金属栅极结构的工艺的多种阶段其剖视图。
附图标记说明：
N1 第一n型沟道场效晶体管
N2 第二n型沟道场效晶体管
N3 第三n型沟道场效晶体管
P1 第一p型沟道场效晶体管
P2 第二p型沟道场效晶体管
P3 第三p型沟道场效晶体管
10 基板
15 掩模图案
20 鳍状结构
30 隔离绝缘层
40 虚置栅极结构
42 界面层
44 栅极介电层
45 掩模图案
50 层间介电层
55 栅极空间
60 金属栅极结构
61 区域
70 第一导电层
80 功函数调整材料层
90 第二导电层
95 第三导电层
100 第一功函数调整材料层
110 第二功函数调整材料层
120 第三功函数调整材料层
130 第四功函数调整材料层
140 第五功函数调整材料层
150 第六功函数调整材料层
具体实施方式
应理解的是，下述内容提供的不同实施例可实施本公开的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本公开。举例来说，元件尺寸并不限于公开的范围或数值，端视工艺调件及/或所需的装置性质而定。此外，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。为简化与清楚说明，可采用不同比例绘示多种结构。
此外，空间性的相对用语如「下方」、「其下」、「较下方」、「上方」、「较上方」、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。此外，用语「…的组成为」可指「包含」或「由…组成」。
图1至图6是本公开一实施例中，半导体装置的工艺中多种阶段的剖视图。
首先，在基板10上制作一或多个鳍状结构20。鳍状结构20包含底部区域与较上区域(如沟道区)。举例来说，基板10可为p型硅基板，其杂质浓度介于约1×1015cm-3至约1×1018cm-3之间。在其他实施例中，基板为n型硅基板，其杂质浓度介于约1×1015cm-3至约1×1018cm-3之间。在其他实施例中，基板10可包含其他半导体元素如锗、半导体化合物(IV-VI族半导体化合物如SiC或SiGe，III-V族半导体化合物如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP、或GaInAsP)、或上述的组合。在一实施例中，基板10为或绝缘层上硅基板的硅层。
为制作鳍状结构20，形成掩模层于基板10上，并在掩模层上进行图案化步骤(包含光刻工艺与蚀刻工艺)以形成掩模图案15。掩模图案15包含一或多层的绝缘材料如氧化硅与氮化硅。在一些实施例中，掩模图案15包含氧化硅组成的较下层，与氮化硅组成的较上层。掩模层的形成方法可为热氧化、低压化学气相沉积、等离子体化学气相沉积、或其他合适的成膜方法。
如图1所示，以掩模图案15作为蚀刻掩模，蚀刻基板10以形成沟槽与鳍状结构20。
在形成鳍状结构20后，形成隔离绝缘层30于鳍状结构20上。隔离绝缘层30包含一或多层的绝缘材料如氧化硅、氮氧化硅、或氮化硅，其形成方法可为低压化学气相沉积、等离子体化学气相沉积、或可流动化学气相沉积。隔离绝缘层可为一或多层的旋转涂布玻璃、SiO、SiON、SiOCN、及/或掺杂氟的硅酸盐玻璃。
在形成隔离绝缘层30于鳍状结构上之后，进行平坦化步骤以移除隔离绝缘层30的较上部分。平坦化步骤可包含化学机械研磨及/或回蚀刻工艺。接着可进一步移除(凹陷化)隔离绝缘层30，以露出鳍状结构20的较上区域，如图2所示。鳍状结构20的露出部分将成为鳍状场效晶体管的沟道区。
如图3所示，形成虚置栅极结构40于露出的鳍状结构20上。虚置栅极结构40包含虚置栅极(组成可为硅)与虚置栅极介电层(组成可为氧化硅)。侧壁间隔物亦可形成于虚置栅极结构的侧壁上，其可包含一或多层的绝缘材料。
为制作虚置栅极结构，先形成虚置栅极层的毯覆层于图2的结构上，再形成多晶硅层的毯覆层于虚置栅极介电层上。接着形成掩模层于多晶硅层上，并在掩模层上进行图案化步骤以得掩模图案45。以掩模图案45作为蚀刻掩模，图案化多晶硅层以形成虚置栅极结构40，如图3所示。
在此发明实施例中，图1至图6中仅图示用于单一虚置栅极结构的两个鳍状结构。然而鳍状结构与虚置栅极结构的数目并不限于图1至图6所示的数目。虚置栅极结构40沿着X方向延伸，而鳍状结构沿着Y方向(未图示)延伸且X方向占有宽度，其中Y方向垂直于X方向与Z方向。
在形成虚置栅极结构40后，虚置栅极结构未覆盖的鳍状结构20将凹陷至低于隔离绝缘层30的上表面。接着以外延成长法形成源极/漏极区(未图示)于凹陷的鳍状结构上。源极/漏极区可包含应力材料，以施加应力至沟道区。
接着形成层间介电层50于虚置栅极结构40与源极/漏极区上，如图4所示。在平坦化步骤后，移除虚置栅极结构40以形成栅极空间55，如图5所示。接着形成金属栅极结构60于栅极空间55中，如图6所示。
图7是对应图6的区域61的放大剖视图。在形成界面层42于鳍状结构20上之后，形成栅极介电层44于鳍状结构20的较上部分(沟道区)上。栅极介电层44包含一或多层的金属氧化物，比如高介电常数的金属氧化物。举例来说，用于高介电常数的金属氧化物的金属氧化物包含Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu、及/或上述的混合物的氧化物。举例来说，界面层42的组成可为二氧化硅。栅极介电层44的形成方法可为化学气相沉积、原子层沉积、或其他合适的成膜方法。
此外，第一导电层70形成于栅极介电层44上，其作为后续蚀刻工艺中的阻挡层或保护层。第一导电层70包含一或多层的Ti、Ta、TiN、TaN、或上述的组合。在一实施例中，第一导电层70采用TaN层。在其他实施例中，第一导电层70包含TaN层形成于Ti层上。
金属栅极结构60还包括一或多层的功函数调整材料层80形成于第一导电层70上。第二导电层90形成于功函数调整材料层80上，且主要栅极金属层的第三导电层95形成于第二导电层90上。
第二导电层90作为用于第三导电层的粘着层，其可包含一或多层的Ti、Ta、TiN、TaN、或上述的组合。在一实施例中，第二导电层90采用TiN层。第三导电层95包含金属材料如W、Co、Ni、Cu、Al、上述的合金、或其他合适材料。
功函数调整材料层80包含一或多层的导电材料如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi、或TiAlC。对n型沟道场效晶体管而言，功函数调整材料层可采用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi、与TaSi中的一或多者。对p型沟道场效晶体管而言，功函数调整材料层可采用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC、与Co中的一或多者。
一些半导体装置包含具有不同临界电压的多种晶体管。举例来说，n型沟道场效晶体管可设定为两或三种不同的临界电压，而p型沟道场效晶体管可设定为两或三种不同的临界电压。在本公开实施例中，通过调整功函数调整材料层80的厚度及/或材料，可调整多种晶体管的临界电压。
图8A至图8C是本公开多种实施例中，对应图6的区域61其用于n型沟道场效晶体管的功函数调整材料层的结构。
图8A是具有临界电压Vn1(比如极低电压)的第一n型沟道场效晶体管N1，图8B是具有临界电压Vn2(比如低电压)的第二n型沟道场效晶体管N2，且图8C是具有临界电压Vn3(比如标准电压)的第三n型沟道场效晶体管N3。上述Vn1<Vn2<Vn3。在一些实施例中，上述三种n型沟道场效晶体管位于核心区。
在图8A中，第一n型沟道场效晶体管N1包含第一功函数调整材料层100(作为功函数调整材料层80)。在一实施例中，第一功函数调整材料层100包含TiAlC。在一些实施例中，第一功函数调整材料层100的厚度介于约0.5nm至约10nm之间。在其他实施例中，第一功函数调整材料层100的厚度介于约3nm至约5nm之间。
在图8B中，第二n型沟道场效晶体管N2包含第二功函数调整材料层110形成于第一导电层70上，以及第一功函数调整材料层100形成于第二功函数调整材料层110上，且第二功函数调整材料层110与第一功函数调整材料层100作为功函数调整材料层80。在一实施例中，第二功函数调整材料层110包含TiN。值得注意的是，最靠近鳍状结构的沟道区的功函数调整材料层，实质上决定临界电压。在一些实施例中，第二功函数调整材料层110的厚度介于约0.5nm至1.2nm之间。
在图8C中，第三n型沟道场效晶体管N3包含第三功函数调整材料层120形成于第一导电层70上，第二功函数调整材料层110形成于第三功函数调整材料层120上，以及第一功函数调整材料层100形成于第二功函数调整材料层110上，且第三功函数调整材料层120、第二功函数调整材料层110、与第一功函数调整材料层100作为功函数调整材料层80。在一实施例中，第三功函数调整材料层120包含TiN。若任何相邻的两个功函数调整材料层的组成材料相同，则这两个功函数调整材料层可视作一个厚层的功函数调整材料层。举例来说，当第三功函数调整材料层120与第二功函数调整材料层110由相同材料组成，上述两者可视作一个厚层的功函数调整材料层。在一些实施例中，第三功函数调整材料层120的厚度介于约0.5nm至1.3nm之间。
如图8A至图8C所示，在第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、与第三n型沟道场效晶体管N3中，用于第一n型沟道场效晶体管N1的功函数调整材料层80的总厚度最小，而用于第三n型沟道场效晶体管N3的功函数调整材料层80的总厚度最大。
如前所述，通过调整功函数调整材料层80的厚度与材料，可调整第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、与第三n型沟道场效晶体管N3的临界电压至0<Vn1<Vn2<Vn3。
图9A至图9C是本公开多种实施例中，对应图6的区域61其用于p型沟道场效晶体管的功函数调整材料层的结构。
图9A是具有临界电压Vp1(比如标准电压)的第一p型沟道场效晶体管P1，图9B是具有临界电压Vp2(比如低电压)的第二p型沟道场效晶体管P2，且图9C是具有临界电压Vp3(比如极低电压)的第三p型沟道场效晶体管P3。上述Vp1<Vp2<Vp3<0V。在一些实施例中，上述三种p型沟道场效晶体管位于核心区。
在图9A中，第一p型沟道场效晶体管P1包含第四功函数调整材料层130形成于第一导电层70、第三功函数调整材料层120、第二功函数调整材料层110、与第一功函数调整材料层100上，且第四功函数调整材料层130、第三功函数调整材料层120、第二功函数调整材料层110、与第一功函数调整材料层100作为功函数调整材料层80。在一实施例中，第四功函数调整材料层130包含TiN。在一些实施例中，第四功函数调整材料层130的厚度介于约1.0nm至约2.0nm之间。
在图9B中，第二p型沟道场效晶体管P2包含第五功函数调整材料层140形成于第一导电层70、第四功函数调整材料层130、第三功函数调整材料层120、第二功函数调整材料层110、与第一功函数调整材料层100上，且第五功函数调整材料层140、第四功函数调整材料层130、第三功函数调整材料层120、第二功函数调整材料层110、与第一功函数调整材料层100作为功函数调整材料层80。在一实施例中，第五功函数调整材料层140包含TiN。在一些实施例中，第五功函数调整材料层140的厚度介于约0.5nm至约1.5nm之间。
在图9C中，第三p型沟道场效晶体管P3包含第六功函数调整材料层150形成于第一导电层70、第五功函数调整材料层140、第四功函数调整材料层130、第三功函数调整材料层120、第二功函数调整材料层110、与第一功函数调整材料层100上，且第六功函数调整材料层150、第五功函数调整材料层140、第四功函数调整材料层130、第三功函数调整材料层120、第二功函数调整材料层110、与第一功函数调整材料层100作为功函数调整材料层80。在一实施例中，第六功函数调整材料层150包含TiN。在一些实施例中，第六功函数调整材料层150的厚度介于约1.0nm至约2.5nm之间。
若任何相邻的两个功函数调整材料层的组成材料相同，则这两个功函数调整材料层可视作一个厚层的功函数调整材料层。举例来说，当第六(第五、第四、或第三)功函数调整材料层至第二功函数调整材料层由相同材料组成，上述相邻的相同材料层可视作一个厚层的功函数调整材料层。
如图9A至图9C所示，在第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3中，用于第一p型沟道场效晶体管P1的功函数调整材料层80的总厚度最小，而用于第三n型沟道场效晶体管P3的功函数调整材料层80的总厚度最大。此外，用于第一p型沟道场效晶体管P1的功函数调整材料层80的总厚度，大于用于第三n型沟道场效晶体管N3的功函数调整材料层80的总厚度。
如前所述，通过调整功函数调整材料层80的厚度与材料，可调整第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3的临界电压至Vp1>Vp2>Vp3。
在图8A至图8C与图9A至图9C中，第一n型沟道场效晶体管N1包含第一材料(如TiAlC)的功函数调整材料层，且第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3包含第一材料与第二材料(如TiN)的两种功函数调整材料层，其中不同场效晶体管中第二材料的功函数调整材料层厚度不同。在一些实施例中，第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3中至少一者不含第一材料(如第一功函数调整材料层100)。在其他实施例中，第一n型沟道场效晶体管N1还包括第二材料的功函数调整材料层形成于第一材料的功函数调整材料层上。此外，一些实施例采用三种或更多种的材料用于功函数调整材料层。在其他实施例中，用于第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3的功函数调整材料层80，采用不同厚度的相同材料。在这些例子中，第一n型沟道场效晶体管N1的功函数调整材料层80的厚度最小，而用于第三p型沟道场像晶体管P3的功函数调整材料层80的厚度最大。
此外，一些实施例中的半导体装置包含不同临界电压的两种n型沟道场效晶体管，及/或不同临界电压的两种p型沟道场效晶体管。在其他实施例中，半导体装置包含四种或更多种不同临界电压的n型沟道场效晶体管，及/或四种或更多种不同临界电压的p型沟道场效晶体管。
在一些实施例中，上述三种n型沟道场效晶体管与三种p型沟道场效晶体管位于输入/输出区，其栅极介电层厚度大于核心区的栅极介电层厚度。在这些实施例中，输入/输出区中的栅极介电层厚度介于约3nm至约6nm之间，而核心区中的栅极介电层厚度介于约0.5nm至约2nm之间。
图10A至图10D是本公开一实施例中，依序形成金属栅极结构的工艺的多种阶段其剖视图。图10A至图10D主要为用于n型沟道场效晶体管的金属栅极结构的工艺，但与用于p型沟道场效晶体管的金属栅极结构的工艺实质上类似。
在图10A中，功函数调整材料层(如第三功函数调整材料层120)形成在用于第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、与第三n型沟道场效晶体管N3的第一导电层70上，并干蚀刻移除第一n型沟道场效晶体管N1与第二n型沟道场效晶体管N2的第三功函数调整材料层120。通过干蚀刻，可露出用于第一n型沟道场效晶体管N1与第二n型沟道场效晶体管N2的第一导电层70。
在图10B中，形成另一功函数调整材料层(如第二功函数调整材料层110)在用于第一n型沟道场效晶体管N1与第二n型沟道场效晶体管N2的第一导电层70上，以及用于第三n型沟道场效晶体管N3的第三功函数调整材料层120上。接着干蚀刻移除第一n型沟道场效晶体管N1上的第二功函数调整材料层110。通过干蚀刻，可露出用于第一n型沟道场效晶体管N1的第一导电层70。
在图10C中，形成又一功函数调整材料层(如第一功函数调整材料层100)在用于第一n型沟道场效晶体管N1的第一导电层70上，以及用于第二n型沟道场效晶体管N2与第三n型沟道场效晶体管N3的第二功函数调整材料层110上。接着形成第二导电层90与第三导电层95于第一功函数调整材料层100上，如图10D所示。
前述工艺步骤包含形成一或多个导电层与蚀刻一或多个导电层，以露出第一导电层的第一步骤，以及形成导电层及不蚀刻导电层的第二步骤。形成用于第一n型沟道场效晶体管N1的功函数调整材料层(比如第一功函数调整材料层100)的工艺步骤包含两个第一步骤与一个第二步骤。形成用于第二n型沟道场效晶体管N2的功函数调整材料层(比如第一功函数调整材料层100与第二功函数调整材料层110)的工艺步骤包含一个第一步骤与两个第二步骤。形成用于第三n型沟道场效晶体管N3的功函数调整材料层的工艺步骤包含三个第二步骤而无第一步骤。
图11A至图11H是本公开一实施例中，依序形成金属栅极结构的工艺的多种阶段其剖视图。图11A至图11H是用于三个n型沟道场效晶体管与三个p型沟道场效晶体管的金属栅极结构的工艺。
在图11A中，形成第六功函数调整材料层150在用于第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3的第一导电层70上。接着干蚀刻移除第二p型沟道场效晶体管P2上的第六功函数调整材料层150。通过干蚀刻，可露出用于第二p型沟道场效晶体管P2的第一导电层70。
在图11B中，形成第五功函数调整材料层140在用于第二p型沟道场效晶体管P1的第一导电层上，以及用于第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、第一p型沟道场效晶体管P1、与第三p型沟道场效晶体管P3的第六功函数调整材料层150上。接着干蚀刻移除用于第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、与第一p型沟道场效晶体管P1的第五功函数调整材料层140与第六功函数调整材料层150，如图11C所示。通过干蚀刻，可露出第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、与第一p型沟道场效晶体管P1的第一导电层70。
在图11D中，形成第四功函数调整材料层130在用于第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、与第一p型沟道场效晶体管P1的第一导电层70上，以及用于第二p型沟道场效晶体管P2与第三p型沟道场效晶体管P3的第五功函数调整材料层140上。接着干蚀刻移除用于第三n型沟道场效晶体管N3的第四功函数调整材料层130，如图11D所示。通过干蚀刻，可露出第三n型沟道场效晶体管N3的第一导电层70。
在图11E中，形成第三功函数调整材料层120在用于第三n型沟道场效晶体管N3的第一导电层70上，以及用于第一n型沟道场效晶体管N1、第二n型沟道场效晶体管N2、第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3的第四功函数调整材料层130上。接着以干刻移除第一n型沟道场效晶体管N1与第二n型沟道场效晶体管N2的第三功函数调整材料层120，如图11F所示。通过干蚀刻，可露出第一n型沟道场效晶体管N1与第二n型沟道场效晶体管N2的第一导电层70。
在图11G中，形成第二功函数调整材料层110在用于第一n型沟道场效晶体管N1与第二n型沟道场效晶体管N2的第一导电层70上，以及用于第三n型沟道场效晶体管N3、第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3的第三功函数调整材料层120上。接着干蚀刻移除用于第一n型沟道场效晶体管N1的第二功函数调整材料层110，如图11G所示。通过干蚀刻，可露出第一n型沟道场效晶体管N1的第一导电层70。
在图11H中，形成第一功函数调整材料层100在用于第一n型沟道场效晶体管N1的第一导电层70上，以及用于第二n型沟道场效晶体管N2、第三n型沟道场效晶体管N3、第一p型沟道场效晶体管P1、第二p型沟道场效晶体管P2、与第三p型沟道场效晶体管P3的第二功函数调整材料层110上。接着形成第二导电层90与第三导电层95于第一功函数调整材料层100上，如图11H所示。
前述工艺步骤包含形成一或多个导电层与蚀刻一或多个导电层，以露出第一导电层的第一步骤，以及形成导电层及不蚀刻导电层的第二步骤。
形成用于第一n型沟道场效晶体管N1的功函数调整材料层(比如第一功函数调整材料层100)的工艺步骤包含三个第一步骤与一个第二步骤。形成用于第二n型沟道场效晶体管N2的功函数调整材料层(比如第一功函数调整材料层100与第二功函数调整材料层110)的工艺步骤包含两个第一步骤与两个第二步骤。形成用于第三n型沟道场效晶体管N3的功函数调整材料层(比如第一功函数调整材料层100、第二功函数调整材料层110、与第三功函数调整材料层120)的工艺步骤包含两个第一步骤与三个第二步骤。
形成用于第一p型沟道场效晶体管P1的功函数调整材料层(比如第一功函数调整材料层100、第二功函数调整材料层110、第三功函数调整材料层120、与第四功函数调整材料层130)的工艺步骤包含一个第一步骤与四个第二步骤。形成用于第二p型沟道场效晶体管P2的功函数调整材料层(比如第一功函数调整材料层100、第二功函数调整材料层110、第三功函数调整材料层120、第四功函数调整材料层130、与第五功函数调整材料层140)的工艺步骤包含一个第一步骤与五个第二步骤。形成用于第三p型沟道场效晶体管P3的功函数调整材料层(比如第一功函数调整材料层100、第二功函数调整材料层110、第三功函数调整材料层120、第四功函数调整材料层130、第五功函数调整材料层140、与第六功函数调整材料层150)的工艺步骤包含六个第二步骤而无第一步骤。
在上述工艺步骤中，功函数调整材料层的形成方法可为化学气相沉积、物理气相沉积如溅镀、原子层沉积、电镀、或其他合适的成膜方法。
与现有技术相较，上述多种实施例或实例具有多种优点。举例来说，本公开实施例调整功函数调整材料层的厚度及/或材料，可调整用于多种晶体管的临界电压。举例来说，与公知采用单一厚度的功函数调整材料层的技术相较，n型沟道场效晶体管中低电压晶体管与极低电压晶体管之间的临界电压偏移(差异)可降低约7％，而p型沟道场效晶体管中低电压晶体管与极低电压晶体管之间的临界电压偏移(差异)可降低约11％。在一些实施例中，n型沟道场效晶体管的临界电压偏移小于或等于2％，而p型沟道场效晶体管的临界电压偏移小于或等于约4％。此外，本公开实施例的工艺步骤中第一导电层70的曝露次数顶多为三次，因此可让第一导电层70的厚度最小化。另一方面，功函数调整材料层的蚀刻步骤最多只在两个功函数调整材料层上进行，因此可让蚀刻对第一导电层70的损伤最小化。
应理解的是，上述内容不必说明所有的优点，且所有实施例或实例均不需具有特定优点。其他实施例或实例可提供不同的优点。
依据本公开一实施例，半导体装置包括：第一型沟道场效晶体管，其包含具有第一栅极结构的第一第一型沟道场效晶体管，以及具有第二栅极结构的第二第一型沟道场效晶体管。第一第一型沟道场效晶体管的临界电压小于第二第一型沟道场效晶体管的临界电压。第一栅极结构包含第一功函数调整材料层，且第二栅极结构包含第二功函数调整材料层。第一功函数调整材料层与第二功函数调整材料层的厚度与材料中至少一者彼此不同。
在一些其他实施例中，该第一型沟道场效晶体管还包括具有第三栅极结构的一第三第一型沟道场效晶体管，其中该第三第一型沟道场效晶体管的临界电压大于第二第一型沟道场效晶体管的临界电压，该第三栅极结构包含一第三功函数调整材料层，以及该第一功函数调整材料层、该第二功函数调整材料层、与该第三功函数调整材料层的厚度与材料中至少一者彼此不同。
在一些其他实施例中，该第一功函数调整材料层包含第一材料组成的第一层；该第二功函数调整材料层与该第三功函数调整材料层各自包含第一材料组成的第一层，以及第二材料组成的第二层位于第一层上，其中第一材料不同于第二材料。
在一些其他实施例中，该第二功函数调整材料层的第二层的厚度，小于该第三功函数调整材料层的第二层的厚度。
在一些其他实施例中，该第二材料为TiN。
在一些其他实施例中，该第一功函数调整材料层、该第二功函数调整材料层、与该第三功函数调整材料层各自形成于第一导电层上，且第一导电层位于栅极介电层上。
在一些其他实施例中，该第一导电层包括TaN层。
在一些其他实施例中，该第一功函数调整材料层、该第二功函数调整材料层、与该第三功函数调整材料层各自包含第二材料的层状物，以及该第一功函数调整材料层的第二材料的层状物厚度小于该第二功函数调整材料层的第二材料的层状物厚度，且该第二功函数调整材料层的第二材料的层状物厚度小于该第三功函数调整材料层的第二材料的层状物厚度。
在一些其他实施例中，该第一功函数调整材料层、该第二功函数调整材料层、与该第三功函数调整材料层各自包含第一材料的层状物位于该第二材料的层状物上。
在一些其他实施例中，该第二材料为TiN。
在一些其他实施例中，第二材料的层状物形成于第一导电层上，且第一导电层位于栅极介电层上。
依据本公开另一实施例，半导体装置包括：第一n型沟道场效晶体管，包含具有临界电压Vn1的第一栅极结构；第二n型沟道场效晶体管，包含具有临界电压Vn2的第二栅极结构；第三n型沟道场效晶体管，包含具有临界电压Vn3的第三栅极结构；第一p型沟道场效晶体管，包含具有临界电压Vp1的第四栅极结构；第二p型沟道场效晶体管，包含具有临界电压Vp2的第五栅极结构；以及第三p型沟道场效晶体管，包含具有临界电压Vp3的第六栅极结构。Vn1<Vn2<Vn3且p1<Vp2<Vp3。第一栅极结构包含第一功函数调整材料层，第二栅极结构包含第二功函数调整材料层，第三栅极结构包含第三功函数调整材料层，第四栅极结构包含第四功函数调整材料层，第五栅极结构包含第五功函数调整材料层，且第六栅极结构包含第六功函数调整材料层。第一功函数调整材料层、第二功函数调整材料层、第三功函数调整材料层、第四功函数调整材料层、第五功函数调整材料层、与第六功函数调整材料层的厚度与材料中至少一者彼此不同。
在一些其他实施例中，该第一功函数调整材料层包含第一材料组成的第一层；以及该第二功函数调整材料层、该第三功函数调整材料层、该第四功函数调整材料层、该第五功函数调整材料层、与该第六功函数调整材料层各自包含第一材料组成的第一层，与第二材料组成的第二层，其中第一层位于第二层上，且第一材料不同于第二材料。
在一些其他实施例中，该第二功函数调整材料层、该第三功函数调整材料层、该第四功函数调整材料层、该第五功函数调整材料层、与该第六功函数调整材料层的第二层的厚度依序增加。
在一些其他实施例中，该第二材料为TiN。
在一些其他实施例中，该第一功函数调整材料层、该第二功函数调整材料层、该第三功函数调整材料层、该第四功函数调整材料层、该第五功函数调整材料层、与该第六功函数调整材料层各自形成于第一导电层上，且第一导电层位于栅极介电层上，第三导电层位于每一该第一功函数调整材料层、该第二功函数调整材料层、该第三功函数调整材料层、该第四功函数调整材料层、该第五功函数调整材料层、与该第六功函数调整材料层上，以及第二导电层位于第三导电层上。
依据本公开又一实施例，用于半导体装置中多个场效晶体管的栅极结构的形成方法包括：形成栅极介电层于用于多个场效晶体管的每一沟道层上。形成第一导电层于栅极介电层上。形成功函数调整材料层于第一导电层上。形成第二导电层于功函数调整材料层上。形成功函数调整材料层以用于至少一场效晶体管的步骤包含：形成一或多个导电层并蚀刻一或多个导电层，以露出第一导电层的第一步骤；以及形成导电层且不蚀刻导电层的第二步骤。
在一些其他实施例中，该些场效晶体管包含一第一n型沟道场效晶体管、一第二n型沟道场效晶体管、与一第三n型沟道场效晶体管，形成该功函数调整材料以用于第一n型沟道场效晶体管的步骤包含三个第一步骤，以及形成该功函数调整材料以用于第二n型沟道场效晶体管与第三n型沟道场效晶体管的步骤包含两个第一步骤。
在一些其他实施例中，该些场效晶体管还包括一第一p型沟道场效晶体管、一第二p型沟道场效晶体管、与一第三p型沟道场效晶体管，形成该功函数调整材料以用于第一p型沟道场效晶体管与第二p型沟道场效晶体管的步骤包含一个第一步骤；以及形成该功函数调整材料以用于第三p型沟道场效晶体管的步骤未包含第一步骤。
在一些其他实施例中，该些场效晶体管包含一第一第一型沟道场效晶体管、一第二第一型沟道场效晶体管、与一第三第一型沟道场效晶体管，形成该功函数调整材料以用于第一第一型沟道场效晶体管的步骤包含两个第一步骤；形成该功函数调整材料以用于第二第一型沟道场效晶体管的步骤包含一个第一步骤；以及形成该功函数调整材料以用于第三第一型沟道场效晶体管的步骤不含第一步骤。
上述实施例的特征有利于本领域技术人员理解本公开。本领域技术人员应理解可采用本公开作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本领域技术人员亦应理解，这些等效置换并未脱离本公开精神与范畴，并可在未脱离本公开的精神与范畴的前提下进行改变、替换、或更动。

Claims (10)

1.一种半导体装置，包括：
第一型沟道场效晶体管，包含具有第一栅极结构的一第一第一型沟道场效晶体管，以及具有第二栅极结构的一第二第一型沟道场效晶体管，其中：
该第一第一型沟道场效晶体管的临界电压小于该第二第一型沟道场效晶体管的临界电压，
该第一栅极结构包含一第一功函数调整材料层，且该第二栅极结构包含一第二功函数调整材料层，以及
该第一功函数调整材料层与该第二功函数调整材料层的厚度与材料中至少一者彼此不同。
2.如权利要求1所述的半导体装置，其中：
该第一型沟道场效晶体管还包括具有第三栅极结构的一第三第一型沟道场效晶体管，其中
该第三第一型沟道场效晶体管的临界电压大于第二第一型沟道场效晶体管的临界电压，
该第三栅极结构包含一第三功函数调整材料层，以及
该第一功函数调整材料层、该第二功函数调整材料层、与该第三功函数调整材料层的厚度与材料中至少一者彼此不同。
3.如权利要求2所述的半导体装置，其中：
该第一功函数调整材料层包含第一材料组成的第一层；
该第二功函数调整材料层与该第三功函数调整材料层各自包含第一材料组成的第一层，以及第二材料组成的第二层位于第一层上，其中第一材料不同于第二材料。
4.如权利要求3所述的半导体装置，其中该第二功函数调整材料层的第二层的厚度，小于该第三功函数调整材料层的第二层的厚度。
5.如权利要求2所述的半导体装置，其中该第一功函数调整材料层、该第二功函数调整材料层、与该第三功函数调整材料层各自形成于第一导电层上，且第一导电层位于栅极介电层上。
6.一种半导体装置，包括：
一第一n型沟道场效晶体管，包含具有临界电压Vn1的一第一栅极结构；
一第二n型沟道场效晶体管，包含具有临界电压Vn2的一第二栅极结构；
一第三n型沟道场效晶体管，包含具有临界电压Vn3的一第三栅极结构；
一第一p型沟道场效晶体管，包含具有临界电压Vp1的一第四栅极结构；
一第二p型沟道场效晶体管，包含具有临界电压Vp2的一第五栅极结构；以及
一第三p型沟道场效晶体管，包含具有临界电压Vp3的一第六栅极结构，
其中：
Vn1<Vn2<Vn3且Vp1<Vp2<Vp3，
该第一栅极结构包含一第一功函数调整材料层，该第二栅极结构包含一第二功函数调整材料层，该第三栅极结构包含一第三功函数调整材料层，该第四栅极结构包含一第四功函数调整材料层，该第五栅极结构包含一第五功函数调整材料层，且该第六栅极结构包含一第六功函数调整材料层，以及
该第一功函数调整材料层、该第二功函数调整材料层、该第三功函数调整材料层、该第四功函数调整材料层、该第五功函数调整材料层、与该第六功函数调整材料层的厚度与材料中至少一者彼此不同。
7.如权利要求6所述的半导体装置，其中：
该第一功函数调整材料层包含第一材料组成的第一层；以及
该第二功函数调整材料层、该第三功函数调整材料层、该第四功函数调整材料层、该第五功函数调整材料层、与该第六功函数调整材料层各自包含第一材料组成的第一层，与第二材料组成的第二层，其中第一层位于第二层上，且第一材料不同于第二材料。
8.一种用于半导体装置中多个场效晶体管的栅极结构的形成方法，包括：
形成一栅极介电层于用于多个场效晶体管的每一沟道层上；
形成一第一导电层于该栅极介电层上；
形成一功函数调整材料层于该第一导电层上；以及
形成一第二导电层于该功函数调整材料层上，其中：
形成该功函数调整材料层以用于至少一场效晶体管的步骤包含：
形成一或多个导电层并蚀刻一或多个导电层，以露出该第一导电层的第一步骤；以及
形成一导电层且不蚀刻该导电层的第二步骤。
9.如权利要求8所述的用于半导体装置中多个场效晶体管的栅极结构的形成方法，其中：
所述多个场效晶体管包含一第一n型沟道场效晶体管、一第二n型沟道场效晶体管、与一第三n型沟道场效晶体管，
形成该功函数调整材料以用于第一n型沟道场效晶体管的步骤包含三个第一步骤，以及
形成该功函数调整材料以用于第二n型沟道场效晶体管与第三n型沟道场效晶体管的步骤包含两个第一步骤。
10.如权利要求9所述的用于半导体装置中多个场效晶体管的栅极结构的形成方法，其中：
所述多个场效晶体管还包括一第一p型沟道场效晶体管、一第二p型沟道场效晶体管、与一第三p型沟道场效晶体管，
形成该功函数调整材料以用于第一p型沟道场效晶体管与第二p型沟道场效晶体管的步骤包含一个第一步骤；以及
形成该功函数调整材料以用于第三p型沟道场效晶体管的步骤未包含第一步骤。
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