CN104867824A - 具有变化栅极结构的集成电路及其制法 - Google Patents
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Abstract
本发明提供一种具有变化栅极结构的集成电路及其制法。该集成电路包括:设于衬底结构上方的变化栅极结构,该变化栅极结构包括位于该衬底结构的第一区域中的第一栅极堆叠,以及位于该衬底结构的第二区域中的第二栅极堆叠;位于该第一区域中的第一场效应晶体管,该第一场效应晶体管包括该第一栅极堆叠并具有第一阈值电压;以及位于该第二区域中的第二场效应晶体管,该第二场效应晶体管包括该第二栅极堆叠并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。该方法包括设置该变化栅极结构,该设置包括:设定该变化栅极结构的层的尺寸,使其在不同区域中具有不同厚度。
Description
技术领域
本发明涉及半导体装置以及制造半导体装置的方法,尤其涉及集成电路以及制造具有变化栅极结构的集成电路的方法。
背景技术
不同的半导体装置可经制造而具有一个或多个不同的装置特征,例如阈值电压、开关速度、泄露功耗等。针对意图执行特定功能的装置,多种不同的设计可分别优化这些特征的其中一个或多个。例如,对于提供计算逻辑功能的装置,一种设计可具有降低的阈值电压以增加开关速度,而对于提供内存存储功能的装置,另一种设计可具有增加的阈值电压以降低功耗。使用针对不同功能分别优化的多个分立装置的系统将导致系统复杂性更高、系统占用面积增大以及系统成本增加。
发明内容
为克服现有技术的缺点并提供额外的优点,在一个态样中提供一种集成电路。该集成电路包括:设于衬底结构上方的变化栅极结构,该变化栅极结构具有位于该衬底结构的第一区域中的第一栅极堆叠,以及位于该衬底结构的第二区域中的第二栅极堆叠;位于该衬底结构的该第一区域中的第一场效应晶体管,该第一场效应晶体管包括该变化栅极结构的该第一栅极堆叠并具有第一阈值电压;以及位于该衬底结构的该第二区域中的第二场效应晶体管,该第二场效应晶体管包括该变化栅极结构的该第二栅极堆叠并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。
在另一个态样中,这里提供一种制造集成电路的方法。该方法包括设置变化栅极结构,该变化栅极结构设于衬底结构上方,该变化栅极结构具有位于该衬底结构的第一区域中的第一栅极堆叠以及位于该衬底结构的第二区域中的第二栅极堆叠,且该设置包括:设定该变化栅极结构的一层的尺寸,使其在该衬底结构的该第一区域中具有第一厚度并在该衬底结构的该第二区域中具有第二厚度;以及设定该变化栅极结构的另一层的尺寸,使其在该衬底结构的该第一区域中具有第三厚度并在该衬底结构的该第二区域中具有第四厚度,其中,该第一厚度不同于该第二厚度,且该第三厚度不同于该第四厚度。
通过本发明的技术实现额外的特征及优点。这里详细说明本发明的其它实施例及态样,作为请求保护的本发明的一部分。
附图说明
本发明的一个或多个态样被特别指出并在说明书的结束处的声明中被明确称为示例。结合附图参照下面的详细说明可清楚本发明的上述及其它目的、特征以及优点,其中:
图1A显示依据本发明的一个或多个态样在电路制造期间所获得的中间电路结构的一个实施例的平面视图以及设于衬底结构上方的变化栅极结构;
图1B显示依据本发明的一个或多个态样的集成电路的一个实施例的立体图;
图2A及2B显示依据本发明的一个或多个态样的图1A的结构的剖视图,并显示该变化栅极结构具有第一及第二栅极堆叠;
图3显示依据本发明的一个或多个态样在该衬底结构的第一区域上方设置保护掩膜以后图2A及2B的结构;
图4A及4B显示依据本发明的一个或多个态样从该衬底结构的第二区域至少部分地移除材料以后图3的结构;
图5A及5B显示依据本发明的一个或多个态样设定该变化栅极结构的一层的尺寸以后图4A及4B的结构;
图6A及6B显示依据本发明的一个或多个态样在该衬底结构上方至少部分地沉积另一层的另一材料以后图5A及5B的结构;
图7显示依据本发明的一个或多个态样在该衬底结构的该第二区域上方设置保护掩膜以后图6A及6B的结构;
图8A及8B显示依据本发明的一个或多个态样从该衬底结构的该第一区域至少部分地移除该另一材料以后图7的结构;
图9A及9B显示依据本发明的一个或多个态样设定该变化栅极结构的该另一层的尺寸以后图8A及8B的结构;
图10显示依据本发明的一个或多个态样在该衬底结构的第三区域上方设置保护掩膜以后图9A及9B的结构;
图11A显示依据本发明的一个或多个态样斜切该衬底结构的第四区域中的该变化栅极结构的该另一层以后图10的结构;
图11B显示依据本发明的一个或多个态样设定该衬底结构的第三区域中的该变化栅极结构的该另一层的尺寸以后图10的结构;
图12A及12B显示依据本发明的一个或多个态样在该衬底结构上方设置另一层以后图11A及11B的结构;以及
图13A及13B显示依据本发明的一个或多个态样使用另一材料填充该变化栅极结构以后图12A及12B的结构。
具体实施方式
通过参照附图中所示的非限制例子来更加充分地解释本发明的态样及其特定的特征、优点以及细节。省略对已知材料、制造工具、制程技术等的说明,以免在细节上不必要地模糊本发明。不过,应当理解,用以说明本发明态样的详细说明及具体例子仅作为示例,而非限制。本领域的技术人员将会从本揭露中了解在基础的发明概念的精神和/或范围内的各种替代、修改、添加和/或布局。
本揭露部分提供集成电路,包括具有变化栅极结构以及多个不同的阈值电压的场效应晶体管(field-effect transistor;FET)。在集成电路制造期间,可能想要通过单个制程在集成电路的整个衬底的所选区域上方设置一个或多个栅极结构来形成众多FET的众多栅极。例如,在整个衬底的所选区域上方可设置具有一致的材料层堆叠的层状栅极结构,以形成众多FET的众多栅极。这里所使用的变化栅极结构是指在集成电路的不同区域中具有多个不同的层堆叠或者多个不同的栅极堆叠的栅极结构,这些不同的层堆叠或不同的栅极堆叠可具有不同组成或尺寸。在一个例子中,这样一个变化栅极结构可在相同或不同区域中具有不同厚度的不同材料层。在另一例子中,这样一个变化栅极结构可在不同区域中具有不同数量的材料层。通过使用这里所述的变化栅极结构,在单个制程中可形成具有不同栅极堆叠的众多栅极。
在一个FET中,阈值电压是使电流能够从源极经该FET的沟道流至漏极所需的最小栅极电压。一般来说,在控制其它因素的情况下,具有较低阈值电压的FET比具有较高阈值电压的FET运行更快,但消耗更多泄露功率。
当设计用于例如手机或媒体播放器的特定应用的集成电路(其包括例如片上系统)时,可能想要通过以具有不同阈值电压的FET实施的集成电路的不同部分来最优化该集成电路的泄露功耗以及速度。例如,可能想要以较高的速度执行逻辑或算术功能以支持高级特征,而以较低的速度执行内存存储以节约功率。在另一个例子中,甚至在集成电路的单个逻辑子系统中,可能想要最优化特定FET的速度并最优化其它FET的功耗。
另外,由于目前的集成电路设计依赖于使用n型FET(NFET)及p型FET(PFET)的互补金属氧化物半导体(complementary metal oxidesemiconductor;CMOS)技术,因此想要获得结合NFET及PFET与多个阈值电压的集成电路。
一般来说,在一个态样中,这里提供一种集成电路。该集成电路包括:设于衬底结构上方的变化栅极结构,该变化栅极结构具有位于该衬底结构的第一区域中的第一栅极堆叠,以及位于该衬底结构的第二区域中的第二栅极堆叠;位于该衬底结构的该第一区域中的第一场效应晶体管,该第一场效应晶体管包括该变化栅极结构的该第一栅极堆叠并具有第一阈值电压;以及位于该衬底结构的该第二区域中的第二场效应晶体管,该第二场效应晶体管包括该变化栅极结构的该第二栅极堆叠并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。在一个实施例中,该变化栅极结构的部分自该第一场效应晶体管延伸至该第二场效应晶体管。在另一个例子中,该第一阈值电压可介于超出该第二阈值电压80至120毫伏之间。在又一个例子中,该变化栅极结构的一层包括功函数层,该变化栅极结构的另一层包括覆盖层,且该变化栅极结构还包括设于该覆盖层下方的栅极介电层。
在一个实施例中,该变化栅极结构可包括一层及另一层,该一层在该衬底结构的该第一区域中具有第一厚度并在该衬底结构的该第二区域中具有第二厚度,且该另一层在该衬底结构的该第一区域中具有第三厚度并在该衬底结构的该第二区域中具有第四厚度,其中,该第一厚度不同于该第二厚度,且该第三厚度不同于该第四厚度。在这样一种情况下,该第一厚度小于该第二厚度,且该第三厚度大于该第四厚度。
在另一个实施例中,该衬底结构可包括在该衬底结构的该第一区域上方延伸的第一鳍片以及在该衬底结构的该第二区域上方延伸的第二鳍片,且该变化栅极结构可共形设于该第一鳍片及该第二鳍片上方。在这样一种情况下,该第一鳍片与该第二鳍片可为同一鳍片。
这里还提供一种制造集成电路的方法。该方法包括设置变化栅极结构,该变化栅极结构设于衬底结构上方,该变化栅极结构具有位于该衬底结构的第一区域中的第一栅极堆叠以及位于该衬底结构的第二区域中的第二栅极堆叠,且该设置包括:设定该变化栅极结构的一层的尺寸,使其在该衬底结构的该第一区域中具有第一厚度并在该衬底结构的该第二区域中具有第二厚度;以及设定该变化栅极结构的另一层的尺寸,使其在该衬底结构的该第一区域中具有第三厚度并在该衬底结构的该第二区域中具有第四厚度,其中,该第一厚度不同于该第二厚度,且该第三厚度不同于该第四厚度。
在一个例子中,该集成电路包括位于该衬底结构的该第一区域中的第一场效应晶体管,以及位于该衬底结构的该第二区域中的第二场效应晶体管,该第一场效应晶体管包括该第一栅极堆叠并具有第一阈值电压,且该第二场效应晶体管包括该第二栅极堆叠并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。在另一个实施例中,该衬底结构的第三区域包括该第一区域的一部分以及该第二区域的另一部分,且该设置还包括,在设定该变化栅极结构的该一层的尺寸以后,重新设定位于该衬底结构的该第三区域中的该一层的尺寸,使其具有第五厚度。
在一个实施例中,设定该变化栅极结构的该一层的尺寸可包括:在该衬底结构的该第一区域及该第二区域上方至少部分地沉积该一层的材料;从该衬底结构的该第一区域至少部分地移除该材料;以及在该衬底结构的该第一区域及该第二区域上方至少部分地再次沉积该材料,以在该第一区域中形成该一层的该第一厚度,并在该第二区域中形成该一层的该第二厚度。
在另一个实施例中,该衬底结构包括在该衬底结构的该第一区域及该第二区域上方延伸的一个或多个鳍片,且设置该变化栅极结构包括在该一个或多个鳍片上方共形设置该变化栅极结构。在这样一种情况下,该集成电路可包括位于该衬底结构的该第一区域中的第一场效应晶体管以及位于该衬底结构的该第二区域中的第二场效应晶体管,该第一场效应晶体管包括该第一栅极堆叠以及该一个或多个鳍片中的第一鳍片,并具有第一阈值电压,且该第二场效应晶体管包括该第二栅极堆叠以及该一个或多个鳍片中的第二鳍片,并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。
下面参照附图。为方便理解,这些附图并非按比例绘制。其中,不同附图中所使用的相同附图标记表示相同或类似的组件。
图1A显示依据本发明的一个或多个态样在电路制造期间所获得的中间电路结构100的一个实施例。在一个例子中,如图所示,栅极结构120设于衬底结构上方。如图所示,在一个例子中,该衬底结构可包括衬底102以及一个或多个鳍片110,以支持鳍式场效应晶体管(FinFET)以及平面FET的形成。
栅极结构120可共形延伸于一个或多个鳍片110上方(并部分包覆该一个或多个鳍片)。在一个例子中,可采用替代栅极制程,其中,可在电路制造的早期阶段设置由适当材料例如多晶硅构成的牺牲栅极,接着将该牺牲栅极移除并由最终的栅极结构替代。在另一个例子中,可直接形成该栅极结构而不使用牺牲栅极。在上述的任意一种栅极制程中,该栅极结构都可在形成场效应晶体管的源区及漏区以前(先栅极)或以后(后栅极)形成,取决于所选择的流程。
衬底102(在一个例子中)可为块体半导体材料,例如块体硅晶圆。在另一个例子中,衬底102可为或包括任意含硅衬底,其包括但不限于单晶硅、多晶硅、非晶硅、悬空硅(Si-on-nothing;SON)、绝缘体上硅(Si-on-insulator;SOI)或替代绝缘体上硅(Si-on-replacementinsulator;SRI)衬底等,且可针对特定应用而经n型掺杂或p型掺杂。在一个例子中,衬底102可为例如约600至700微米厚或更薄的晶圆或衬底。
鳍片110可自衬底102延伸,且可包括位于第一区域131中的一个或多个鳍片以及位于第二区域132中的一个或多个鳍片。例如,为形成鳍片,可移除衬底的一个或多个部分,从而形成材料与衬底相同(例如半导体或结晶材料)的鳍片。在一个例子中,鳍片的形成可通过使用任意各种方法图案化衬底来实现,包括:直接光刻;侧壁图像转移技术;极紫外光刻(extreme ultraviolet lithography;EUV);电子束技术;光刻-蚀刻光刻-蚀刻;或光刻-蚀刻光刻-冻结。图案化以后可执行材料移除,例如通过任意合适的蚀刻制程,例如非等向性干式蚀刻制程,例如六氟化硫(SF6)中的反应离子蚀刻(reactive-ion-etching;RIE)所执行。尽管下述数字是相对的且高度可变化,但作为一个具体例子,鳍片可具有约40纳米的高度以及约1微米、几微米或整个晶圆的直径的长度,且鳍片的厚度可为约10纳米或更小。在另一个例子中,鳍片可形成于衬底上,且鳍片与衬底可为不同材料。
请参照图1B,其显示具有两个场效应晶体管(FET)的集成电路100’的一个实施例,以提供有关本发明的总体环境。如图所示,栅极结构120’的部分可自区域133中的第一FET延伸至区域134中的第二FET,且每个FET可包括两个鳍片110。在一个典型的集成电路中,数千个、数百万个或更多的FET可互连。在互补金属氧化物半导体(CMOS)技术中,例如通过共用共同的栅极结构或者可通过金属接触(未图示)连接,n型FET(NFET)可与p型FET(PFET)互连。各FET可包括例如任意数目的鳍片,取决于想要的电路设计,因为具有更多的鳍片可使FET能够从源极112向漏极114传输更大的电流。例如,如图所示的各FET具有两个鳍片。在给定的集成电路中,可具有各种FET,这些FET具有数目变化的鳍片分布于该集成电路中。
出于上述原因,可能想要使集成电路的不同FET具有不同的阈值电压。这里所揭露的在不同区域中具有不同栅极堆叠的变化栅极结构允许针对那些不同区域中的FET选择不同的阈值电压。另外,由于NFET与PFET的不同电性特征,因此该变化栅极结构允许针对NFET及PFET选择相同或相似的阈值电压,该NFET及PFET包括通过该变化栅极结构的部分直接连接的NFET及PFET。在一些情况中,可能要求6个或更多不同的阈值电压。例如,CMOS集成电路可能需要一对常规阈值电压、一对低阈值电压以及一对超低阈值电压,每一对为各NFET及PFET提供阈值电压。
栅极结构120’可例如通过使用这里所揭露的技术形成,且可在区域133中具有一个栅极堆叠并在区域134中具有一个不同的栅极堆叠,从而允许针对那些不同区域中的FET选择不同的阈值电压。在另一个例子中,在区域133及区域134中具有不同栅极堆叠的变化栅极结构允许针对区域133中的NFET以及区域134中的PFET选择相同(或相似)的阈值电压。
图2A显示图1A的结构沿图1A中的线2A-2A的剖视图以及在鳍片110上方延伸的变化栅极结构120。如图所示,在这个例子中,栅极结构120处于制造的中间阶段。通过例如包含经沉积以形成各层的材料,间隙壁112可帮助多个层的形成。在一个例子中,栅极结构可包括介电层122、覆盖层124以及另一覆盖层126。另外要注意的是,在衬底与介电层122之间可设置界面层121。
通过使用一系列可保护衬底结构的一些区域并暴露衬底结构的区域的保护掩膜,可形成变化栅极结构,而非一致的栅极结构,该变化栅极结构具有多个不同的栅极堆叠,例如在多个不同区域中具有变化厚度的材料层,从而支持具有多个不同的阈值电压的FET。由于FET的阈值电压受位于FET的沟道与向栅极施加栅极电压的栅极接触之间的栅极的电性属性影响,因此该变化栅极结构可支持多个不同的阈值电压。通过设定该变化栅极结构的尺寸或调节该变化栅极结构以使其在不同区域中具有不同的栅极堆叠,可获得不同的阈值电压,因为在FET中,阈值电压与栅极电压如何影响位于栅极下方的沟道中的载流子的行为直接相关。
在一个例子中,介电层122可为包括硅的材料,例如二氧化硅或氮氧化硅。在另一个例子中,介电层122可为介电常数大于例如约3.9(二氧化硅的介电常数)的高介电常数(高k)材料,包括但不限于氧化铪、氧化钽、氧化锆、氧化钛或氧化铝的其中一种或多种。在一个具体例子中,介电层122可为具有约15埃()的厚度的高k材料。界面层121可帮助介电层122的形成,且可为例如下方衬底的化学氧化物,例如二氧化硅,其具有约的厚度。
可包括覆盖层124以在各种制程步骤期间保护介电层122免受损伤。在一个例子中,覆盖层124可为或包括氮化钛(TiN)或氮化钽(TaN),且可具有约在与之间的厚度,以及在一个具体例子中,可为具有的厚度的TiN层。
各介电层122、覆盖层124以及覆盖层126可使用任意各种沉积制程来沉积,包括例如物理气相沉积(physical vapor deposition;PVD)、原子层沉积(atomic layer deposition;ALD)、化学气相沉积(chemicalvapor desposition;CVD)、溅镀或其它制程,取决于该层的材料组成。该沉积可顺应衬底结构,包括包覆鳍片110。
图2B显示图1的结构沿图1的线2B-2B的剖视图。在这里所揭露的制造方法的一个实施例中,在如图2A及2B所示的制造阶段,栅极结构120可包括在第一区域131及第二区域132中具有相似尺寸的相似层。在另一个例子中,这些层的尺寸及组成可在如图所示的这个制造阶段已经变化。
图3至5B显示用以设定栅极结构120的一层的尺寸的制程的一个实施例。在这组例子中,栅极结构120的覆盖层可经尺寸设定而在衬底结构的不同区域中具有不同的厚度。通常,覆盖层可用以保护下方的介电层,且其通常不被视为会影响阈值电压。不过,如这里所揭露的那样,改变覆盖层的尺寸可改变该变化栅极结构的其它层的位置,从而改变该变化栅极结构的电性属性。层中的这样一个位置改变以及电性属性的改变可导致不同的阈值电压。
在如图3至5B所示的制程中,使用加成及减成制程来设定覆盖层的尺寸。这样一个制程可能优于仅加成的制程,因为用于向覆盖层添加材料的沉积制程可能与所需的掩膜技术不兼容。不过,如果可使用适当的掩膜技术,则可使用仅加成的制程来设定覆盖层的尺寸。
图3显示在图2A及2B的结构在衬底结构的第一区域131上方设置保护掩膜141并暴露第二区域132之後的结构,其中该第二区域132被暴露以用於执行进一步参照图4A及4B进行揭露的制程步骤。保护掩膜141可设于整个电路结构100的上方,接着使用标准光刻制程进行图案化,以暴露第二区域132并保护第一区域131。图3显示较大的集成电路的一部分,且第一区域131可为不连续的区域,其具有被保护掩膜141保护的众多部分,取决于正在制造的具体集成电路。
在一个例子中,保护掩膜141可包括例如氮化硅、氧化硅或氮氧化硅等材料,并可使用传统的沉积制程沉积,例如CVD或等离子增强型CVD(plasma-enhanced CVD;PECVD)。在其它例子中,依据电路100中所使用的材料可使用其它掩膜材料。例如,保护掩膜141可为或包括有机材料。例如,通过流动式化学气相沉积(flowable chemicalvapor desposition;F-CVD)可沉积可流动氧化物,例如氢倍半硅氧烷聚合物或无碳倍半硅氧烷聚合物。在另一个例子中,保护掩膜141可为或包括有机聚合物,例如聚丙烯酸酯树脂、环氧树脂、酚醛树脂、聚酰胺树脂、聚酰亚胺树脂、不饱和聚酯树脂、聚苯醚树脂、聚苯硫醚树脂或苯并环丁烯(BCB)。
图4A显示图3的结构沿图3的线4A-4A的剖视图,且图4B显示图3的结构沿图3的线4B-4B的剖视图。如图所示,在一个例子中,设定覆盖层126的尺寸的制程包括自衬底结构的第二区域132移除覆盖层126的材料,并保持第一区域131中的覆盖层126不变。在另一个例子中,可部分移除材料,以降低第二区域132中的覆盖层126的厚度。
移除覆盖层126可通过任意适当的蚀刻制程实现,例如干式或湿式蚀刻制程。在一个例子中,通过例如离子束蚀刻、等离子蚀刻或等向性RIE,可使用等向性干式蚀刻。在另一个例子中,通过使用对覆盖层126的材料具有选择性的蚀刻溶液,也可执行等向性湿式蚀刻。保护掩膜141确保在这样的移除制程期间不会自第一区域131移除覆盖层126的材料。
图5A及5B显示图4A及4B的结构在移除该保护掩膜并在衬底结构的第一区域131及第二区域132上方沉积覆盖层126的材料以后的结构。在一个例子中,如图所示,沉积该材料使覆盖层126在第一区域131中具有第一厚度T1,并在第二区域132中具有第二厚度T2。如图所示,T1可大于T2;但在另一个例子中,T2可大于T1。该材料可通过各种沉积制程而沉积,包括例如物理气相沉积(PVD)、原子层沉积(ALD)或化学气相沉积(CVD)。例如,覆盖层126可为或包括TiN或TaN,并具有介于与之间的厚度。在一个具体例子中,覆盖层126可为TaN,并在第一区域131中具有介于与之间的厚度T1,且在第二区域132中具有的厚度T2。
移除该保护掩膜可通过使用任意适当的制程实现,例如化学-机械抛光(chemical-mechanical polishing;CMP)或蚀刻,取决于该保护掩膜的化学性质。
图6A至9B显示设定(或改变)栅极结构120的另一层的尺寸的例子。在这些例子中,变化栅极结构120的功函数层可经尺寸设定以在衬底结构的不同区域中具有不同的厚度,从而在这些不同区域中实现不同的栅极堆叠。对于一导体,功函数是描述自该导体移除电子所需的最小能量的电性属性。因此,栅极结构的功函数层是直接影响阈值电压的材料层,因为它影响电子从栅极堆叠流向栅极接触所需的能量大小,从而影响可用于吸引栅极下方的沟道中的载流子的能量大小。另外,设定覆盖层的尺寸的上述制程可影响随后形成的功函数层相对于下方沟道的垂直位置。这些不同因素一起作用以形成定义不同阈值电压的变化栅极结构。
图6A及6B显示在第一区域131及第二区域132上方沉积功函数层128的材料以后图5A及5B的结构。功函数层128的材料可通过使用参照图5A及5B所述的用以沉积覆盖层126的任意沉积制程形成。
功函数层128可为或包括金属及其氮化物,例如氮化钛(TiN)、氮化钽(TaN)、氮化钛铝(TiAlN)、氮化钽铝(TaAlN)、氮化铌(NbN)、氮化钒(VN)、氮化钨(WN)。在另一个例子中,功函数层128可为或包括金属及其碳化物,例如碳化钛(TiC)、碳化钛铝(TiAlC)、铝化钛(TiAl)、碳化钽(TaC)、碳化钽铝(TaAlC)、碳化铌(NbC)、碳化钒(VC)等。在另一个例子中,功函数层128也可包括钌(Ru)、铂(Pt)、钼(Mo)、钴(Co)及其合金及组合。
图7显示图6A及6B的结构在衬底结构的第二区域131上方设置另一个保护掩膜142并暴露第一区域131後的结构,其中该第一区域131被暴露以执行进一步参照图8A及8B进行揭露的制程步骤。保护掩膜142可具有前面参照图3的保护掩膜所述的任意属性。
图8A显示图7的结构沿图7的线8A-8A的剖视图,图8B显示图7的结构沿图7的线8B-8B的剖视图。如图所示,在一个例子中,设定功函数层128的尺寸的制程包括自衬底结构的第一区域132移除功函数层128的材料。在另一个例子中,可部分移除该材料,以降低第一区域131中的功函数层128的厚度。移除功函数层128可通过使用参照图4A及4B所述的用以移除覆盖层126的任意移除制程实现。
图9A及9B显示图8A及8B的结构在移除该另一保护掩膜并在第一区域131及第二区域132上方沉积功函数层128的材料以后的结构。在一个例子中,如图所示,沉积该材料在第一区域131中形成功函数层128的第一厚度T’1,在第二区域132中形成第二厚度T’2。如图所示,T’2可大于T’1,但在另一个例子中,T’1可大于T’2。沉积功函数层128的材料可通过使用前面参照图6A及6B所述的技术实现。
例如,功函数层128可为或包括TiN或TiC,且可具有约在与之间的厚度。在一个具体例子中,功函数层128可为TiN层,其可在第二区域132中具有约的厚度T’2,且在第一区域中具有约的厚度T’1。在这样一个例子中,与经尺寸设定的覆盖层126一起,第一栅极堆叠可定义约0.35V的第一区域131中的FET的第一阈值电压以及约0.25V的第二区域132中的另一FET的第二阈值电压,它们之间的差别介于80至120毫伏之间。
图10显示图9A及9B的结构在衬底结构的第三区域133上方设置另一保护掩膜143并暴露衬底结构的第四区域134之後的结构,其中该衬底结构的第四区域134被暴露以执行进一步参照图11A进行揭露的制程步骤。如图所示,第三区域133及第四区域134各自重叠第一区域131及第二区域132。在一个例子中,变化栅极结构120可在第三区域133中具有一栅极堆叠以为PFET提供阈值电压,并在第四区域134中具有另一栅极堆叠以为NFET提供不同的阈值电压。通过使用保护掩膜以及重叠区域,变化栅极结构120可在众多区域中具有厚度不同的不同层,从而允许定义电路设计所需的任意数目的阈值电压。
图11A显示图10的结构在斜切衬底结构的第四区域中的功函数层128以后的结构。可选择性地斜切功函数层128,以移除尖角,从而方便后续制程步骤,因为栅极结构120的狭窄开口使沉积其它材料变得困难。斜切可通过任意适当的蚀刻制程实现,例如等向性蚀刻。
图11B显示图10的结构在移除衬底结构的第三区域中的功函数层以后的结构。为移除该功函数层,可在衬底结构的第四区域上方设置保护掩膜,并可以先前参照图7至8B所述的类似方式采用移除制程。在另一个例子中,仅该功函数层的部分被移除。
图12A及12B显示图11A及11B的结构在衬底结构上方设置另一层129以后的结构。在一个例子中,另一层129可为功函数层,且可为与功函数层128相同或不同的材料。通过使用前面所述的技术,可设定另一层129的尺寸,使其在衬底结构的不同区域中具有不同的厚度。
图13A及13B显示图12A及12B的结构在沉积包覆层130’并使用材料130填充变化栅极结构120以后的结构。在一个例子中,材料130可为任意适当的材料,包括金属,例如钨(W)。包覆层130’可用以保护下方的栅极堆叠免受机械损伤或材料130的扩散影响,且在一个具体例子中,包覆层130’可为具有的厚度的TiN。由于变化栅极结构120变化的总体厚度,可沉积足量的材料130,以完全填充栅极结构120。在使用材料130填充栅极结构120以后,电路结构可经化学机械抛光(CMP)制程以自电路结构的不同部分移除额外的栅极堆叠材料。
如图所示,变化栅极结构120可具有不同的材料层,其包括功函数及覆盖层,它们在衬底结构的不同区域中具有不同的尺寸。总之,图13A及13B显示变化栅极结构120的四个不同的栅极堆叠,其具有四种不同的尺寸形状,以允许四个不同的阈值电压。很容易理解,通过应用这里所揭露的技术,可在额外的区域中调整变化栅极结构120,以形成额外的不同栅极堆叠,以及由此形成的不同的阈值电压,包括例如针对NFET及PFET的额外的不同阈值电压对。
另外,在特定情况下,在电路结构的部分中,例如栅极结构下方的沟道区或所述各层中,可能想要通过注入掺杂例如n型或p型掺杂物进一步调整通过使用这里所述的变化栅极结构所获得的阈值电压。此类调整可通过利用各种材料的电路结构的等离子掺杂或离子注入实现。
这里所使用的术语仅是出于说明特定例子的目的,并非意图限制本发明。除非上下文中明确指出,否则这里所使用的单数形式“一个”以及“该”也意图包括复数形式。还应当理解,术语“包括”(以及任意形式的包括)、“具有”(以及任意形式的具有)以及“包含”(任意形式的包含)都是开放式连接动词。因此,“包括”、“具有”或“包含”一个或多个步骤或元件的方法或装置具有那些一个或多个步骤或元件,但并不限于仅仅具有那些一个或多个步骤或元件。类似地,“包括”、“具有”或“包含”一个或多个特征的一种方法的步骤或一种装置的元件具有那些一个或多个特征,但并不限于仅仅具有那些一个或多个特征。而且,以特定方式配置的装置或结构至少是以这种方式配置,但也可以未列出的方式配置。
本发明的权利要求中的所有方式或步骤加功能元素的相应结构、材料、动作及等同(如果有的话)意图包括执行该功能的任意结构、材料或动作结合具体请求保护的其它请求保护的元素。本发明的说明是出于示例及说明目的,并非意图详尽无遗或将本发明限于所揭露的形式。本领域的技术人员很容易了解许多修改及变更,而不背离本发明的范围及精神。实施例经选择并说明以最好地解释本发明的一个或多个态样的原理以及实际应用,并使本领域的技术人员能够理解本发明的一个或多个态样为适应所考虑的特定应用而作出各种修改的各种实施例。
Claims (20)
1.一种装置,包括:
集成电路,该集成电路包括:
变化栅极结构,设于衬底结构上方,该变化栅极结构包括位于该衬底结构的第一区域中的第一栅极堆叠,以及位于该衬底结构的第二区域中的第二栅极堆叠,其中,该第一栅极堆叠不同于该第二栅极堆叠;
第一场效应晶体管,位于该衬底结构的该第一区域中,该第一场效应晶体管包括该变化栅极结构的该第一栅极堆叠并具有第一阈值电压;以及
第二场效应晶体管,位于该衬底结构的该第二区域中,该第二场效应晶体管包括该变化栅极结构的该第二栅极堆叠并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。
2.如权利要求1所述的装置,其中,该变化栅极结构包括一层及另一层,该一层在该衬底结构的该第一区域中具有第一厚度并在该衬底结构的该第二区域中具有第二厚度,且该另一层在该衬底结构的该第一区域中具有第三厚度并在该衬底结构的该第二区域中具有第四厚度,其中,该第一厚度不同于该第二厚度,且该第三厚度不同于该第四厚度。
3.如权利要求2所述的装置,其中,该第一厚度小于该第二厚度,且该第三厚度大于该第四厚度。
4.如权利要求1所述的装置,其中,该变化栅极结构的部分自该第一场效应晶体管延伸至该第二场效应晶体管。
5.如权利要求1所述的装置,其中,该第一阈值电压介于超出该第二阈值电压80至120毫伏之间。
6.如权利要求1所述的装置,其中,该衬底结构包括在该衬底结构的该第一区域上方延伸的第一鳍片以及在该衬底结构的该第二区域上方延伸的第二鳍片,且该变化栅极结构共形设于该第一鳍片及该第二鳍片上方。
7.如权利要求6所述的方法,其中,该变化栅极结构的部分自该第一场效应晶体管延伸至该第二场效应晶体管。
8.如权利要求6所述的装置,其中,该第一鳍片与该第二鳍片是同一鳍片。
9.如权利要求1所述的装置,其中,该变化栅极结构的一层包括功函数层,该变化栅极结构的另一层包括覆盖层,且该变化栅极结构还包括设于该覆盖层下方的栅极介电层。
10.一种方法,包括:
制造集成电路,该制造包括:
设置变化栅极结构,该变化栅极结构设于衬底结构上方,该变化栅极结构包括位于该衬底结构的第一区域中的第一栅极堆叠以及位于该衬底结构的第二区域中的第二栅极堆叠,且该设置包括:
设定该变化栅极结构的一层的尺寸,使其在该衬底结构的该第一区域中具有第一厚度并在该衬底结构的该第二区域中具有第二厚度;以及
设定该变化栅极结构的另一层的尺寸,使其在该衬底结构的该第一区域中具有第三厚度并在该衬底结构的该第二区域中具有第四厚度,其中,该第一厚度不同于该第二厚度,且该第三厚度不同于该第四厚度。
11.如权利要求10所述的方法,其中,该集成电路包括位于该衬底结构的该第一区域中的第一场效应晶体管,以及位于该衬底结构的该第二区域中的第二场效应晶体管,该第一场效应晶体管包括该第一栅极堆叠并具有第一阈值电压,且该第二场效应晶体管包括该第二栅极堆叠并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。
12.如权利要求11所述的方法,其中,该变化栅极结构的部分自该第一场效应晶体管延伸至该第二场效应晶体管。
13.如权利要求10所述的方法,其中,该第一厚度小于该第二厚度,且该第三厚度大于该第四厚度。
14.如权利要求10所述的方法,其中,设定该变化栅极结构的该一层的尺寸包括:
在该衬底结构的该第一区域及该第二区域上方至少部分地沉积该一层的材料;
从该衬底结构的该第一区域至少部分地移除该材料;以及
在该衬底结构的该第一区域及该第二区域上方至少部分地再次沉积该材料,以在该第一区域中形成该一层的该第一厚度,并在该第二区域中形成该一层的该第二厚度。
15.如权利要求10所述的方法,其中,该衬底结构的第三区域包括该第一区域的一部分以及该第二区域的另一部分,且该设置还包括,在设定该变化栅极结构的该一层的尺寸以后,重新设定位于该衬底结构的该第三区域中的该一层的尺寸,使其具有第五厚度。
16.如权利要求10所述的方法,其中,该衬底结构包括在该衬底结构的该第一区域及该第二区域上方延伸的一个或多个鳍片,且设置该变化栅极结构包括在该一个或多个鳍片上方共形设置该变化栅极结构。
17.如权利要求16所述的方法,其中,该集成电路包括位于该衬底结构的该第一区域中的第一场效应晶体管以及位于该衬底结构的该第二区域中的第二场效应晶体管,该第一场效应晶体管包括该第一栅极堆叠以及该一个或多个鳍片中的第一鳍片,并具有第一阈值电压,且该第二场效应晶体管包括该第二栅极堆叠以及该一个或多个鳍片中的第二鳍片,并具有第二阈值电压,其中,该第一阈值电压不同于该第二阈值电压。
18.如权利要求17所述的方法,其中,该变化栅极结构的部分自该第一场效应晶体管延伸至该第二场效应晶体管。
19.如权利要求17所述的方法,其中,该第一鳍片与该第二鳍片是该一个或多个鳍片结构中的同一鳍片。
20.如权利要求10所述的方法,其中,该变化栅极结构的该一层包括功函数层,该变化栅极结构的该另一层包括覆盖层,且该变化栅极结构还包括设于该覆盖层下方的栅极介电层。
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Also Published As
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TW201533854A (zh) | 2015-09-01 |
CN104867824B (zh) | 2020-04-17 |
US20150243658A1 (en) | 2015-08-27 |
TWI591772B (zh) | 2017-07-11 |
US9576952B2 (en) | 2017-02-21 |
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