CN107305866A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN107305866A
CN107305866A CN201610260956.4A CN201610260956A CN107305866A CN 107305866 A CN107305866 A CN 107305866A CN 201610260956 A CN201610260956 A CN 201610260956A CN 107305866 A CN107305866 A CN 107305866A
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metal
workfunction layers
metal gates
layer
groove
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刘恩铨
杨智伟
赖冠颖
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法包括，首先提供一基底，然后形成一第一金属栅极以及一第二金属栅极于基底上，其中第一金属栅极包含一第一功函数金属层，第二金属栅极包含一第二功函数金属层，第一金属栅极及第二金属栅极具有不同尺寸，且第一功函数金属层及第二功函数金属层包含不同厚度。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作具有不同尺寸的金属栅极的方法。
背景技术
在现有半导体产业中，多晶硅广泛地应用于半导体元件如金氧半导体(metal-oxide-semiconductor,MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boronpenetration)效应导致元件效能降低，及其难以避免的空乏效应(depletioneffect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(work function)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
然而在现今金属栅极晶体管制作过程中，特别是为了制作具有不同临界电压(multi-VT)的半导体元件而沉积不同厚度功函数金属层时，容易因沉积不均于栅极结构中的材料层之间产生孔洞(void)，进而影响到整个元件的效能与运作。因此如何改良现行金属栅极制作工艺以解决此问题即为现今一重要课题。
发明内容
本发明公开一种制作半导体元件的方法。首先提供一基底，然后形成一第一金属栅极以及一第二金属栅极于基底上，其中第一金属栅极包含一第一功函数金属层，第二金属栅极包含一第二功函数金属层，第一金属栅极及第二金属栅极具有不同尺寸，且第一功函数金属层及第二功函数金属层包含不同厚度。
本发明另一实施例公开一种半导体元件，其中半导体元件包含一基底、一第一金属栅极设于基底上以及一第二金属栅极设于基底上。其中第一金属栅极包含一第一功函数金属层，第二金属栅极包含一第二功函数金属层，第一金属栅极及第二金属栅极具有不同尺寸，且第一功函数金属层及第二功函数金属层包含不同厚度。
附图说明
图1至图5为本发明较佳实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 区域
16 区域 18 区域
20 鳍状结构 22 虚置栅极
24 栅极介电层 26 栅极材料层
28 间隙壁 30 源极/漏极区域
32 接触洞蚀刻停止层 34 层间介电层
36 凹槽 38 高介电常数介电层
40 底部金属阻隔层 42 功函数金属层
44 低阻抗金属层 46 金属栅极
48 接触插塞 50 金属层
具体实施方式
请参照图1至图5，图1至图5为本发明较佳实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有三个或三个以上的晶体管区，例如包括区域14、区域16及区域18。在本实施例中，三个区域14、16、18较佳为相同导电型式的晶体管区，例如均为PMOS晶体管区或均为NMOS晶体管区，且三个区域14、16、18分别预定为后续制作不同临界电压(threshold voltage)的栅极结构。基底12的各晶体管区上皆具有至少一鳍状结构20及一绝缘层(图未示)，其中鳍状结构20的底部是被绝缘层，例如氧化硅所包覆而形成浅沟隔离。需注意的是，本实施例虽以制作鳍状结构场效晶体管为例，但不局限于此，本发明又可应用至一般平面型场效晶体管，此实施例也属本发明所涵盖的范围。
依据本发明的较佳实施例，鳍状结构20较佳通过侧壁图案转移(sidewallimage transfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构20的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构20。另外，鳍状结构20的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构20。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
接着可于基底12上形成栅极结构或虚置栅极22。在本实施例中，形成虚置栅极22的方式较佳依序形成一栅极介电层、一栅极材料层以及一选择性硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分栅极材料层与部分栅极介电层，然后剥除图案化光致抗蚀剂，以于区域14、16、18的鳍状结构20上形成至少一由图案化的栅极介电层24与图案化的栅极材料层26所构成的虚置栅极22或栅极结构。
值得注意的是，由于在本实施例中，三个区域14、16、18较佳为相同导电型式的晶体管区，例如均为PMOS晶体管区或均为NMOS晶体管区，且三个区域14、16、18分别预定为后续制作不同临界电压(threshold voltage)等的情况，因此后续转换为金属栅极后，其所分别形成的底部金属阻隔层(bottom barrier metal,BBM)及/或功函数金属层至少有一者具有不同厚度及/或不同数目的多层结构。所以本发明即对具有较厚及/或数目多的多层结构底部的金属阻隔层(BBM)及/或功函数金属层，直接利用光学邻近修正(opticalproximity correction,OPC)来调整原先尺寸设计相同的栅极线宽，预定调整(pre-sizing)成较大的栅极线宽，以期后续形成的栅极凹槽相对较宽。
举例来说，各区域14、16、18上的虚置栅极22较佳因应后续晶体管元件的临界电压的不同而具有不同尺寸，例如区域14于后续制作工艺中是用来制作具有标准临界电压(standard voltage threshold,SVT)的晶体管元件，因此在此区域14中的虚置栅极22较佳为最小尺寸；区域16在后续制作工艺中是用来制作具有低临界电压(low voltage threshold,LVT)的晶体管元件，因此在此区域16中的虚置栅极22较佳为中等尺寸或略大于区域14的虚置栅极22；区域18在后续制作工艺中是用来制作具有超低临界电压(ultra lowvoltage threshold,ULVT)的晶体管元件，因此在此区域18中的虚置栅极22较佳为三个区域14、16、18中的最大尺寸。需注意的是，在本实施例中所定义虚置栅极22尺寸不同是指各区域14、16、18中的虚置栅极22具有不同的宽度及/或长度，尤其是在对应通道长度的方向上，各区域14、16、18中的虚置栅极22具有不同的宽度，而虚置栅极22之间的其他参数，例如材料组成或高度等则相同。
然后在各虚置栅极22侧壁形成至少一间隙壁28，于间隙壁28两侧的鳍状结构20以及/或基底12中形成一源极/漏极区域30及/或外延层(图未示)，并选择性于源极/漏极区域30及/或外延层的表面形成一金属硅化物(图未示)。在本实施例中，间隙壁28可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁(图未示)以及一主间隙壁(图未示)，且间隙壁28可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。源极/漏极区域30与外延层可依据所置备晶体管的导电型式而包含不同掺质或不同材料。例如源极/漏极区域30可包含P型掺质或N型掺质，而外延层则可包含锗化硅、碳化硅或磷化硅。
然后如图2所示，可选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contact etch stop layer,CESL)32于基底12上并覆盖虚置栅极22，再形成一层间介电层34于CESL 32上。接着进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分层间介电层34与部分接触洞蚀刻停止层32并暴露出由多晶硅材料所构成的栅极材料层26，使各区域14、16、18的栅极材料层26上表面与层间介电层34上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构22转换为金属栅极。例如图3所示，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(TetramethylammoniumHydroxide,TMAH)等蚀刻溶液来去除虚置栅极22或栅极结构中的栅极材料层26，以于层间介电层34中形成凹槽36。
值得注意的是，由于原本设于基底12上的虚置栅极22各具有不同尺寸，因此在去除虚置栅极22后各凹槽36也具有不同尺寸。例如在本实施例中，区域14的凹槽36较佳为最小尺寸，区域16的凹槽36为中等尺寸或略大于区域14的凹槽36，而区域18的凹槽36则为三者中的最大尺寸。如同上面关于尺寸的论述，本实施例中所谓凹槽36之间具有不同尺寸是指各区域14、16、18中的凹槽36具有不同宽度及/或长度，凹槽36之间的其他参数，例如深度则相同。
之后如图4所示，依序形成一高介电常数介电层38、一底部金属阻隔层(bottom barrier metal,BBM)40、一功函数金属层42以及一低阻抗金属层44于各凹槽14、16、18内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层44、部分功函数金属层42、部分底部金属阻隔层40与部分高介电常数介电层38以形成金属栅极46于各区域14、16、18。
在本实施例中，由于各区域14、16、18中的凹槽36在填入高介电常数介电层38等材料层之前便已各自包含不同尺寸，因此依据本发明一实施例，在各区域14、16、18中沉积于各凹槽的高介电常数介电层38、底部金属阻隔层40以及/或功函数金属层42可直接具有不同厚度。
更具体而言，各区域14、16、18中的高介电常数介电层38可分别具有不同厚度，各区域14、16、18中的底部金属阻隔层40可具有不同厚度，以及/或是各区域14、16、18中的功函数金属层42可具有不同厚度。
需注意的是，虽然各区域14、16、18中所沉积的高介电常数介电层38、底部金属阻隔层40以及功函数金属层42可分别具有不同厚度，但依据本发明的较佳实施例，本发明较佳在区域14、16、18中的各高介电常数介电层38为相同厚度以及各底部金属阻隔层40为相同厚度的情况下使区域14、16、18中的各功函数金属层42为不同厚度。此外，依据本发明另一实施例，又可选择在区域14、16、18中形成相同厚度的高介电常数介电层38但不同厚度的底部金属阻隔层40，例如区域14的底部金属阻隔层40具有最低厚度，区域16的底部金属阻隔层40具有中间厚度，而区域18的底部金属阻隔层40具有最高厚度，同时各区域14、16、18中的功函数金数层42厚度可选择为相同或不同，此实施例也属本发明所涵盖的范围。
在本实施例中，于各区域14、16、18中形成不同厚度功函数金属层42的方法除了可依据前述利用凹槽36尺寸的不同直接沉积形成具有不同厚度的功函数金属层42外，又可选择先沉积一功函数金属层于各凹槽14、16、18后再分别以蚀刻去除特定区域的部分功函数金属层42，由此调整功函数金属层42于各区域14、16、18的厚度。举例来说，可先沉积一功函数金属层于区域14、16、18中的各凹槽36，然后形成一图案化掩模，例如图案化光致抗蚀剂于区域18，接着去除未被图案化光致抗蚀剂所遮蔽的区域14与区域16上的部分功函数金属层，使区域18上的功函数金属层厚度大于区域14、16上的功函数金属层厚度。随后可再形成另一图案化光致抗蚀剂覆盖区域16、18，并利用另一道蚀刻去除区域14上的部分功函数金属层，如此便可得到三种不同厚度的功函数金属层，即区域18上的功函数金属层厚度大于区域16上的功函数金属层，同时区域16上的功函数金属层厚度又大于区域14上的功函数金属层。
在本实施例中，高介电常数介电层38包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium siliconoxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconiumsilicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconatetitanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。
底部金属阻隔层40可选自由氮化钛(TiN)以及氮化钽(TaN)所构成的群组，但不局限于此。
功函数金属层42较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层42可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层42可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层42与低阻抗金属层44之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层44则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。
之后可选择性去除部分高介电常数介电层38、部分底部金属阻隔层40、部分功函数金属层42与部分低阻抗金属层44形成凹槽(图未示)，然后再填入一硬掩模(图未示)于凹槽内并使硬掩模与层间介电层34表面齐平，其中硬掩模可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
随后如图5所示，可进行一接触插塞制作工艺形成接触插塞48分别电连接源极/漏极区域30。在本实施例中，形成接触插塞48的方式可先去除部分层间介电层34与部分接触洞蚀刻停止层32形成接触洞(图未示)，然后依序沉积一阻隔层(图未示)与一金属层50于基底12上并填满接触洞。接着利用一平坦化制作工艺，例如CMP去除部分金属层50、部分阻隔层甚至部分层间介电层34，以于接触洞中形成接触插塞48，其中接触插塞48上表面较佳与层间介电层34上表面切齐。在本实施例中，阻隔层较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层50较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (16)

1.一种制作半导体元件的方法，包含：
提供一基底；以及
形成一第一金属栅极以及一第二金属栅极于该基底上，其中该第一金属栅极包含一第一功函数金属层，该第二金属栅极包含一第二功函数金属层，该第一金属栅极及该第二金属栅极具有不同尺寸，且该第一功函数金属层及该第二功函数金属层包含不同厚度。
2.如权利要求1所述的方法，另包含：
形成一第一虚置栅极以及一第二虚置栅极于该基底上；
形成一介电层于该第一虚置栅极及该第二虚置栅极上；
平坦化该介电层；以及
去除该第一虚置栅极及该第二虚置栅极以形成一第一凹槽及一第二凹槽。
3.如权利要求2所述的方法，其中该第一虚置栅极及该第二虚置栅极包含不同尺寸。
4.如权利要求2所述的方法，另包含：
形成该第一功函数金属层于该第一凹槽以及该第二功函数金属层于该第二凹槽；
形成一第一低阻抗金属层于该第一功函数金属层上以及一第二低阻抗金属层于该第二功函数金属层上；以及
平坦化该第一低阻抗金属层、该第一功函数金属层、该第二低阻抗金属层及该第二功函数金属层以形成该第一金属栅极及该第二金属栅极。
5.如权利要求4所述的方法，其中该第一功函数金属层及该第二功函数金属层包含相同导电型式。
6.如权利要求4所述的方法，另包含形成该第一凹槽、该第二凹槽以及一第三凹槽于该介电层中，其中该第一凹槽、该第二凹槽及该第三凹槽包含不同尺寸。
7.如权利要求6所述的方法，另包含：
形成该第一虚置栅极、该第二虚置栅极以及一第三虚置栅极于该基底上；
形成该介电层于该第一虚置栅极、该第二虚置栅极及该第三虚置栅极上；
平坦化该介电层；以及
去除该第一虚置栅极、该第二虚置栅极及该第三虚置栅极以形成该第一凹槽、该第二凹槽及该第三凹槽。
8.如权利要求7所述的方法，其中该第一虚置栅极、该第二虚置栅极及该第三虚置栅极包含不同尺寸。
9.如权利要求7所述的方法，另包含形成一第三功函数金属层于该第三凹槽，其中该第一功函数金属层、该第二功函数金属层及该第三功函数金属层包含不同厚度。
10.如权利要求9所述的方法，
形成一第一低阻抗金属层于该第一功函数金属层上，一第二低阻抗金属层于该第二功函数金属层上以及一第三低阻抗金属层于该第三功函数金属层上；以及
平坦化该第一低阻抗金属层、该第一功函数金属层、该第二低阻抗金属层，该第二功函数金属层，该第三低阻抗金属层及该第三功函数金属层以形成该第一金属栅极、该第二金属栅极及一第三金属栅极。
11.如权利要求9所述的方法，其中该第一功函数金属层、该第二功函数金属层及该第三功函数金属层包含相同导电型式。
12.一种半导体元件，包含：
基底；
第一金属栅极，设于该基底上，其中该第一金属栅极包含第一功函数金属层；以及
第二金属栅极，设于该基底上，其中该第二金属栅极包含第二功函数金属层，该第一金属栅极及该第二金属栅极具有不同尺寸，且该第一功函数金属层及该第二功函数金属层包含不同厚度。
13.如权利要求12所述的半导体元件，其中该第一功函数金属层及该第二功函数金属层包含相同导电型式。
14.如权利要求12所述的半导体元件，另包含介电层，设于该基底上并环绕该第一金属栅极及该第二金属栅极，其中该第一金属栅极、该第二金属栅极及该介电层的上表面齐平。
15.如权利要求12所述的半导体元件，另包含第三金属栅极，设于该基底上，该第三金属栅极包含第三功函数金属层，该第一金属栅极、该第二金属栅极及该第三金属栅极具有不同尺寸，且该第一功函数金属层、该第二功函数金属层及该第三功函数金属层包含不同厚度。
16.如权利要求15所述的半导体元件，另包含介电层，设于该基底上并环绕该第一金属栅极、该第二金属栅极及该第三金属栅极，其中该第一金属栅极、该第二金属栅极、该第三金属栅极及该介电层的上表面齐平。
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