CN106683990A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN106683990A
CN106683990A CN201510749346.6A CN201510749346A CN106683990A CN 106683990 A CN106683990 A CN 106683990A CN 201510749346 A CN201510749346 A CN 201510749346A CN 106683990 A CN106683990 A CN 106683990A
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CN106683990B (zh
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王嫈乔
林昭宏
傅思逸
郑志祥
冯立伟
洪裕祥
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法包括：首先提供一基底，该基底上设有一栅极结构、一第一间隙壁环绕该栅极结构以及一接触洞蚀刻停止层设于该第一间隙壁旁，然后形成一遮盖层于栅极结构、第一间隙壁及接触洞蚀刻停止层上，并接着去除部分遮盖层以形成一第二间隙壁于接触洞蚀刻停止层旁。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种于接触洞蚀刻停止层旁形成间隙壁的方法。
背景技术
在现有半导体产业中，多晶硅系广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boron penetration)效应导致元件效能降低，及其难以避免的空乏效应(depletion effect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(work function)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
在现今金属栅极晶体管制作过程中，特别是在进行自行对准接触插塞(self-aligned contacts,SAC))制作工艺时通常会先去除部分金属栅极并于金属栅极上填入一保护用的硬掩模。然而现行于金属栅极上设置硬掩模的设计已无法在形成接触洞时确保金属栅极不受到损害。因此如何改良现行金属栅极制作工艺即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例公开一种制作半导体元件的方法。首先提供一基底，该基底上设有一栅极结构、一第一间隙壁环绕该栅极结构以及一接触洞蚀刻停止层设于该第一间隙壁旁，然后形成一遮盖层于栅极结构、第一间隙壁及接触洞蚀刻停止层上，并接着去除部分遮盖层以形成一第二间隙壁于接触洞蚀刻停止层旁。
本发明另公开一种半导体元件，包含：一基底，一栅极结构设于基底上，一第一间隙壁环绕栅极结构，一接触洞蚀刻停止层设于第一间隙壁旁以及一第二间隙壁设于接触洞蚀刻停止层旁。
附图说明
图1至图11为本发明优选实施例制作一半导体元件的方法示意图；
图12为本发明另一实施例的一半导体元件的结构示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 栅极结构 18 栅极结构
20 栅极结构 22 栅极结构
24 高介电常数介电层 26 栅极电极
28 第一硬掩模 30 第二硬掩模
32 间隙壁 34 源极/漏极区域
36 接触洞蚀刻停止层
38 掩模层 40 第一层间介电层
42 遮盖层 44 遮盖层
46 遮盖层 48 间隙壁
50 间隙壁 52 间隙壁
54 第二层间介电层 56 功函数金属层
58 低阻抗金属层 66 金属栅极
68 金属栅极 70 金属栅极
72 金属栅极 74 接触插塞
具体实施方式
请参照图1至图11，图1至图11为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上可定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。基底12上具有至少一鳍状结构14及一绝缘层(图未示)，其中鳍状结构14的底部被绝缘层，例如氧化硅所包覆而形成浅沟隔离，且部分的鳍状结构14上另分别设有多个栅极结构16、18、20、22。需注意的是，本实施例虽以四个栅极结构16、18、20、22为例，但栅极结构16、18、20、22的数量并不局限于此，而可视制作工艺需求任意调整。
鳍状结构14的形成方式可以包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中。接着，对应三栅极晶体管元件及双栅极鳍状晶体管元件结构特性的不同，而可选择性去除或留下图案化掩模，并利用沉积、化学机械研磨(chemicalmechanical polishing,CMP)及回蚀刻制作工艺而形成一环绕鳍状结构14底部的浅沟隔离。除此之外，鳍状结构14的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出半导体层，此半导体层即可作为相对应的鳍状结构14。同样的，另可以选择性去除或留下图案化硬掩模层，并通过沉积、CMP及回蚀刻制作工艺形成一浅沟隔离以包覆住鳍状结构14的底部。另外，当基底12为硅覆绝缘基板时，则可利用图案化掩模来蚀刻基底上的一半导体层，并停止于此半导体层下方的一底氧化层以形成鳍状结构，故可省略前述制作浅沟隔离的步骤。
栅极结构16、18、20、22的制作方式可依据制作工艺需求以先栅极(gatefirst)制作工艺、后栅极(gate last)制作工艺的先栅极介电层(high-k first)制作工艺以及后栅极制作工艺的后栅极介电层(high-k last)制作工艺等方式制作完成。以本实施例的先栅极介电层制作工艺为例，可先于鳍状结构14上形成一优选包含高介电常数介电层24、多晶硅材料所构成的栅极电极26、第一硬掩模28与第二硬掩模30所构成的栅极结构16、18、20、22，然后于栅极结构16、18、20、22侧壁形成间隙壁32。
在本实施例中，高介电常数介电层24包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium siliconoxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconiumsilicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconatetitanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。
其次，第一硬掩模28与第二硬掩模30优选由不同材料所构成，例如第一硬掩模28可包含氮化硅而第二硬掩模30可包含氧化硅，但不局限于此。间隙壁32可选自由二氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。
接着于间隙壁32两侧的鳍状结构14以及/或基底12中形成一源极/漏极区域34及/或外延层(图未示)，并选择性于源极/漏极区域34及/或外延层的表面形成一金属硅化物(图未示)。然后形成一接触洞蚀刻停止层36于栅极结构16、18、20、22与基底12上，其中接触洞蚀刻停止层36可选自由氮化硅以及氮碳化硅所构成的群组，但并不局限于此。
随后如图2所示，形成一掩模层38于栅极结构16、18、20、22与接触洞蚀刻停止层36上并填满栅极结构16、18、20、22之间的空间。在本实施例中，掩模层38可包含一有机介电层(organic dielectric layer,ODL)以及/或一光致抗蚀剂层，但不局限于此。
如图3所示，然后进行一蚀刻制作工艺，去除部分掩模层38并使掩模层38的上表面略低于第二硬掩模30的上表面。
如图4所示，接着再进行一蚀刻制作工艺，去除第二硬掩模30旁的部分接触洞蚀刻停止层36与部分间隙壁32以暴露出第二硬掩模30，包括第二硬掩模30的上表面与侧壁。在本步骤中，仅部分间隙壁32被去除而剩余的的间隙壁32仍设于第一硬掩模28旁且其上表面具有一约略弧形的轮廓。
然后如图5所示，完全去除掩模层38并暴露出下面的接触洞蚀刻停止层36。
如图6所示，接着形成一第一层间介电层40于栅极结构16、18、20、22上并完全覆盖接触洞蚀刻停止层36、间隙壁32与第二硬掩模30。在本实施例中，第一层间介电层40可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。
如图7所示，然后进行一平坦化制作工艺，例如以CMP平坦化部分第一层间介电层40并去除所有第二硬掩模30甚至部分第一硬掩模28，使剩余的第一硬掩模28上表面与第一层间介电层40上表面齐平。
接着如图8所示，进行一蚀刻制作工艺完全去除第一层间介电层40并再次暴露出下面的接触洞蚀刻停止层36。
随后如图9所示，形成一遮盖层42于栅极结构16、18、20、22、间隙壁32、第一硬掩模28与接触洞蚀刻停止层36上，其中遮盖层42优选为一复合层结构，例如又更细部包含一遮盖层44与遮盖层46。在本实施例中，遮盖层44与遮盖层46优选由不同材料所构成，例如遮盖层44可包含氧化硅而遮盖层46可包含氮碳化硅，但不局限于此。依据本发明的一实施例，遮盖层44与遮盖层46可选自由氧化硅、氮碳化硅(SiCN)、碳氮氧化硅(SiCON)以及碳氮硼化硅(SiCBN)所构成的群组且两者优选由不同材料所构成，此实施例也属本发明所涵盖的范围。
然后如图10所示，进行一蚀刻制作工艺去除部分遮盖层42以形成另一间隙壁48于接触洞蚀刻停止层36旁，其中间隙壁48更细部包含一间隙壁50跨坐于接触洞蚀刻停止层36上以及一间隙壁52设于间隙壁50上。
如图11所示，接着形成一第二层间介电层54于栅极结构16、18、20、22、接触洞蚀刻停止层36与间隙壁48上，并进行一平坦化制作工艺，例如利用CMP去除部分第二层间介电层54、部分间隙壁32、部分接触洞蚀刻停止层36及部分间隙壁48，使剩余的第二层间介电层54、间隙壁32、接触洞蚀刻停止层36及间隙壁48的上表面齐平。
之后进行一金属栅极置换制作工艺，例如先以蚀刻方式去除由多晶硅材料所构成的栅极电极26以形成一开口(图未示)，然后依序形成一功函数金属层56以及一低阻抗金属层58于开口内，并搭配进行一平坦化制作工艺，例如以CMP去除部分低阻抗金属层58与部分功函数金属层56以形成金属栅极66、68、70、72。
在本实施例中，功函数金属层56优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层56可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层56可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层56与低阻抗金属层58之间可包含另一顶部阻障层(图未示)，其中顶部阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层58则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungstenphosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是此领域者所熟知技术，在此不另加赘述。
随后可选择性进行一接触插塞制作工艺，例如可利用蚀刻去除金属栅极68与金属栅极70之间的部分或所有第二层间介电层54以及部分接触洞蚀刻停止层36形成接触洞(图未示)，然后再填入金属材料形成接触插塞74电连接基底12的源极/漏极区域34。在本实施例中，接触插塞74可包含一阻隔层与一金属层，其中阻隔层优选选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层优选选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。至此即完成本发明的半导体元件的制作。
请再参照图11，其另揭露本发明优选实施例的一半导体元件的结构示意图。如图11所示，本发明的半导体元件主要包含一基底12、至少一栅极结构或金属栅极66设于基底12上、一间隙壁32环绕金属栅极66、一接触洞蚀刻停止层36设于间隙壁32旁以及另一间隙壁48设于接触洞蚀刻停止层36旁。
更具体而言，本实施例的接触洞蚀刻停止层36优选为L型，间隙壁48更细部包含一间隙壁50与间隙壁52，其中间隙壁50与接触洞蚀刻停止层36一样为L型并跨坐在接触洞蚀刻停止层上36，间隙壁52设于间隙壁50上，且间隙壁50与间隙壁52的边缘优选不与接触洞蚀刻停止层36的边缘切齐。另外在本实施例中，接触洞蚀刻停止层36优选包含氮化硅或氮碳化硅，间隙壁32优选包含氧化硅或氮化硅，间隙壁50优选包含氧化硅而间隙壁52则包含氮碳化硅，但不局限于此，例如间隙壁50、52又可选自由氧化硅、氮碳化硅(SiCN)、碳氮氧化硅(SiCON)以及碳氮硼化硅(SiCBN)所构成的群组且两者优选由不同材料所构成。
请接着参照图12，其为本发明另一实施例的一半导体元件的结构示意图。如图12所示，相较于图10中以蚀刻制作工艺去除部分遮盖层42形成间隙壁48时不耗损任何间隙壁48下方的接触洞蚀刻停止层36，本实施例可于去除部分遮盖层42形成间隙壁48时同时去除部分接触洞蚀刻停止层36，使间隙壁48的边缘与接触洞蚀刻停止层36的一边缘切齐，而形成另一种半导体元件的态样。
综上所述，本发明主要于接触洞蚀刻停止层形成后再沉积一遮盖层于栅极结构、间隙壁以及接触洞蚀刻停止层上，然后去除部分遮盖层以于接触洞蚀刻停止层旁形成另一间隙壁。通过此间隙壁的保护，本发明可于后续进行自行对准接触插塞(self-aligned contact)制作工艺时直接利用间隙壁定义出接触洞的位置，并对之后所进行的蚀刻制作工艺提供一种最佳化的选择。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (9)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上设有栅极结构、第一间隙壁环绕该栅极结构以及接触洞蚀刻停止层设于该第一间隙壁旁；
形成一遮盖层于该栅极结构、该第一间隙壁及该接触洞蚀刻停止层上；以及
去除部分该遮盖层以形成一第二间隙壁于该接触洞蚀刻停止层旁。
2.如权利要求1所述的方法，还包含：
形成该第一间隙壁于该栅极结构旁，该栅极结构包含第一硬掩模以及第二硬掩模设于一栅极电极上；
形成该接触洞蚀刻停止层于该基底、该第一间隙壁及该第二硬掩模上；
形成一掩模层于该接触洞蚀刻停止层上；
去除部分该掩模层并使该掩模层的上表面低于该第二硬掩模的上表面；
去除部分该接触洞蚀刻停止层及部分该第一间隙壁以暴露出该第二硬掩模；
去除该掩模层；
形成一第一层间介电层于该接触洞蚀刻停止层及该第二硬掩模上；
平坦化部分该第一层间介电层及该第二硬掩模；
去除该第一层间介电层；以及
形成该遮盖层于该接触洞蚀刻停止层及该第一硬掩模上。
3.如权利要求1所述的方法，还包含：
形成一第二层间介电层于该栅极结构、该接触洞蚀刻停止层及该第二间隙壁上；以及
平坦化部分该第二层间介电层、部分该第二间隙壁、部分该接触洞蚀刻停止层及部分该第一间隙壁。
4.如权利要求1所述的方法，还包含去除部分该遮盖层及部分该接触洞蚀刻停止层以形成该第二间隙壁。
5.一种半导体元件，包含：
基底，该基底上具有栅极结构；
第一间隙壁，环绕该栅极结构；
接触洞蚀刻停止层，设于该第一间隙壁旁；以及
第二间隙壁，设于该接触洞蚀刻停止层旁。
6.如权利要求5所述的半导体元件，其中该接触洞蚀刻停止层为L型。
7.如权利要求6所述的半导体元件，其中该第二间隙壁包含：
第三间隙壁，设于该接触洞蚀刻停止层上，该第三间隙壁为L型；以及
第四间隙壁，设于该第三间隙壁上。
8.如权利要求5所述的半导体元件，其中该第二间隙壁的一边缘与该接触洞蚀刻停止层的一边缘切齐。
9.如权利要求5所述的半导体元件，其中该第二间隙壁的一边缘不与该接触洞蚀刻停止层的一边缘切齐。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10147649B2 (en) 2016-05-27 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with gate stack and method for forming the same
US10276662B2 (en) 2016-05-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming contact trench
US10847634B2 (en) * 2017-10-30 2020-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Field effect transistor and method of forming the same
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Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050040479A1 (en) 2003-08-20 2005-02-24 Pdf Solutions Oxide-Nitride-Oxide spacer with oxide layers free of nitridization
US20080179684A1 (en) * 2007-01-29 2008-07-31 Chia-Wen Liang Method of fabricating a strained silicon channel complementary metal oxide semiconductor transistor and structure thereof
US7888195B2 (en) * 2008-08-26 2011-02-15 United Microelectronics Corp. Metal gate transistor and method for fabricating the same
US8048790B2 (en) 2009-09-17 2011-11-01 Globalfoundries Inc. Method for self-aligning a stop layer to a replacement gate for self-aligned contact integration
US8389371B2 (en) 2010-06-30 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating integrated circuit device, including removing at least a portion of a spacer
US20120098043A1 (en) * 2010-10-25 2012-04-26 Ya-Hsueh Hsieh Semiconductor device having metal gate and manufacturing method thereof
US8431453B2 (en) * 2011-03-31 2013-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure
US8765561B2 (en) * 2011-06-06 2014-07-01 United Microelectronics Corp. Method for fabricating semiconductor device
TWI570783B (zh) * 2013-06-07 2017-02-11 聯華電子股份有限公司 半導體製程
US8921947B1 (en) * 2013-06-10 2014-12-30 United Microelectronics Corp. Multi-metal gate semiconductor device having triple diameter metal opening
US8765546B1 (en) * 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor

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