CN106409889A - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN106409889A
CN106409889A CN201510467637.6A CN201510467637A CN106409889A CN 106409889 A CN106409889 A CN 106409889A CN 201510467637 A CN201510467637 A CN 201510467637A CN 106409889 A CN106409889 A CN 106409889A
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barrier layer
titanium
bottom metal
half portion
nitrogen
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CN106409889B (zh
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陆俊岑
赖建铭
周禄盛
蔡雅卉
邱靖翔
萧有彤
黄振铭
李昆儒
王裕平
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件，其包含一基底以及一栅极结构设于基底上，其中栅极结构包含一高介电常数介电层设于基底上以及一底部金属阻隔层设于高介电常数介电层上，该底部金属阻隔层包含一上半部、一中半部以及一下半部，且上半部为一富氮部分而中半部及下半部各为一富钛部分。

Description

半导体元件
技术领域
本发明涉及一种半导体元件，尤其是涉及一种具有金属栅极的半导体元件。
背景技术
在现有半导体产业中，多晶硅系广泛地应用于半导体元件如金属氧化物半导体(metal-oxide-semiconductor，MOS)晶体管中，作为标准的栅极填充材料选择。然而，随着MOS晶体管尺寸持续地微缩，传统多晶硅栅极因硼穿透(boron penetration)效应导致元件效能降低，及其难以避免的空乏效应(depletion effect)等问题，使得等效的栅极介电层厚度增加、栅极电容值下降，进而导致元件驱动能力的衰退等困境。因此，半导体业界更尝试以新的栅极填充材料，例如利用功函数(work function)金属来取代传统的多晶硅栅极，用以作为匹配高介电常数(High-K)栅极介电层的控制电极。
一般而言，传统平面型金属栅极晶体管通常采用离子注入的方式来同时调整晶体管的临界电压。然而随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。然而现今鳍状场效晶体管的制作工艺中，当施加于介电材料上的电场强度超过临界值时，若流过该介电材料电流突然增大容易使介电材料完全失效而产生所谓的时间相依介电击穿(time-dependent dielectric breakdown,TDDB)问题。因此如何在鳍状晶体管的架构下改良此缺点即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例揭露一种半导体元件，其包含一基底以及一栅极结构设于基底上，其中栅极结构包含一高介电常数介电层设于基底上以及一底部金属阻隔层设于高介电常数介电层上，该底部金属阻隔层包含一上半部、一中半部以及一下半部，且上半部为一富氮部分而中半部及下半部各为一富钛部分。
本发明另一实施例揭露一种半导体元件，其包含一基底以及一栅极结构设于基底上，其中栅极结构包含一高介电常数介电层设于基底上以及一底部金属阻隔层设于高介电常数介电层上，该底部金属阻隔层包含一上半部、一中半部以及一下半部，且中半部为一富氮部分而上半部及下半部各为一富钛部分。
附图说明
图1为本发明优选实施例制作一半导体元件的示意图；
图2为本发明优选实施例的底部金属阻隔层的放大示意图；
图3为本发明另一实施例的半导体元件的结构示意图。
主要元件符号说明
12 基底 14 栅极结构
16 间隙壁 18 源极/漏极区域
20 接触洞蚀刻停止层 22 层间介电层
24 介质层 26 高介电常数介电层
28 底部金属阻隔层 30 底部金属阻隔层
32 功函数金属层 34 低阻抗金属层
36 上半部 38 中半部
40 下半部
具体实施方式
请参照图1， 图1为本发明优选实施例制作一半导体元件的示意图。如图1所示，首先提供一基底12，然后于基底上形成至少一栅极结构14。其中，基底12例如是一硅基底、一含硅基底(例如SiC)、一三五族基底(例如GaN)、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)、一硅覆绝缘(silicon-on-insulator, SOI)基底或一含外延层的基底(例如具有2.5微米(um)厚的P型外延层的P型基底)等半导体基底。
栅极结构14的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先栅极介电层(high-k first)制作工艺以及后栅极制作工艺的后栅极介电层(high-k last)制作工艺等方式制作完成。以本实施例的后栅极介电层制作工艺为例，可先于基底12上形成一优选包含由介质层与多晶硅材料所构成的虚置栅极(图未示)，然后于虚置栅极侧壁形成间隙壁16。接着于间隙壁16两侧的基底12中形成一源极/漏极区域18及/或外延层(图未示)、选择性于源极/漏极区域18及/或外延层的表面形成一金属硅化物(图未示)、形成一接触洞蚀刻停止层20覆盖虚置栅极，并形成一层间介电层22于接触洞蚀刻停止层20上。
之后可进行一金属栅极置换(replacement metal gate)制作工艺，先平坦化部分的层间介电层22及接触洞蚀刻停止层20，并再将虚置栅极转换为金属栅极的栅极结构14。金属栅极置换制作工艺可包括先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除虚置栅极中的多晶硅材料以于层间介电层22与间隙壁16中形成一凹槽。
接着可先去除原本虚置栅极中的介质层，并依序沉积另一介质层24、一高介电常数介电层26、一底部金属阻隔层28、一底部金属阻隔层30、一功函数金属层32以及一低阻抗金属层34于凹槽内。然后搭配进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)制作工艺使高介电常数介电层26、底部金属阻隔层28、底部金属阻隔层30、功函数金属层32以及低阻抗金属层34的上表面与层间介电层22表面齐平。由于本实施例是依据后栅极介电层(high-k last)制作工艺所制作，因此高介电常数介电层26、底部金属阻隔层28、底部金属阻隔层30以及功函数金属层32等剖面优选为U型。若本发明依据先栅极介电层(high-k first)制作工艺来制作，则高介电常数介电层26的剖面优选为一字型，而底部金属阻隔层28、底部金属阻隔层30与功函数金属层32等的剖面则为U型，此实施例也属本发明所涵盖的范围。
在本实施例中，介质层24优选包含硅化物层，例如二氧化硅(SiO2)、氮化硅(SiN)或氮氧化硅(SiON)，但不排除可选自高介电常数的介电材料。底部金属阻隔层28优选包含氮化钛(TiN)，底部金属阻隔层30则优选包含氮化钽(TaN)，但不局限于此。
高介电常数介电层26包含介电常数大于4的介电材料，例如是选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminumoxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontiumtitanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuthtantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。
功函数金属层32优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层32可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层32可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层32与低阻抗金属层34之间可包含另一顶部阻障层(图未示)，其中顶部阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层34则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极乃此领域者所熟知技术，在此不另加赘述。
值得注意的是，本发明于沉积底部金属阻隔层28时优选同时调整其中氮与钛的比例，使底部金属阻隔层28中的不同部分可具有不同氮对钛的比例。更具体而言，请参考图2，图2为图1部分组成结构的放大示意图，如图2所示，本实施例所沉积的底部金属阻隔层28可大致分为上半部36、中半部38以及下半部40等三部分，其中上半部36、中半部38以及下半部40的厚度各为底部金属阻隔层28整体厚度的三分之一。另外在本实施例中，上半部36为一富氮部分而中半部38及下半部40各为一富钛部分，或从氮与钛的比例分布来看，上半部36的氮对钛的比例为1至1.2比1，中半部38的氮对钛的比例为0.5至1比1，而下半部40的氮对钛的比例为0.5至1比1。换句话说，在本实施例中，底部金属阻隔层28的上半部36具有较高的氮原子比例，而中半部38与下半部40则具有较高的钛原子比例。
请接着参照图3，图3为本发明另一实施例的半导体元件的底部金属阻隔层28的结构示意图。如同前述图2的实施例，本实施例所沉积的底部金属阻隔层28同样可分为上半部36、中半部38以及下半40部等三部分，其中上半部36、中半部38以及下半部40的厚度各为底部金属阻隔层38整体厚度的三分之一。在本实施例中，中半部38为一富氮部分而上半部36及下半部40各为一富钛部分，或从氮与钛的比例分布来看，中半部38的氮对钛的比例为1至1.2比1，上半部36的氮对钛的比例为0.5至1比1，而下半部40的氮对钛的比例为0.5至1比1。换句话说，本实施例中底部金属阻隔层28的中半部38具有较高的氮原子比例，而上半部36与下半部40则具有较高的钛原子比例。
综上所述，本发明主要提供两种金属栅极晶体管架构，其中金属栅极中由氮化钛所构成的底部金属阻隔层优选具有一上半部、一中半部以及一下半部，且上半部为一富氮部分而中半部及下半部各为一富钛部分，或中半部为一富氮部分且上半部及下半部各为一富钛部分。依据上述二实施例所提供的两种金属栅极晶体管架构，本发明可有效改善现行架构容易产生时间相依介电击穿(time-dependent dielectric breakdown,TDDB)的问题。需注意的是，本实施例虽以由氮化钛所构成的底部金属阻隔层28为多层结构而氮化钽所构成的底部金属阻隔层30为单一结构层为例，但不排除依据前述实施例来调整底部金属阻隔层30中氮与钽的比例，使底部金属阻隔层30如同底部金属阻隔层28般经由沉积后分为上半部、中半部以及下半部，且上半部、中半部以及下半部分别具有富氮部分或富钽部分。举例来说，可调整底部金属阻隔层30的上半部为富氮部分而中半部与下半部为富钽部分，或调整底部金属阻隔层30的中半部为富氮部分而上半部与下半部为富钽部分，或调整底部金属阻隔层30的下半部为富氮部分而上半部与中半部为富钽部分，这些实施例均属本发明所涵盖的范围。
另外，上述实施例虽以平面型晶体管为例，但在其他变化实施例中，本发明的半导体元件也可应用于非平面晶体管，例如是鳍状晶体管(Fin-FET)，此时，图1至图3所标示的基底12即相对应代表为形成于一基底上的鳍状结构，此实施例也属本发明所涵盖的范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (14)

1.一种半导体元件，包含：
基底；以及
栅极结构，设于该基底上，该栅极结构包含：
高介电常数介电层，设于该基底上；以及
底部金属阻隔层，设于该高介电常数介电层上，该底部金属阻隔层包含上半部、中半部以及下半部，且该上半部为一富氮部分而该中半部及该下半部各为一富钛部分。
2.如权利要求1所述的半导体元件，其中该上半部的厚度为该底部金属阻隔层的三分之一厚度。
3.如权利要求1所述的半导体元件，其中该中半部的厚度为该底部金属阻隔层的三分之一厚度。
4.如权利要求1所述的半导体元件，其中该下半部的厚度为该底部金属阻隔层的三分之一厚度。
5.如权利要求1所述的半导体元件，其中该上半部的氮对钛的比例为1至1.2比1。
6.如权利要求5所述的半导体元件，其中该中半部的氮对钛的比例为0.5至1比1。
7.如权利要求5所述的半导体元件，其中该下半部的氮对钛的比例为0.5至1比1。
8.一种半导体元件，包含：
基底；以及
栅极结构，设于该基底上，该栅极结构包含：
高介电常数介电层，设于该基底上；以及
底部金属阻隔层，设于该高介电常数介电层上，该底部金属阻隔层包含上半部、中半部以及下半部，且该中半部为一富氮部分且该上半部及该下半部各为一富钛部分。
9.如权利要求8所述的半导体元件，其中该上半部的厚度为该底部金属阻隔层的三分之一厚度。
10.如权利要求第8项所述的半导体元件，其中该中半部的厚度为该底部金属阻隔层的三分之一厚度。
11.如权利要求8所述的半导体元件，其中该下半部的厚度为该底部金属阻隔层的三分之一厚度。
12.如权利要求8所述的半导体元件，其中该中半部的氮对钛的比例为1至1.2比1。
13.如权利要求8所述的半导体元件，其中该中半部的氮对钛的比例为0.5至1比1。
14.如权利要求8所述的半导体元件，其中该下半部的氮对钛的比例为0.5至1比1。
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