CN107808849A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN107808849A
CN107808849A CN201610810283.5A CN201610810283A CN107808849A CN 107808849 A CN107808849 A CN 107808849A CN 201610810283 A CN201610810283 A CN 201610810283A CN 107808849 A CN107808849 A CN 107808849A
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grid structure
clearance wall
dielectric layer
interlayer dielectric
hard mask
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CN107808849B (zh
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洪庆文
吴家荣
李怡慧
刘盈成
黄志森
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/285,471 priority patent/US9941215B2/en
Priority to US15/894,940 priority patent/US10141263B2/en
Publication of CN107808849A publication Critical patent/CN107808849A/zh
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Abstract

本发明公开一种半导体元件及其制作方法。该半导体元件制作方法包括，首先提供一基底，然后形成一第一栅极结构于基底上、一第一间隙壁环绕第一栅极结构以及一层间介电层环绕第一间隙壁。接着进行一第一蚀刻制作工艺去除部分层间介电层以形成一凹槽，进行一第二蚀刻制作工艺去除部分第一间隙壁并扩大该凹槽，最后再形成一接触插塞于该凹槽内。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件，尤其是涉及一种接触插塞底表面包含倒V型轮廓的半导体元件。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
一般而言，半导体制作工艺在进入10纳米世代后接触插塞的接触面积会大幅降低，造成阻值的增加。除此之外，接触插塞的制作也需伴随更多的光掩模来完成。而随着光掩模数量的提升，一点点主动区域的偏移又会再次造成阻值的提升，影响整个元件的运作。因此如何在现今场效晶体管的架构下改良此问题即为现今一重要课题。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先提供一基底，然后形成一第一栅极结构于基底上、一第一间隙壁环绕第一栅极结构以及一层间介电层环绕第一间隙壁。接着进行一第一蚀刻制作工艺去除部分层间介电层以形成一凹槽，进行一第二蚀刻制作工艺去除部分第一间隙壁并扩大该凹槽，最后再形成一接触插塞于该凹槽内。
本发明另一实施例公开一种半导体元件，其主要包含：一基底，一第一栅极结构设于基底上，一第一间隙壁环绕第一栅极结构，一层间介电层环绕第一间隙壁，以及一接触插塞设于第一栅极结构、第一间隙壁以及层间介电层上，其中接触插塞的底表面包含一倒V型。
附图说明
图1为本发明一较佳实施例的半导体元件的上视布局图；
图2至图7为沿着图1中切线AA'方向制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 PMOS区域
16 NMOS区域 18 浅沟隔离
20 栅极结构 22 栅极结构
24 栅极结构 26 栅极介电层
28 栅极材料层 30 间隙壁
32 源极/漏极区域 34 接触洞蚀刻停止层
36 层间介电层 38 高介电常数介电层
40 功函数金属层 42 低阻抗金属层
44 硬掩模 46 遮盖层
48 凹槽 50 凹槽
52 接触插塞 54 接触插塞
56 接触插塞 58 阻隔层
60 金属层 62 V型轮廓
64 倒V型轮廓
具体实施方式
请参照图1至图7，图1为本发明一较佳实施例的半导体元件的上视布局图，图2至图7则为沿着图1中切线AA'位置制作一半导体元件的方法示意图。如图1至图7所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板。基底12上较佳定义有至少一主动区(图未示)，其可于后续制作工艺中用来制作一静态随机存取存储器(static random accessmemory,SRAM)。主动区可细部包含一P型金属氧化物半导体(PMOS)区域14与一N型金属氧化物半导体(NMOS)区域16，其中PMOS区域14与NMOS区域16周围较佳设有例如由氧化硅所构成的浅沟隔离(shallow trench isolation,STI)18。
需注意的是，本实施例虽以制作平面型(planar)场效晶体管为例，但不局限于此，本发明又可应用至一般非平面型场效晶体管(non-planar)鳍状结构场效晶体管，例如可于主动区的基底12上形成至少一鳍状结构，而鳍状结构的底部则较佳被浅沟隔离18所围绕，此实施例也属本发明所涵盖的范围。
依据本发明的较佳实施例，鳍状结构较佳通过侧壁图案转移(sidewall imagetransfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可透过光光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构。另外，鳍状结构的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构。这些形成鳍状结构的实施例均属本发明所涵盖的范围。
接着可于基底12上形成多个栅极结构，例如栅极结构20、22、24或虚置栅极。其中栅极结构可设于PMOS区域14、NMOS区域16或同时横跨PMOS区域14与NMOS区域16。以下主要针对设于浅沟隔离18上的栅极结构20、22、24进行说明。
如图2所示，栅极结构20、22、24的制作方式可依据制作工艺需求以先栅极(gatefirst)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先依序形成一栅极介电层或介质层、一栅极材料层以及一选择性硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分栅极材料层与部分栅极介电层，然后剥除图案化光致抗蚀剂，以于浅沟隔离18上形成由图案化的栅极介电层26与图案化的栅极材料层28所构成的栅极结构20、22、24。
然后在各栅极结构20、22、24侧壁形成至少一间隙壁30，于主动区中间隙壁30两侧的基底12中形成一源极/漏极区域32及/或外延层(图未示)，并选择性于源极/漏极区域32及/或外延层的表面形成一金属硅化物(图未示)。在本实施例中，间隙壁30可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁(图未示)以及一主间隙壁(图未示)。其中本实施例的间隙壁30较佳由氮化硅所构成，但间隙壁30又可选自由氧化硅、氮氧化硅以及氮碳化硅所构成的群组。源极/漏极区域32与外延层可依据所置备晶体管的导电型式而包含不同掺质或不同材料。例如源极/漏极区域32可包含P型掺质或N型掺质，而外延层则可包含锗化硅、碳化硅或磷化硅。
然后如图3所示，先形成一由氮化硅所构成的接触洞蚀刻停止层(contact etchstop layer,CESL)34于基底12上覆盖栅极结构20、22、24，再形成一层间介电层36于接触洞蚀刻停止层34上。接着进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)去除部分层间介电层36与部分接触洞蚀刻停止层34并暴露出由多晶硅材料所构成的栅极材料层28，使各栅极材料层28上表面与层间介电层36上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构20、22、24转换为金属栅极。例如图4所示，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构20、22、24中的栅极材料层28，以于层间介电层36中形成凹槽(图未示)。之后依序形成一高介电常数介电层38、一功函数金属层40以及一低阻抗金属层42于各凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层42、部分功函数金属层40与部分高介电常数介电层38以形成金属栅极。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，各栅极结构20、22、24较佳包含一介质层或栅极介电层26、一U型高介电常数介电层38、一U型功函数金属层40以及一低阻抗金属层42。
在本实施例中，高介电常数介电层38包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层40较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层40可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层40可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层40与低阻抗金属层42之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层42则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
接着去除部分高介电常数介电层38、部分功函数金属层40与部分低阻抗金属层42形成凹槽(图未示)，然后再填入硬掩模44于凹槽内并使硬掩模44与层间介电层38表面齐平，其中硬掩模44可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。之后形成一遮盖层46于层间介电层36上，其中遮盖层46较佳包含氧化物，例如四乙氧基硅烷(Tetraethyl orthosilicate,TEOS)，但不局限于此。
如图5所示，然后先形成一图案化掩模(图未示)，例如一图案化光致抗蚀剂于遮盖层46上，再利用图案化光致抗蚀剂为掩模进行一第一蚀刻制作工艺去除部分遮盖层46与部分层间介电层36以形成凹槽48、50。依据本发明的较佳实施例，第一蚀刻制作工艺中较佳选用对氧化物具有较高选择比或蚀刻率而对氮化物具有较低选择比或蚀刻率的蚀刻剂来形成凹槽48、50，因此第一蚀刻制作工艺较佳在去除由氧化物所构成的部分遮盖层46与部分层间介电层36的同时不去除或仅仅去除一小部分周边由非氧化物所构成的元件，例如接触洞蚀刻停止层34与间隙壁30。换句话说，所形成的凹槽48、50向下深入层间介电层36的深度较佳大于深入接触洞蚀刻停止层34以及/或间隙壁30的深度。在本实施例中，第一蚀刻制作工艺所使用的蚀刻剂较佳选自由环丁烯(C4H6)、氧气以及氩气所构成的群组，但不局限于此。
随后如图6所示，进行一第二蚀刻制作工艺去除部分间隙壁30并扩大之前所形成的凹槽48、50。更具体而言，第二蚀刻制作工艺较佳选用对氮化物具有较高选择比或蚀刻率而对氧化物具有较低选择比或蚀刻率的蚀刻剂来扩大凹槽48、50，因此第二蚀刻制作工艺较佳在去除由氮化物所构成的元件，包括部分硬掩模44、部分接触洞蚀刻停止层34以及部分间隙壁30的同时不去除或仅仅去除一小部分旁边由氧化物所构成的层间介电层36。换句话说，原本较深入层间介电层36的凹槽48、50在第二蚀刻制作工艺后由于将改变为较深入接触洞蚀刻停止层34与间隙壁30。迨第二蚀刻制作工艺完成后，所形成的凹槽48、50，特别是栅极结构与栅极结构之间的凹槽50底部较佳呈现约略波浪状的轮廓，且在层间介电层36正上方具有至少一倒V型轮廓。
最后如图7所示，进行一接触插塞制作工艺形成接触插塞52、54填满凹槽48、50并形成接触插塞56电连接主动区上的源极/漏极区域32。在本实施例中，形成接触插塞52、54、56的方式可先依序沉积一阻隔层58与一金属层60于凹槽48、50内，再利用一平坦化制作工艺，例如以CMP去除部分金属层60、部分阻隔层58甚至部分遮盖层46，以于凹槽48、50中形成接触插塞52、54，其中接触插塞52、54上表面较佳与遮盖层46上表面切齐。在本实施例中，阻隔层58较佳选自由钛、钽、氮化钛、氮化钽以及氮化钨所构成的群组，金属层60较佳选自由铝、钛、钽、钨、铌、钼以及铜所构成的群组，但不局限于此。至此即完成本发明的半导体元件的制作。
请再参照图7，其另公开一半导体元件的结构示意图。如图7中栅极结构22、24之间的元件来看，半导体元件主要包含一基底12、一浅沟隔离18设于基底12上、栅极结构22、24设于浅沟隔离18上、硬掩模44分别设于栅极结构22、24上、间隙壁30分别环绕栅极结构22与栅极结构24、接触洞蚀刻停止层34与层间介电层36设于间隙壁30之间以及接触插塞54设于栅极结构22、24、间隙壁30以及层间介电层36上。
从细部来看，硬掩模44上表面较佳与间隙壁30、接触洞蚀刻停止层34以及层间介电层36上表面齐平，且接触插塞54较佳直接接触栅极结构22、24中的功函数金属层40与低阻抗金属层42等导电材料、硬掩模44、间隙壁30、接触洞蚀刻停止层34以及层间介电层36。
另外在本实施例中，接触插塞54底表面较佳呈现约略波浪状的轮廓，且波浪状轮廓又细部包含V型轮廓62与倒V型轮廓64。更具体而言，层间介电层36正上方的接触插塞54底部较佳具有一倒V型轮廓64，而衔接倒V型轮廓64两侧并深入接触洞蚀刻停止层34的接触插塞54底部即具有V型轮廓62。其中倒V型轮廓64的顶点较佳位于层间介电层36正上方，而V型轮廓62谷点则较佳位于接触洞蚀刻停止层34上或直接接触接触洞蚀刻停止层34，但不排除可位于间隙壁30上，甚至同时位于接触洞蚀刻停止层34以及间隙壁30上，这些均属本发明所涵盖的范围。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (17)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成一第一栅极结构于该基底上、一第一间隙壁环绕该第一栅极结构以及一层间介电层环绕该第一间隙壁；
进行一第一蚀刻制作工艺去除部分该层间介电层以形成一凹槽；
进行一第二蚀刻制作工艺去除部分该第一间隙壁并扩大该凹槽；以及
形成一接触插塞于该凹槽内。
2.如权利要求1所述的方法，另包含：
形成一第二栅极结构于该基底上、一第二间隙壁环绕该第二栅极结构以及该层间介电层环绕该第二间隙壁；
进行该第一蚀刻制作工艺去除设于该第一栅极结构及该第二栅极结构之间的部分该层间介电层；
进行该第二蚀刻制作工艺去除部分该第一间隙壁及部分该第二间隙壁；以及
形成该接触插塞。
3.如权利要求2所述的方法，另包含：
在形成该层间介电层之前形成一接触洞蚀刻停止层于该第一间隙壁及该第二间隙壁上；
进行该第一蚀刻制作工艺；
进行该第二蚀刻制作工艺去除部分该接触洞蚀刻停止层、部分该第一间隙壁以及部分该第二间隙壁；以及
形成该接触插塞。
4.如权利要求2所述的方法，另包含：
形成一第一硬掩模于该第一栅极结构上以及一第二硬掩模于该第二栅极结构上，其中该第一硬掩模、该第二硬掩模及该层间介电层上表面齐平；
进行该第一蚀刻制作工艺；
进行该第二蚀刻制作工艺去除部分该第一硬掩模、部分该第二硬掩模、部分该第一间隙壁以及部分该第二间隙壁；以及
形成该接触插塞。
5.如权利要求1所述的方法，其中该第一蚀刻制作工艺的蚀刻剂选自由环丁烯(C4H6)、氧气以及氩气所构成的群组。
6.如权利要求1所述的方法，其中该第二蚀刻制作工艺的蚀刻剂选自由二氟甲烷(CH2F2)以及氢气所构成的群组。
7.如权利要求1所述的方法，其中该接触插塞的底表面包含一倒V型。
8.如权利要求2所述的方法，其中该接触插塞直接接触该第一栅极结构、该第二栅极结构及该层间介电层。
9.如权利要求3所述的方法，其中该接触插塞直接接触该第一栅极结构、该第二栅极结构、该接触洞蚀刻停止层以及该层间介电层。
10.如权利要求4所述的方法，其中该接触插塞直接接触该第一栅极结构、该第一硬掩模、该第二栅极结构、该第二硬掩模以及该层间介电层。
11.一种半导体元件，包含：
基底；
第一栅极结构，设于该基底上；
第一间隙壁，环绕该第一栅极结构；
层间介电层，环绕该第一间隙壁；以及
接触插塞，设于该第一栅极结构、该第一间隙壁以及该层间介电层上，其中该接触插塞的底表面包含一倒V型。
12.如权利要求11所述的半导体元件，另包含：
第二栅极结构，设于该基底上；
第二间隙壁，环绕该第二栅极结构；以及
该层间介电层，设于该第一间隙壁及该第二间隙壁之间。
13.如权利要求12所述的半导体元件，另包含一接触洞蚀刻停止层设于该第一间隙壁及该第二间隙壁之间。
14.如权利要求12所述的半导体元件，另包含：
第一硬掩模，设于该第一栅极结构上；以及
第二硬掩模，设于该第二栅极结构上，其中该第一硬掩模、该第二硬掩模及该层间介电层的上表面齐平。
15.如权利要求12所述的半导体元件，其中该接触插塞直接接触该第一栅极结构、该第二栅极结构及该层间介电层。
16.如权利要求13所述的半导体元件，其中该接触插塞直接接触该第一栅极结构、该第二栅极结构、该接触洞蚀刻停止层及该层间介电层。
17.如权利要求14所述的半导体元件，其中该接触插塞直接接触该第一栅极结构、该第一硬掩模、该第二栅极结构、该第二硬掩模及该层间介电层。
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