CN109994537A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN109994537A
CN109994537A CN201711474311.1A CN201711474311A CN109994537A CN 109994537 A CN109994537 A CN 109994537A CN 201711474311 A CN201711474311 A CN 201711474311A CN 109994537 A CN109994537 A CN 109994537A
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groove
isolation structure
substrate
laying
semiconductor element
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CN109994537B (zh
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马瑞吉
林家辉
杨国裕
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201711474311.1A priority Critical patent/CN109994537B/zh
Priority to CN202210954362.9A priority patent/CN115332153A/zh
Priority to US15/888,072 priority patent/US10460980B2/en
Publication of CN109994537A publication Critical patent/CN109994537A/zh
Priority to US16/561,026 priority patent/US11101165B2/en
Priority to US17/340,075 priority patent/US11521891B2/en
Priority to US17/380,057 priority patent/US20210351066A1/en
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法为，首先形成一第一凹槽以及一第二凹槽于一基底内，然后形成一衬垫层于第一凹槽以及第二凹槽内，形成一第一图案化掩模于该基底上并覆盖第二凹槽，去除第一凹槽内的衬垫层，去除第一图案化掩模，之后再形成一绝缘层于第一凹槽以及第二凹槽内以形成一陷捕隔离结构于第一凹槽内以及一深沟槽隔离结构于第二凹槽内。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作深沟槽隔离结构(deep trench isolation)于基底以及一陷捕隔离结构(trap rich isolation)设于基底内并环绕该深沟槽隔离结构的方法。
背景技术
在无线射频(radio frequency,RF)集成电路应用中，例如RF选频装置(RF switchdevice)或功率放大器(power amplifier device)，其性能经常受到寄生表面电荷(parasitic surface charge)问题的影响。因为寄生表面电荷而产生谐波效应(harmoniceffect)，进而影响装置效能。有数种晶片制作工艺技术用以解决此问题，例如使用绝缘层上覆盖半导体层(semiconductor-on-insulator,SOI)的晶片将电荷与高电阻晶片基板互相隔离。然而现今采用SOI晶片的设计通常过于昂贵，因此如何在更低成本的情况下改良现有制作工艺提升元件整体效能并提供更有竞争力的产品即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法。首先形成一第一凹槽以及一第二凹槽于一基底内，然后形成一衬垫层于第一凹槽以及第二凹槽内，形成一第一图案化掩模于该基底上并覆盖第二凹槽，去除第一凹槽内的衬垫层，去除第一图案化掩模，之后再形成一绝缘层于第一凹槽以及第二凹槽内以形成一陷捕隔离结构于第一凹槽内以及一深沟槽隔离结构于第二凹槽内。
本发明另一实施例公开一种半导体元件，其主要包含一金属氧化物半导体晶体管设于基底上、一深沟槽隔离结构设于基底内并环绕金属氧化物半导体晶体管以及一陷捕隔离结构设于基底内并环绕深沟槽隔离结构。
依据本发明一实施例，深沟槽隔离结构较佳包含一衬垫层设于基底内以及一绝缘层设于衬垫层上，其中衬垫层上表面较佳切齐绝缘层上表面。陷捕隔离结构则仅由绝缘层所构成，其中衬垫层较佳包含氧化硅而绝缘层则较佳包含无掺杂多晶硅或氮化硅等介电材料。另外依据本发明又一实施例，陷捕隔离结构以及深沟槽隔离结构可依据产品需求包含相同深度或不同深度。
附图说明
图1至图5为本发明一实施例制作一半导体元件的方法示意图；
图6为本发明一实施例的一半导体元件的结构示意图；
图7为本发明一实施例的一半导体元件的结构示意图。
主要元件符号说明
12 基底 14 凹槽
16 凹槽 18 图案化掩模
20 第一掩模层 22 第二掩模层
24 衬垫层 26 图案化掩模
28 开口 30 绝缘层
32 陷捕隔离结构 34 深沟槽隔离结构
36 深N阱 38 P阱
40 栅极结构 42 栅极介电层
44 栅极材料层 46 间隙壁
48 源极/漏极区域 50 层间介电层
52 接触插塞 54 金属内连线
56 金属氧化物半导体晶体 58 金属栅极管
60 介质层 62 高介电常数介电层
64 功函数金属层 66 低阻抗金属层
68 气孔
具体实施方式
请参照图1至图5，图1至图5为本发明一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，其中基底12较佳为一具有高阻值的半导体基底，例如具有高阻值的硅基底，然后形成多个凹槽14、16于基底12内。在本实施例中，凹槽14较佳于后续制作工艺中经填入绝缘材料后形成深沟槽隔离结构用来隔离金属氧化物半导体晶体管，而环绕于最外围的凹槽16则于后续制作工艺中经填入绝缘材料后形成陷捕隔离结构用来隔离元件之间的噪声。
依据本发明一实施例，形成凹槽14、16的方式可先形成一掩模层(图未示)于基底12上，其中掩模层较佳包含一双层结构，例如更细部包含一第一掩模层20设于基底12表面以及一第二掩模层22设于第一掩模层20上。接着利用一图案化光致抗蚀剂(图未示)为掩模以例如蚀刻方式去除部分第二掩模层22、部分第一掩模层20以及部分基底12以形成凹槽14、16于基底12内，并同时将掩模层转换为一图案化掩模18。在本实施例中，第一掩模层20较佳包含氧化硅而第二掩模层22则包含氮化硅，但均不限于此。随后进行一氧化制作工艺氧化各凹槽14、16内的基底12侧壁以及基底12底部以形成衬垫层24于各凹槽14、16内。
如图2所示，接着形成另一图案化掩模26于图案化掩模18表面并覆盖凹槽14，其中图案化掩模26较佳具有开口28分别暴露出最外围的凹槽16。然后利用图案化掩模26为掩模进行一蚀刻制作工艺去除凹槽16内的所有衬垫层24并暴露出凹槽16内的基底12侧壁以及基底12底部。
接着如图3所示，先去除第一图案化掩模26，再形成一绝缘层30于凹槽14、16内以形成陷捕隔离结构32于凹槽16内以及深沟槽隔离结构34于凹槽14内。从细部来看，本实施例形成陷捕隔离结构32以及深沟槽隔离结构34的方法较佳先形成绝缘层30填满凹槽14、16并覆盖图案化掩模18表面，然后进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)制作工艺去除部分绝缘层30以及图案化掩模18，使剩余的绝缘层30上表面切齐基底12上表面并同时形成陷捕隔离结构32于凹槽16内以及深沟槽隔离结构34于凹槽14内。在本实施例中，绝缘层30较佳包含无掺杂多晶硅或氮化硅等绝缘材料，但均不限于此。
请接着参照图4至图5，其中图4为本发明接续图3制作半导体元件的剖面示意图，而图5则为图4的上视图。如图4所示，随后可进行后续晶体管制作工艺，例如可先依序形成一深阱区以及一阱区于基底12内，再形成栅极结构40以及源极/漏极区域48等晶体管元件于基底12上。
在本实施例中，深阱区以及阱区的导电型式可依据所制备的晶体管型态来调整，例如本实施例的深阱区较佳包含一深N阱36而阱区则较佳包含一P阱38，但均不局限于此。另外栅极结构40的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例先栅极制作工艺为例为例，可先依序形成一栅极介电层42或介质层、一由多晶硅所构成的栅极材料层44以及一选择性硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分栅极材料层44与部分栅极介电层42，然后剥除图案化光致抗蚀剂，以于基底12上形成各由图案化的栅极介电层42与图案化的栅极材料层44所构成的栅极结构40、20、22、24。
然后在各栅极结构40侧壁形成至少一间隙壁46，于间隙壁46两侧的基底12中形成源极/漏极区域48及/或外延层，并选择性于源极/漏极区域48及/或外延层的表面形成一金属硅化物(图未示)。在本实施例中，间隙壁46可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁以及一主间隙壁。其中偏位间隙壁与主间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。源极/漏极区域48可依据所置备晶体管的导电型式而包含不同掺质，例如在本实施例中可包含N型掺质。
接着先形成一选择性接触洞蚀刻停止层(图未示)覆盖栅极结构40表面，再形成一层间介电层50于接触洞蚀刻停止层上。之后可进行一图案转移制作工艺，例如可利用一图案化掩模去除栅极结构40旁的部分的层间介电层50以及部分接触洞蚀刻停止层以形成多个接触洞(图未示)并暴露出下面的源极/漏极区域48。然后再于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。接着进行一平坦化制作工艺，例如以化学机械研磨制作工艺去除部分金属材料以分别形成接触插塞52于各接触洞内电连接源极/漏极区域48。之后可进行后续金属内连线制作工艺以于层间介电层50上形成金属间介电层(图未示)以及金属内连线54分别连接各接触插塞52。至此即完成本发明优选实施例的半导体元件的制作。
请再同时参照图4及图5，图4及图5又揭露本发明一实施例的半导体元件的结构示意图。如图4及图5所示，本发明的半导体元件主要包含至少一金属氧化物半导体晶体管，例如金属氧化物半导体晶体管56设于基底12上，深沟槽隔离结构34设于基底12内并环绕金属氧化物半导体晶体管56以及陷捕隔离结构32设于基底12内并环绕深沟槽隔离结构34。
在本实施例中，各深沟槽隔离结构34包含一衬垫层24设于基底12内以及一绝缘层30设于衬垫层24上，其中衬垫层24为U型，衬垫层24上表面切齐绝缘层30上表面，且衬垫层24包含氧化硅而绝缘层30则包含无掺杂多晶硅或氮化硅等介电材料。相较于深沟槽隔离结构34由两种材料所构成，陷捕隔离结构32仅由单一绝缘层30所构成，且陷捕隔离结构32内的绝缘层30同样包含例如无掺杂多晶硅或氮化硅等介电材料。
另外需注意的是，陷捕隔离结构32以及深沟槽隔离结构34又可依据制作工艺或产品需求包含相同或不同深度，而所谓相同或不同深度可定义为陷捕隔离结构32中的绝缘层30底部切齐深沟槽隔离结构34中的绝缘层30底部或衬垫层24底部。以本实施例为例，陷捕隔离结构32中的绝缘层30底部虽较佳切齐深沟槽隔离结构34中的衬垫层24底部，但不局限于此，陷捕隔离结构32中的绝缘层30底部又可切齐深沟槽隔离结构34中的绝缘层30底部，此实施例也属本发明所涵盖的范围。
若陷捕隔离结构32以及深沟槽隔离结构34包含不同深度，则陷捕隔离结构32中的绝缘层30底部可选择低于深沟槽隔离结构34中的衬垫层30底部，或深沟槽隔离结构34中的衬垫层24底部可选择低于陷捕隔离结构32中的绝缘层30底部，这些变化型均属本发明所涵盖的范围。
请接着参照图6，图6为本发明一实施例依据后高介电常数介电层制作工艺将前述实施例中由多晶硅材料所构成的栅极结构40转换为金属栅极58的剖面示意图。如图6所示，本发明可于前述实施例形成层间介电层50后先进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分层间介电层50以及部分接触洞蚀刻停止层并暴露出由多晶硅材料所构成的栅极材料层44，使栅极材料层44上表面与层间介电层50上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构40转换为金属栅极58。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构40中的栅极材料层44甚至栅极介电层42，以于层间介电层50中形成凹槽(图未示)。
接着依序形成一选择性介质层60或栅极介电层、一高介电常数介电层62、一功函数金属层64以及一低阻抗金属层66于凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层66、部分功函数金属层64以及部分高介电常数介电层62以形成金属栅极58。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，所形成的各金属栅极58较佳包含一介质层60或栅极介电层、一U型高介电常数介电层62、一U型功函数金属层64以及一低阻抗金属层66。
在本实施例中，高介电常数介电层62包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层64较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层64可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层64可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层64与低阻抗金属层66之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层66则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
请再继续参照图7，图7为本发明一实施例的半导体元件的结构示意图。如图7所示，本发明可于图3将绝缘层30填入凹槽14、16内的同时分别形成气孔68于陷捕隔离结构32以及深沟槽隔离结构34内，或更具体而言形成气孔68于陷捕隔离结构32以及深沟槽隔离结构34的绝缘层30内。依据本发明一实施例，气孔68的设置有助于降低晶体管的电阻值，进而改善半导体元件，或更具体而言无线射频元件的选频效能(switch performance)。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，其特征在于，该方法包含：
形成一第一凹槽以及一第二凹槽于一基底内；
形成一衬垫层于该第一凹槽以及该第二凹槽内；
形成一第一图案化掩模于该基底上并覆盖该第二凹槽；
去除该第一凹槽内的该衬垫层；
去除该第一图案化掩模；以及
形成一绝缘层于该第一凹槽以及该第二凹槽内，以形成一陷捕隔离结构于该第一凹槽内以及一深沟槽隔离结构于该第二凹槽内。
2.如权利要求1所述的方法，另包含：
形成一掩模层于该基底上；以及
去除部分该掩模层以及部分该基底以形成一第二图案化掩模于该基底上以及该第一凹槽及该第二凹槽于该基底内。
3.如权利要求2所述的方法，其中该掩模层包含：
第一掩模层，设于该基底上；以及
第二掩模层，设于该第一掩模层上。
4.如权利要求3所述的方法，其中该第一掩模层包含氧化硅以及该第二掩模层包含氮化硅。
5.如权利要求1所述的方法，另包含进行一氧化制作工艺氧化该第一凹槽以及该第二凹槽的侧壁以形成该衬垫层。
6.如权利要求5所述的方法，其中该衬垫层包含氧化硅。
7.如权利要求2所述的方法，还包含：
形成该第一图案化掩模于该第二图案化掩模上；以及
利用该第一图案化掩模为掩模去除该第一凹槽内的该衬垫层。
8.如权利要求1所述的方法，还包含：
在去除该第一图案化掩模后形成该绝缘层于该第一凹槽以及该第二凹槽内；以及
进行一平坦化制作工艺去除部分该绝缘层以形成该陷捕隔离结构以及该深沟槽隔离结构。
9.如权利要求1所述的方法，其中该绝缘层包含无掺杂多晶硅或氮化硅。
10.如权利要求1所述的方法，还包含形成一第一气孔于该陷捕隔离结构内以及一第二气孔于该深沟槽隔离结构内。
11.如权利要求1所述的方法，其中该第一凹槽以及该第二凹槽包含相同深度。
12.如权利要求1所述的方法，其中该第一凹槽以及该第二凹槽包含不同深度。
13.一种半导体元件，其特征在于，包含：
金属氧化物半导体晶体管，设于一基底上；
深沟槽隔离结构，设于该基底内并环绕该金属氧化物半导体晶体管；以及
陷捕隔离结构，设于该基底内并环绕该深沟槽隔离结构。
14.如权利要求13所述的半导体元件，其中该深沟槽隔离结构包含：
衬垫层，设于该基底内；以及
绝缘层，设于该衬垫层上，其中该衬垫层上表面切齐该绝缘层上表面。
15.如权利要求14所述的半导体元件，其中该衬垫层为U型。
16.如权利要求14所述的半导体元件，其中该衬垫层包含氧化硅且该绝缘层包含无掺杂多晶硅或氮化硅。
17.如权利要求13所述的半导体元件，其中该陷捕隔离结构包含无掺杂多晶硅或氮化硅。
18.如权利要求13所述的半导体元件，另包含第一气孔，设于该陷捕隔离结构内；以及第二气孔，设于该深沟槽隔离结构内。
19.如权利要求13所述的半导体元件，其中该陷捕隔离结构以及该深沟槽隔离结构包含相同深度。
20.如权利要求13所述的半导体元件，其中该陷捕隔离结构以及该深沟槽隔离结构包含不同深度。
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