CN109216191A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN109216191A
CN109216191A CN201710516576.7A CN201710516576A CN109216191A CN 109216191 A CN109216191 A CN 109216191A CN 201710516576 A CN201710516576 A CN 201710516576A CN 109216191 A CN109216191 A CN 109216191A
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fin structure
semiconductor element
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CN109216191B (zh
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林俊豪
陈信宇
谢守伟
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Blue Gun Semiconductor Co ltd
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United Microelectronics Corp
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Priority to US15/660,991 priority patent/US9953880B1/en
Priority to US15/917,859 priority patent/US10141228B1/en
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Abstract

本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法包括，首先形成一鳍状结构于基底上，然后形成一浅沟隔离于鳍状结构周围，形成一栅极层于鳍状结构及浅沟隔离上，去除部分栅极层、部分鳍状结构以及部分浅沟隔离以形成一开口，之后再形成一介电层于开口内以形成一单扩散隔离结构。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种分隔鳍状结构以形成单扩散隔离(single diffusion break,SDB)结构的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
在现行的鳍状场效晶体管元件制作工艺中，鳍状结构周围形成浅沟隔离后通常会以蚀刻方式去除部分鳍状结构与浅沟隔离形成凹槽，然后填入绝缘物以形成单扩散隔离结构并将鳍状结构分隔为两部分。然而现今单扩散隔离结构与金属栅极的制作工艺在搭配上仍存在许多问题，因此如何改良现有鳍状场效晶体管制作工艺与架构即为现今一重要课题。
发明内容
为解决上述问题，本发明一实施例公开一种制作半导体元件的方法。首先形成一鳍状结构于基底上，然后形成一浅沟隔离于鳍状结构周围，形成一栅极层于鳍状结构及浅沟隔离上，去除部分栅极层、部分鳍状结构以及部分浅沟隔离以形成一开口，之后再形成一介电层于开口内以形成一单扩散隔离结构。
本发明另一实施例公开一种半导体元件，其主要包含一鳍状结构设于一基底上、一单扩散隔离结构设于鳍状结构内并将该鳍状结构分隔为第一部分与第二部分、一栅极结构设于该第一部分上以及一接触洞蚀刻停止层设于栅极结构旁并延伸至单扩散隔离结构上。
附图说明
图1至图10为本发明一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 浅沟隔离 18 栅极介电层
20 栅极层 22 图案化掩模
24 开口 26 开口
28 第一部分 30 第二部分
32 介电层 34 单扩散隔离结构
36 第一硬掩模 38 第二硬掩模
40 图案化掩模 42 栅极结构
44 遮盖层 46 第一间隙壁
48 第二间隙壁 50 源极/漏极区域
52 接触洞蚀刻停止层 54 层间介电层
56 凹槽 58 介质层
60 高介电常数介电层 62 功函数金属层
64 低阻抗金属层 66 金属栅极
68 硬掩模 70 接触插塞
具体实施方式
请参照图1至图2，其中图1为本发明一实施例制作一半导体元件的上视图，图2左半部为图1中沿着切线AA'的剖面示意图，图2右半部则为图1中沿着切线BB'的剖面示意图。如图1至图2所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板。然后形成多个鳍状结构14于基底12上。在本实施例中，设于基底12上的鳍状结构14虽以四根为例，但所设置的鳍状结构数量均可依据产品需求任意调整，并不局限于此。
依据本发明的优选实施例，鳍状结构14较佳通过侧壁图案转移(sidewall imagetransfer,SIT)等技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构14。另外，鳍状结构14的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构14。这些形成鳍状结构14的实施例均属本发明所涵盖的范围。
然后形成一浅沟隔离(shallow trench isolation,STI)16环绕鳍状结构14。在本实施例中，形成浅沟隔离16的方式可先利用一可流动式化学气相沉积(flowable chemicalvapor deposition,FCVD)制作工艺形成一氧化硅层于基底12上并完全覆盖鳍状结构14。接着利用化学机械研磨(chemical mechanical polishing,CMP)制作工艺并搭配蚀刻制作工艺去除部分氧化硅层，使剩余的氧化硅层低于鳍状结构14表面以形成浅沟隔离16。
接着依序形成一栅极介电层18以及一栅极层20并完全覆盖于鳍状结构14与浅沟隔离16上，然后形成一图案化掩模22于栅极层20上，其中图案化掩模22具有一开口24暴露出部分栅极层20表面。在本实施例中，栅极介电层18较佳包含氧化硅，栅极层20则可选自由非晶硅以及多晶硅所构成的群组。另外图案化掩模22可包含一有机介电层(organicdielectric layer,ODL)、一含硅硬掩模与抗反射(silicon-containing hard maskbottom anti-reflective coating,SHB)层以及一图案化光致抗蚀剂，且于图案化掩模22中形成开口24的步骤可利用图案化光致抗蚀剂为掩模去除部分含硅硬掩模与抗反射层与部分有机介电层来达成。
如图3所示，然后利用图案化掩模22为掩模进行一蚀刻制作工艺，依序去除部分栅极层20、部分栅极介电层18以及部分鳍状结构14以形成开口26，并同时将鳍状结构14分隔为两部分，包括位于开口26左侧的第一部分28与位于开口26右侧的第二部分30。
随后如图4所示，形成一平坦的介电层32于开口26内与栅极层20上，其中介电层32较佳填满开口26且介电层32上表面较佳高于栅极层20上表面。在本实施例中，介电层32与浅沟隔离16较佳包含不同材料，例如填入开口26内的介电层32较佳包含氮化硅而浅沟隔离16包含氧化硅，但不局限于此，依据本发明一实施例介电层32又可与浅沟隔离16选用相同材料，例如同样包含氧化硅，此实施例也属本发明所涵盖的范围。
请接着参照图5与图6，图5为接续图4制作半导体元件的上视图，图6左半部为图5中沿着切线CC'的剖面示意图，图6右半部则为图5中沿着切线DD'的剖面示意图。如图5至图6所示，然后进行一平坦化制作工艺，例如利用化学机械研磨制作工艺去除部分介电层32并使剩余的介电层32上表面约略切齐栅极层20上表面，由此形成一单扩散隔离结构34突出于鳍状结构14，并约略切齐栅极层20上表面。如图5的上视图所示，各鳍状结构14较佳沿着一第一方向(例如X方向)延伸而单扩散隔离结构34则较佳沿着一第二方向(例如Y方向)延伸横跨鳍状结构并同时将各鳍状结构分隔为两部分，例如设于单扩散隔离结构34左侧的第一部分28与右侧的第二部分30。
如图7所示，随后对栅极层20进行一图案转移制作工艺，例如先依序形成一第一硬掩模36、第二硬掩模38以及一图案化掩模40于栅极层上且图案化掩模40较佳不覆盖单扩散隔离结构34。在本实施例中，第一硬掩模36与第二硬掩模38较佳包含不同材料，例如第一硬掩模36较佳包含氮化硅而第二硬掩模38较佳包含氧化硅，但不局限于此。图案化掩模40可包含单一图案化光致抗蚀剂，或可与图2所形成的图案化掩模22包含相同材料，例如可包含一有机介电层(organic dielectric layer,ODL)、一含硅硬掩模与抗反射(silicon-containing hard mask bottom anti-reflective coating,SHB)层以及一图案化光致抗蚀剂等三层结构，这些实施例均属本发明所涵盖的范围。
如图8所示，接着利用图案化掩模40为掩模进行一次或多次蚀刻制作工艺，依序去除部分第二硬掩模38、部分第一硬掩模36、部分栅极层20以及部分栅极介电层18，以于单扩散隔离结构34旁形成一栅极结构42。值得注意的是，在形成栅极结构42时单扩散隔离结构34上方并未形成任何栅极结构，但鳍状结构14的边缘处可设有虚置栅极(图未示)同时跨在鳍状结构14与浅沟隔离16上，虚置栅极上表面可切齐栅极结构42上表面，且以高度而言浅沟隔离16上表面较佳略低于鳍状结构14表面而单扩散隔离结构34上表面则同时高于鳍状结构14与浅沟隔离16上表面。此外，突出于鳍状结构14的单扩散隔离结构34会受此蚀刻制作工艺的影响而略低于栅极层20的上表面，但仍突出于鳍状结构14。随后可形成一遮盖层44于鳍状结构14上并覆盖栅极结构42与单扩散隔离结构34。在本实施例中，遮盖层44可包含氮化硅、氧化硅、氮氧化硅、氮碳化硅或其组合所构成，但不局限于此。
然后如图9所示，进行一蚀刻制作工艺去除部分遮盖层44以形成一第一间隙壁46于栅极结构42侧壁并同时形成第二间隙壁48于单扩散隔离结构34侧壁。接着于第一间隙壁46与第二间隙壁48两侧的鳍状结构14以及/或基底12中形成源极/漏极区域50及/或外延层(图未示)，并选择性于源极/漏极区域50及/或外延层的表面形成一金属硅化物(图未示)。在本实施例中，第一间隙壁46与第二间隙壁48虽分别以单一间隙壁为例，但又可各别为复合式间隙壁，例如可细部包含一偏位间隙壁以及一主间隙壁。其中偏位间隙壁与主间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。源极/漏极区域50可依据所置备晶体管的导电型式而包含不同掺质，例如可包含P型掺质或N型掺质。
随后形成一接触洞蚀刻停止层52于鳍状结构14表面并覆盖栅极结构42与单扩散隔离结构34，再形成一层间介电层54于接触洞蚀刻停止层52上。然后进行一平坦化制作工艺，例如利用化学机械研磨去除部分层间介电层54与部分接触洞蚀刻停止层52并暴露出由多晶硅材料所构成的栅极层20，使栅极层20上表面与层间介电层52上表面齐平。
随后进行一金属栅极置换制作工艺将栅极结构42转换为金属栅极。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除栅极结构42中的第二硬掩模38、第一硬掩模36、栅极层20甚至栅极介电层18，以于层间介电层54中形成凹槽56。
如图10所示，之后依序形成一选择性介质层58或栅极介电层、一高介电常数介电层60、一功函数金属层62以及一低阻抗金属层64于凹槽内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层64、部分功函数金属层62与部分高介电常数介电层60以形成金属栅极66。随后可去除部分低阻抗金属层64、部分功函数金属层64以及部分高介电常数介电层60以形成凹槽(图未示)，再填入一由例如氮化硅所构成的硬掩模68于凹槽内并使硬掩模68上表面切齐层间介电层54上表面。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，所形成的金属栅极66较佳包含一介质层58或栅极介电层、一U型高介电常数介电层60、一U型功函数金属层62以及一低阻抗金属层64。
在本实施例中，高介电常数介电层60包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层62较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层62可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或碳化钛铝(TiAlC)等，但不以此为限；若晶体管为P型晶体管，功函数金属层62可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层62与低阻抗金属层64之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层64则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
之后可进行一图案转移制作工艺，例如可利用一图案化掩模去除金属栅极66与单扩散隔离结构34旁的部分的层间介电层54以形成多个接触洞(图未示)并暴露出下面的源极/漏极区域50。然后再于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。之后进行一平坦化制作工艺，例如以化学机械研磨去除部分金属材料以分别形成接触插塞70于各接触洞内电连接源极/漏极区域50。至此即完成本发明优选实施例的半导体元件的制作。
请继续参照图10，图10另揭露本发明一实施例的一半导体元件的结构示意图。如图10所示，半导体元件主要包含一鳍状结构14设于基底12上，一单扩散隔离结构34设于鳍状结构14内且突出于鳍状结构14并将鳍状结构14分隔为第一部分28与第二部分30以及一栅极结构或金属栅极66设于第一部分28上，其中金属栅极66上表面可切齐或略高于单扩散隔离结构34上表面。在本实施例中，鳍状结构14沿着一第一方向延伸而单扩散隔离结构34沿着一第二方向延伸，且第一方向较佳垂直第二方向，例如图5的上视图所示。
此外，半导体元件又包含一第一间隙壁46设于金属栅极66侧壁、第二间隙壁48设于单扩散隔离结构34侧壁、接触洞蚀刻停止层52设于第一间隙壁46旁并延伸至第二间隙壁48与单扩散隔离结构34上且直接接触单扩散隔离结构34、以及源极/漏极区域50分别设于第一间隙壁46两侧的鳍状结构14或基底12内与第二间隙壁48两侧的鳍状结构14内。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种制作半导体元件的方法，包含：
形成一鳍状结构于一基底上；
形成一浅沟隔离于该鳍状结构周围；
形成一栅极层于该鳍状结构及该浅沟隔离上；
去除部分该栅极层、部分该鳍状结构以及部分该浅沟隔离以形成一开口；以及
形成一介电层于该开口内以形成一单扩散隔离结构。
2.如权利要求1所述的方法，另包含于形成该栅极层之前形成一栅极介电层于该鳍状结构上。
3.如权利要求1所述的方法，另包含：
形成一图案化掩模于该栅极层上；以及
利用该图案化掩模为掩模去除部分该栅极层、部分该栅极介电层以及部分该鳍状结构以形成该开口。
4.如权利要求1所述的方法，另包含：
形成该介电层于该开口内以及该栅极层上；
平坦化该介电层并使该介电层上表面切齐该栅极层上表面。
5.如权利要求1所述的方法，另包含：
在形成该单扩散隔离结构后去除部分该栅极层以于该单扩散隔离结构旁形成一栅极结构。
6.如权利要求1所述的方法，另包含：
形成一遮盖层于该栅极结构及该单扩散隔离结构上；以及
去除部分该遮盖层以形成一第一间隙壁于该栅极结构旁以及一第二间隙壁于该单扩散隔离结构旁。
7.如权利要求1所述的方法，其中该鳍状结构沿着一第一方向延伸且该单扩散隔离结构沿着一第二方向延伸。
8.如权利要求7所述的方法，其中该第一方向垂直该第二方向。
9.如权利要求1所述的方法，其中该栅极层包含多晶硅。
10.如权利要求1所述的方法，其中该栅极层包含非晶硅。
11.如权利要求1所述的方法，其中该介电层包含氮化硅。
12.如权利要求1所述的方法，其中该介电层包含氧化硅。
13.一种半导体元件，包含：
鳍状结构，设于一基底上；
单扩散隔离结构，设于该鳍状结构内并将该鳍状结构分隔为第一部分与第二部分；
栅极结构，设于该第一部分上；以及
接触洞蚀刻停止层，设于该栅极结构旁并延伸至该单扩散隔离结构上。
14.如权利要求13所述的半导体元件，另包含：
第一间隙壁，设于该栅极结构侧壁；以及
第二间隙壁，设于该单扩散隔离结构侧壁，其中该接触洞蚀刻停止层设于该第一间隙壁以及该第二间隙壁上。
15.如权利要求14所述的半导体元件，另包含一源极/漏极区域设于该第一间隙壁两侧的该基底内。
16.如权利要求14所述的半导体元件，另包含一源极/漏极区域设于该第二间隙壁两侧的该基底内。
17.如权利要求13所述的半导体元件，其中该鳍状结构沿着一第一方向延伸且该单扩散隔离结构沿着一第二方向延伸。
18.如权利要求17所述的半导体元件，其中该第一方向垂直该第二方向。
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US11901239B2 (en) 2018-01-17 2024-02-13 United Microelectronics Corp. Semiconductor device and method for fabricating the same
CN111769045A (zh) * 2019-04-01 2020-10-13 联华电子股份有限公司 半导体元件及其制作方法
CN111769045B (zh) * 2019-04-01 2024-04-02 联华电子股份有限公司 半导体元件及其制作方法
CN113345839A (zh) * 2020-03-02 2021-09-03 联华电子股份有限公司 半导体元件及其制作方法

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