CN109087889B - 在finfet装置中用于阈值电压控制的方法、设备及系统 - Google Patents

在finfet装置中用于阈值电压控制的方法、设备及系统 Download PDF

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CN109087889B
CN109087889B CN201810579685.8A CN201810579685A CN109087889B CN 109087889 B CN109087889 B CN 109087889B CN 201810579685 A CN201810579685 A CN 201810579685A CN 109087889 B CN109087889 B CN 109087889B
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CN109087889A (zh
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东乡光洋
蓝·阿斯拉
张兴
P·巴拉苏布拉马尼亚姆
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及在FINFET装置中用于阈值电压控制的方法、设备及系统，所揭示的是就多个晶体管装置用于控制阈值电压值的至少一种方法、设备及系统。判定第一晶体管栅极的第一阈值电压，该第一晶体管栅极包含具有第一长度的第一栅极通道。判定第二晶体管栅极的第二栅极通道的第二长度。基于该第二长度判定该第二栅极的程序调整，用于提供该第二晶体管栅极的第二阈值电压。该第二阈值电压是在该第一阈值电压的预定范围内。提供与程序调整有关的数据至处理控制器，用于进行该程序调整。

Description

在FINFET装置中用于阈值电压控制的方法、设备及系统
技术领域
本发明大体上是涉及尖端半导体装置的制造，并且更具体地说，是涉及就FinFET装置用于提供阈值电压控制的各种方法。
背景技术
诸如CPU、储存装置、ASIC(特定应用集成电路)及诸如此类的先进集成电路在制作时，需要根据指定的电路布局，在给定的芯片面积中，形成大量电路组件，其中所谓的金属氧化物场效晶体管(MOSFET或FET)代表一种重要的电路组件类型，其实质决定集成电路的效能。FET是一种装置，其典型包括源极区、漏极区、置于该源极区与该漏极区之间的通道区，以及置于该通道区上面的栅极电极。通过FET的电流流动是通过控制施加至栅极电极的电压来控制。若对栅极电极施加比装置的阈值电压更小的电压，则没有通过该装置的电流流动(略去非所欲的漏电流，其相对较小)。然而，对栅极电极施加与装置的阈值电压相等或比其更大的电压时，信道区变为具有导电性，并且允许电流穿过导电通道区在源极区与漏极区之间流动。
为了提升场效晶体管的运作速度，并且增加集成电路装置上场效晶体管的密度，装置设计人员多年来已大幅缩减场效晶体管的实体尺寸。更具体地说，FET的通道长度已显著缩减，已使FET的切换速度获得提升。然而，缩减FET的通道长度亦缩减源极区与漏极区之间的距离。在一些情况下，缩减源极与漏极之间的间隔会造成难以有效率地使通道的电位免于因漏极的电位而受到负面影响。这有时称为所谓的短通道效应，其中FET作为主动开关的特性会降低。
与具有平面结构的平面型FET相比，有所谓的3D装置，诸如说明性FinFET装置，其是一种3维结构。更具体地说，在FinFET中，形成大体上垂直而置的鳍形主动区，而且栅极电极将鳍形主动区的侧边及上表面两者都包围，用以形成三闸结构，为的是要使用具有3维结构而非平面结构的信道。在一些情况下，绝缘覆盖层(例如：氮化硅)是置于鳍片的顶端，并且FinFET装置仅具有双闸结构。
FinFET设计使用可使用选择性蚀刻程序在半导体晶圆的表面上形成的「鳍片」。鳍片可用于在晶体管的栅极与源极与漏极之间形成隆起通道。接着沉积栅极，使得其环绕鳍片以形成三闸结构。由于通道极薄，栅极对里面的载子一般会具有更大的控制。然而，当晶体管切换为接通时，通道的形状可限制电流的流动。因此，可平行使用多个鳍片以提供更大的电流流动使驱动强度提升。
图1绘示目前FinFET装置的特写截面图。图1所示的FinFET装置100包含多个「鳍片」110。该半导体装置可朝垂直取向安置，建立一或多个鳍片110。该FinFET的源极与漏极是沿着鳍片水平置放。高k金属栅极120环绕于鳍片上方，将其三个侧边包覆。栅极120界定FinFET装置的长度。顺着与半导体晶圆的平面平行的方向沿着正交晶面出现电流流动。鳍片的电气有效高度(标示为H)典型为通过鳍片显露步骤中的氧化物凹陷量来测定，因此，所有鳍片110都固定。
鳍片的厚度(标示为Tfi)判定晶体管装置的短信道行为，并且通常比鳍片110的高度H还小。鳍片之间距(标示为P)是通过微影限制条件来测定，并且指定要实施所欲装置宽度的晶圆区。若间距P值小且高度H值大，则能实现每平方面积的较佳装置堆积，导致设计更稠密，或硅晶圆区使用更有效率。
集成电路有比例缩小的趋势，以利支持不断缩减的电子装置。这已促使设计人员缩减finFET装置的尺寸。如此，finFET装置中鳍片的间距得以缩减，使finFET装置的密度增加。如此，在许多情况下，以紧密靠近的方式形成包含多个finFET晶体管的装置，这些晶体管有不同的栅极长度或通道长度。在许多装置中，源极与漏极之间的通道宽度缩减，可能出现所谓的短通道效应。这可能造成装置彼此间阈值电压(VT)出现变异。
随着栅极通道的长度缩减，VT也可能改变。因此，含有具不同栅极通道长度、不同阈值电压的晶体管的装置可适用于不同晶体管。亦即，相比于更短信道装置的阈值电压，长信道装置彼此间可有明显的阈值电压差异。这可能例如对于给定电压造成效能问题，有一些晶体管可变为启动，而其它则停住，需要在功率消耗与空间消耗方面代价高昂的补偿电路。
本发明可因应及/或至少减少以上指认的其中一或多个问题。
发明内容
以下介绍本发明的简化概要，以便对本发明的一些态样有基本的了解。本概要并非本发明的详尽概述。用意不在于指认本发明的重要或关键要素，或叙述本发明的范畴。目的仅在于以简化形式介绍一些概念，作为下文更详细说明的引言。
大体上，本发明是针对就多个晶体管装置用于控制阈值电压值的各种方法、设备及系统。判定第一晶体管栅极的第一阈值电压，该第一晶体管栅极包含具有第一长度的第一栅极通道。判定第二晶体管栅极的第二栅极通道的第二长度。基于该第二长度判定该第二栅极的程序调整，用于提供该第二晶体管栅极的第二阈值电压。该第二阈值电压是在该第一阈值电压的预定范围内。提供与程序调整有关的数据至处理控制器，用于进行该程序调整。
附图说明
本发明可搭配所附图式参照以下说明来了解，其中相似的组件符号表示相似的组件，并且其中：
图1绘示目前FinFET装置的特写图；
图2根据本文中的具体实施例，绘示半导体装置的透视图的特写图；
图3根据本文中的具体实施例，绘示沿着图2的装置的第一区段取看的截面图的特写图；
图4根据本文中的具体实施例，绘示图2的装置进一步顺着程序的截面图的特写图；
图5根据本文中的具体实施例，绘示finFET装置的特写、简化俯视图；
图6绘示具有PRVT特性及习知功函数金属层的两个finFET的特写截面图；
图7根据本文中的一具体实施例，绘示具有PRVT特性及功函数金属层的两个finFET的特写截面图；
图8绘示具有NRVT特性及习知功函数金属层的两个finFET的特写截面图；
图9根据一项具体实施例，绘示具有NRVT特性及功函数金属层的finFET的特写截面图；
图10根据另一具体实施例，绘示具有NRVT特性及功函数金属层的finFET的特写截面图；
图11根据一项具体实施例，绘示具有PRVT特性及相反极性功函数金属层的finFET的特写截面图；
图12根据另一具体实施例，绘示具有PRVT特性及相反极性功函数金属层的finFET的特写截面图；
图13根据本文中的具体实施例，绘示半导体装置上栅极切口区的俯视图的特写图；
图14根据本文中的具体实施例，绘示用于对具有不同栅极信道长度的诸装置调整阈值电压的程序的流程图；以及
图15根据本文中的具体实施例，绘示用于制作半导体装置的系统的特写图，该半导体装置具有不同栅极信道长度finFET装置及预定范围内的阈值电压。
尽管本文所揭示的申请目标易受各种修改和替代形式所影响，其特定具体实施例已通过图式中的实施例予以表示并且在本文中予以详述。然而，应了解的是，本文中特定具体实施例的说明用意不在于将本发明限制于所揭示的特定形式，相反地，如随附权利要求书所界定，用意在于涵盖落于本发明的精神及范畴内的所有修改、均等例及替代方案。再者，所提供的图式未依照比例绘制。
主要组件符号说明
100 FinFET装置
110、510 鳍片
120 高k金属栅极、栅极
500 半导体装置、装置、晶体管
501、605、605a、605b、705a、705b、805a、805b、905a、905b、1105a、1105b衬底
502 基础层、层
510C 中央部分
510E 末端部分
511 漏极与源极区
512 覆盖层
520 栅极电极结构
521 侧壁间隔物结构、结构
522 栅极电极材料、电极材料
600、700、800、900、1100装置、第一装置
601、701、801、901、1101装置、第二装置
603源极/漏极鳍片、鳍片
622a、622b、722a、722b、822a、822b、922a、922b、1122a、
1122b源极区
624a、624b、724a、724b、824a、824b、924a、924b、1124a、
1124b漏极区
630a、630b、640、645、730a、730b、830a、830b、930a、930b、1130a、1130b栅极
645a、645b、745a、745b、845a、845b、945b、1145b高k衬垫650、650a、650b功函数材料、WFM特征
660切割线路
660a、660b、760a、760b、860a、860b、960a、960b、1160a、
1160b栅极填充区
670、770、870、970、1270光晕层
750a、750b、850a、850b、950a、950b、1150a、1150b WFM特征、WFM
855a、855b、955a、955b衬垫层、内层、层
1300 集成电路
1310 栅极形成体、栅极
1320 源极/漏极(S/D)形成体
1330 衬底层
1340、1342栅极切口区
1410至1470步骤1500 系统
1510 半导体装置处理系统、处理系统
1515 集成电路或装置
1520 处理控制器
1540 设计单元
1550 输送机构
H 高度
Tfi 厚度
P 间距。
具体实施方式
下面说明本发明的各项说明性具体实施例。为了澄清，本说明书中并未说明实际实作态样的所有特征。当然，将会领会的是，在开发任何此实际具体实施例时，必须作出许多实作态样特定决策才能达到开发者的特定目的，例如符合系统有关及业务有关的限制条件，这些限制条件会随实作态样不同而变。此外，将会领会的是，此一开发努力可能复杂且耗时，虽然如此，仍会是受益于本发明的所属领域技术人员的例行工作。
本申请目标现将参照附图来说明。各种结构、系统及装置在图式中只是为了阐释而绘示，为的是不要因所属领域技术人员众所周知的细节而混淆本发明。虽然如此，仍将附图包括进来以说明并阐释本发明的说明性实施例。本文中使用的字组及词组应了解并诠释为与所属领域技术人员了解的字组及词组具有一致的意义。与所属领域技术人员了解的通常及惯用意义不同的词汇或词组(即定义)的特殊定义，用意不在于通过本文词汇或词组的一致性用法提供暗示。就一词汇或词组用意在于具有特殊意义的方面来说，即有别于所属领域技术人员了解的意义，此一特殊定义将会按照为此词汇或词组直接且不含糊地提供此特殊定义的定义方式，在本说明书中明确提出。
本文中的具体实施例是用来形成包含具不同栅极信道长度的finFET的装置，以及提供预定变异内的各别阈值电压。举例而言，本文中的具体实施例是用来形成包含具有不同栅极通道的多个finFET装置的装置，其中该等finFET装置包含不同对应的功函数特性。各种功函数特性可补偿不同栅极通道长度，使得各个finFET装置的阈值电压处在预定范围内。因此，本文中的具体实施例提供具有类似阈值电压的不同栅极信道长度的finFET装置。
在一些具体实施例中，为了提供实质均匀的阈值电压，在装置的栅极部分的形成期间，功函数特性经调制为功函数材料的厚度。在其他具体实施例中，为了提供实质均匀的阈值电压，功函数特性经调制为当作功函数层使用的材料的类型。在又其它具体实施例中，为了提供实质均匀的阈值电压，可调制或消除相邻源极与漏极区所形成的光晕层。「实质均匀的阈值电压」一词可指称为处在电压值预定范围内的阈值电压。本文中所述的具体实施例可因应具有不同栅极长度的装置中与阈值电压差异相关联的问题。再者，诸如栅极线与空间间距的栅极设计差异等可造成阈值电压差异的其它因素亦可使用本文中提供的具体实施例，通过调整阈值电压来因应。
图2至4根据本文中的具体实施例，绘示与进行形成finFET装置的初始程序有关的各种特写图。图2示意性绘示半导体装置500的透视图，其可以是包含多个鳍片的finFET装置。在所示制造阶段中，装置500可包含衬底501，诸如硅衬底或任何其它适当的载体材料，其上可形成适当的基础层502，其在一些说明性具体实施例中可代表绝缘层，诸如二氧化硅层、氮化硅层、氮氧化硅层及类似者。举例而言，若衬底501可由实质结晶半导体材料所构成，基础层502(若以绝缘材料的形式提供)及衬底501可界定绝缘体上硅(SOI)组态。
此外，多个鳍片510是在层502上形成，并且包含各别末端部分510E及中央部分510C，其是通过栅极电极结构520所包覆。再者，至少可在鳍片510的侧壁上形成栅极绝缘材料(图2未示)，而若考虑三闸晶体管架构，可在鳍片510的顶端表面上形成对应栅极绝缘层。在其它例子中，鳍片510可通过覆盖层(图未示)所包覆，其可导致连至鳍片510的电容性耦合不足，以致其顶端表面可能无法有效充当通道区。关于鳍片510的任何材料组成，要领会的是，可使用任何适当的材料，诸如硅、硅/锗、锗或任何其它适当的半导体化合物，端视总体装置要求而定。类似的是，鳍片510的对应尺寸可根据所考虑对应技术节点的设计规则来选择。
图3绘示沿着图2的区段IIb取看的截面图的特写图。如图所示，可在鳍片510与栅极电极结构520上形成覆盖层512，诸如氧化硅层或高K HFO2层及/或类似者。栅极电极结构520可由诸如多晶硅、含金属材料及类似者等适当的材料所构成，可在覆盖层512上形成，并且亦可沿着鳍片510的对应侧壁(图3的区段中未示)向下延展至层502。如图2及3所示的半导体装置500可基于建置良好的程序技巧来形成，举例来说，亦如以上参照装置500所阐释。
图4绘示晶体管500在更晚期制造阶段时的透视图的特写图。如图所示，栅极电极结构520可包含侧壁间隔物结构521，其可由诸如氮化硅、二氧化硅及类似者等任何适当的材料所构成。该间隔物结构可基于建置良好的沉积与蚀刻技巧来形成，其中间隔物结构521的宽度可根据鳍片510的各末端部分510E中的所欲掺质分布来选择。亦即，相邻于栅极电极结构520的末端部分510E中可建立适度高掺质浓度，有可能使用偏移间隔物组件(图未示)来建立，之后，可提供结构521的一或多个间隔物组件，并且可在一或多个后续布植步骤期间将其当作布植掩膜使用，以在对栅极电极结构520的栅极电极材料522具有侧向距离的末端部分510E中提供所欲高掺质浓度。应领会的是，通过在结构521中适当地形成对应数目的间隔物组件，可建立延展自电极材料522的任何适当的浓度分布。应进一步领会的是，可进行任何其它布植程序，举例来说，关于在中央部分510C附近界定反掺杂区，该反掺杂区代表实际通道区。可在相反安置的末端部分510E处形成漏极与源极区511，该等末端部分相对中央部分510C具有所欲掺质浓度与浓度梯度。基于就图2至4所示的概念，可形成具有各种栅极通道长度的各个finFET装置。运用本文中提供的具体实施例所例示的一或多种概念，具有各种栅极通道长度的各个finFET装置可显示实质类似的阈值电压值。
现请参阅图5，根据本文中的具体实施例，所绘示的是finFET装置的特写、简化俯视图。图5绘示装置600，其包含形成于衬底605上的多个源极/漏极鳍片603，与图4所示的实施例类似。再者，图5绘示多个栅极，例如：栅极640与栅极645。栅极640、645可由功函数材料层650所围绕。图5展示切割线路660，其中图6至12就切割线路660表示finFET装置的特写截面图。
在一些具体实施例中，可将晶体管装置的阈值电压区分成六类：PFET规则电压阈值(PRVT)；PFET低电压阈值(PLVT)；PFET超低电压阈值(PSLVT)；NFET规则电压阈值(NRVT)；NFET低电压阈值(NLVT)；NFET超低电压阈值(NSLVT)。在一些具体实施例中，PRVT与NRVT的绝对值可约为0.25伏特，PLVT与NLVT的绝对值可约为0.20伏特，以及PSLVT与NSLVT的绝对值可约为0.15伏特，其中可施加其它电压位准，但仍在本发明的精神内。所属领域技术人员将轻易理解的是，上列电压阈值是以绝对值的方式来提供，以及PFET装置大体上将具有负VT值，而NFET装置大体上将具有正VT值。本文中的具体实施例是用来提供就复数种栅极通道宽度间的不同阈值电压类别维持实质一致的阈值电压。
现请参阅图6，所示为具有PRVT特性及习知功函数金属层的两个finFET的特写截面图。图6包含图6的(a)部分所示的第一装置600及图6的(b)部分所示的第二装置601。装置600包含衬底605a、栅极630a、源极区622a以及漏极区624a。大体上，源极/漏极区622a、622b、624a、624b是由所谓的光晕层670所围绕，如图6所示。
装置601包含衬底605b、栅极630b、源极区622b以及漏极区624b。各装置600、601包含位在栅极电极内的金属，大体上称为功函数金属(work-function metal；WFM)。栅极630a包含高k衬垫645a、WFM特征650a与栅极填充区660a，其可填充有钨。类似的是，栅极630b包含高k衬垫645b、WFM特征650b与栅极填充区660b。
如图6所示，栅极630a的通道长度比栅极630b的通道长度相对更小。如此，栅极填充区660b比栅极填充区660a更宽。在诸如图6所示的装置600、601等习知装置中，WFM特征650a、650b有类似的厚度及材料类型。此习知组态可造成装置600的阈值电压与装置601的阈值电压明显不同。
现请参阅图7，根据本文中的具体实施例，所示为具有PRVT特性及功函数金属层的两个finFET的特写截面图。图7包含图7的(a)部分所示的第一装置700及图7的(b)部分所示的第二装置701。装置700包含衬底705a、栅极730a、源极区722a以及漏极区724a。类似的是，装置701包含衬底705b、栅极730b、源极区722b以及漏极区724b。在一些具体实施例中，图6至12所示的源极与漏极区可对应于第5图的鳍片603。
在一项具体实施例中，源极/漏极区722a、722b、724a、724b可由所谓的光晕层770所围绕，类似于图6的光晕层670。在其他具体实施例中，可省略光晕层770的沉积，其中源极/漏极区722a、722b、724a、724b将不由光晕层所围绕。
栅极730a包含高k衬垫745a、功函数金属(WFM)特征750a与栅极填充区760a，其在一项具体实施例中，可填充有钨。类似的是，栅极730b包含高k衬垫745b、WFM特征750b与栅极填充区760b。
如图7所示，栅极730a的通道长度比栅极730b的通道长度相对更小。如此，栅极填充区760b比栅极填充区760a更宽。在一项具体实施例中，相比于WFM 750b，WFM 750a具有不同厚度。举例而言，WFM 750b的厚度可比WFM 750a的厚度大一预定量，以顾及装置701的栅极信道增加。在一项具体实施例中，相对装置700的栅极信道长度，WFM 750b的厚度增加(从WFM 750a的基线厚度起增加)可与装置701的栅极信道长度增加成比例。在一些具体实施例中，可增加WFM 750b的厚度，使得栅极填充区760b与栅极填充区760a实质相同。按照这种方式，装置701因其栅极通道尺寸增加所致的阈值电压变化可减少或实质降到最小，以使短信道装置700与长信道装置701有实质类似的阈值电压。
现请参阅图8，所示为具有NRVT特性及习知功函数金属层的两个finFET的特写截面图。图8包含图8的(a)部分所示的第一装置800及图8的(b)部分所示的第二装置801。装置800包含衬底805a、栅极830a、源极区822a以及漏极区824a。装置801包含衬底805b、栅极830b、源极区822b以及漏极区824b。大体上，源极/漏极区822a、822b、824a、824b是由光晕层870所围绕，如图8所示。
装置801包含栅极830b、源极区822b以及漏极区824b。各装置800、801包含位在栅极电极内的金属，俗称功函数金属(WFM)。装置800的栅极830a包含高k衬垫845a、WFM特征650a、内层855a(诸如钛组合层，例如：TiAl或TiAlC)与栅极填充区860a，其可填充有钨。类似的是，装置801的栅极830b包含高k衬垫845b、内层855b、WFM特征850b以与栅极填充区860b。
如图8所示，栅极830a的通道长度比栅极830b的通道长度相对更小。如此，栅极填充区860a比栅极填充区860b更宽。在诸如图8所示的装置800、801等习知装置中，WFM特征850a、850b有类似的厚度及材料类型。此习知组态可造成装置800的阈值电压与装置801的阈值电压明显不同。
现请参阅图9及10，根据本文中的具体实施例，所示为具有NRVT特性及功函数金属层的finFET的特写截面图。图9及10各包含图9的(a)部分所示的第一装置900及图10的(b)部分所示的第二装置901。装置900包含衬底905a、栅极930a、源极区922a以及漏极区924a。装置901包含衬底905b、栅极930b、源极区922b以及漏极区924b。在一项具体实施例中，图9的源极/漏极区922a、922b、924a、924b可由光晕层970所围绕，类似于图6的光晕层670。在其他具体实施例中，如图10所例示，可省略光晕层970的沉积，其中图10中源极/漏极区922a、922b、924a、924b将不由光晕层所围绕。在一些具体实施例中，图9的光晕层可仅在一个装置900或另一装置901上形成，用于达到预定范围内的阈值电压位准。
栅极930b包含高k衬垫945b、功函数金属(WFM)特征950b以及内层955b，诸如钛组合层，例如：TiAl或TiAlC。再者，WFM 950a(请参阅(a)部分)及层955a内形成栅极填充区960a，其在一项具体实施例中，可填充有钨。类似的是，栅极930b包含高k衬垫945b、WFM特征950b、钛组合层955b与栅极填充区960b。
如图9所示，栅极930a的通道长度比栅极930b的通道长度相对更小。如此，栅极填充区960b比栅极填充区960a更宽。在一项具体实施例中，相比于WFM 950b，WFM 950a具有不同厚度。举例而言，WFM 950b的厚度可增加一预定量，以顾及装置901的栅极信道增加。在一项具体实施例中，相对装置900、901的栅极通道长度，WFM 950b的厚度增加(从WFM 950a的基线厚度起增加)可与装置901的栅极信道长度增加成比例。
在一些具体实施例中，可增加WFM 950b的厚度，使得WFM 950b对栅极填充区960b的比例有别于WFM 950b对栅极填充区960b的比例。因此，在一项具体实施例中，对于NRVT装置中的小栅极通道长度，可使用较薄的WFM，其中可将更厚的WFM用于更大的栅极通道长度，以使介于那两个装置之间的VT保持类似。
按照这种方式，可对栅极通道长度的变化进行补偿，使得装置901的阈值电压相比于装置900的VT因其栅极通道尺寸增大所致的变化可以降低或实质降到最小。再者，在一些具体实施例中，对于NSLVT装置，可调整图9及10的类似WFM厚度以提供实质类似的VT值。
现请参阅图11及12，根据本文中的具体实施例，所示为具有PRVT特性及相反极性功函数金属层的finFET的特写截面图。大体上，处理finFET装置时可使用两种类型的功函数金属(WFM)：用于p信道装置的第一WFM及用于n信道装置的第二WFM。大体上，关于影响电压阈值，对PFET装置施加大有效功函数(即第一WFM)，其可对NFET装置指出大阻障高度。相比之下，大体上，关于影响电压阈值，对NFET装置施加小有效功函数(即第二WFM)，其可对PFET装置指出大阻障高度。关于WFM的「极性」一词大体上是指用于PFET装置的有效WFM类型与用于NFET装置的有效WFM类型的相对关系，因为PFET与NFET大体上视为相反极性。因此，在一些具体实施例中，「相反极性的WFM」一词可指称为使用位在PFET装置上的第二WFM以及位在NFET装置上的第一WFM。诸如掺杂程序、合金化程序、退火程序、离子布植程序等一或多个程序可影响有效WFM，并从而影响WFM极性。
图11及12各包含图11与12的(a)部分所示的第一装置1100及第11与12图的(b)部分所示的第二装置1101。装置1100包含衬底1105a、栅极1130a、源极区1122a以及漏极区1124a。类似的是，装置1101包含衬底1105b、栅极1130b、源极区1122b以及漏极区1124b。在一项具体实施例中，图12的源极/漏极区1122a、1122b、1124a、1124b可由光晕层1270所围绕，类似于图6的光晕层670。在其他具体实施例中，如图11所例示，可省略光晕层1270的沉积，其中源极/漏极区1122a、1122b、1124a、1124b将不由光晕层所围绕。
栅极1130b包含高k衬垫1145b、功函数金属(WFM)特征1250b。再者，WFM 1150a(请参阅(a)部分)及层1155a内形成栅极填充区1160a，其在一项具体实施例中，可填充有钨。类似的是，栅极1130b包含高k衬垫1145b、WFM特征1150b、钛组合层1155b与栅极填充区1160b。
如图11所示，栅极1130a的通道长度比栅极1130b的通道长度相对更小。如此，栅极填充区1160b比栅极填充区1160a更宽。在一项具体实施例中，相比于WFM 1150b，WFM 1150a具有不同厚度。举例而言，WFM 1150b的厚度可增加一预定量，以顾及装置1101的栅极信道差异。在一项具体实施例中，相对装置1100、1101的栅极通道长度，WFM 1150b的厚度增加(从WFM 1150a的基线厚度起增加)可与装置1101的栅极信道长度增加成比例。因此，相对于薄WFM层1150b，装置1100的WFM 1150a可以是更薄的层。再者，相比于WFM 1150b，WFM 1150a可具有不同极性。在一项具体实施例中，装置1100、1101其中一者的极性差异结合WFM层1150a、1150b的厚度变化可修改VT，使得装置1100、1101的阈值电压可在预定变异范围内。
在一些具体实施例中，VT的预定变异可约为10％；因此，对于约0.250伏特的VT，预定可接受差异可约为0.025伏特。
在一些具体实施例中，可将WFM 1150b的厚度从「更薄」层级增加至「薄」层级，使得WFM 1150b对栅极填充区1160b的比例有别于WFM 1150b对栅极填充区1160b的比例。在一些具体实施例中，「薄」层级WFM可约为30-40A(例如：TiN)，「更薄」层级可低于30A，而「厚」层级可约为40-50A。因此，在一项具体实施例中，对于PRVT装置中的小栅极通道长度，可使用较薄的WFM，其中可将薄WFM用于更大的栅极通道长度，以使介于那两个装置之间的VT保持类似。按照这种方式，可对栅极通道长度的变化进行补偿，使得装置1101的阈值电压相比于装置1100的VT因其栅极通道尺寸增大所致的变化可以降低或实质降到最小。
在一些具体实施例中，类似于通过使用不同极性的WFM层来控制具有不同信道长度的PFET装置的阈值电压，可通过使用不同极性的WFM层，使具有不同通道长度的NFET的阈值电压在预定容差等级内。
现请参阅图13，根据本文中的具体实施例，所示为半导体装置上栅极切口区的俯视图的特写图。形成集成电路1300，其中可在衬底层(例如：非晶硅)1330上形成多个栅极形成体1310。可在栅极形成体1310周围形成栅极间隔物。再者，形成多个源极/漏极(S/D)形成体1320。可在S/D鳍片320上形成磊晶(EPI)形成体325(N型及P型)。
图13亦展示两个例示性栅极切口区1340、1342。在一些具体实施例中，栅极切口区1340、1342的定位可影响电路1300的装置的阈值电压。可在栅极切口1340、1342的位置处切割栅极1310。就影响待处理装置的阈值电压(例如：设计程序期间)而言，栅极切割的位置可在形成栅极前先判定。定位栅极切口1340、1342及源极/漏极设计可影响装置设计，藉此影响用于形成电路1300的finFET的阈值电压。栅极切口1340、1342的定位可影响漏电流，其进而可影响装置的阈值电压。在一些具体实施例中，可施作上述对WFM层及/或光晕特征的调整，以使不同栅极-源极-漏极设计之诸装置之间达到所欲的阈值电压范围。
因此，为了补偿因栅极通道长度不同所致的阈值电压变化，可使栅极切口位置的位置所造成的变化带来具有不同栅极通道长度或不同栅极-源极-漏极设计的finFET装置的阈值电压。
现请参阅图14，根据本文中的具体实施例，所示为用于对具有不同栅极信道长度的诸装置调整阈值电压的程序的流程图。本文中所述的程序可在设计时间期间及/或处理阶段期间进行。
可判定finFET装置的装置类型，亦即P型装置或N型装置(于1410)。再者，可判定装置的阈值电压，亦即PLVT、PRVT、PSLVT、NLVT、NRVT、NSLVT(于1420)。再者，可判定用于形成标准胞元及/或集成电路的装置的栅极信道长度(于1430)。再者，可判定对应于各种栅极信道长度的阈值电压(于1440)。
不同阈值电压一经判定，便可判定阈值电压控制程序(于1450)。此程序可包括判定阈值电压值的范围，该范围内应含有具不同栅极信道阈值的装置的阈值电压。再者，此程序亦可包括识别要对特定装置采取的特定程序动作。举例而言，可选择具有更大栅极信道的特定装置，用于修改WFM厚度、WFM材料及/或光晕层的存在性。这些技巧其中的一或多者可用于使各个装置的VT位准具有不同栅极与源极/漏极设计，该等设计是在可接受、预定的范围内。
阈值电压调整参数一经判定，便可进行特定设计及/或程序调整。可进行WFM厚度的调整(于1460)，可进行WFM材料的调整(例如：材料类型、极性等)(于1462)，及/或可进行光晕层程序的调整(于1464)。基于这些调整，对包含具不同栅极信道长度的装置的集成电路进行处理(于1470)。按照这种方式，形成包含具不同栅极信道长度的装置的集成电路，使得该等装置呈现预定可接受范围内的阈值电压。
现请参阅图15，根据本文中的具体实施例，所绘示的是用于制作包含集成电路的半导体装置封装的系统的特写图，该集成电路形成有不同栅极通道长度的多个装置，使得该等装置呈现预定可接受范围内的阈值电压。图15的系统1500可包含半导体装置处理系统1510及设计单元1540。半导体装置处理系统1510可基于设计单元1540所提供的一或多个设计来制造集成电路装置。
半导体装置处理系统1510可包含各种处理站，例如：蚀刻程序站、光微影程序站、CMP程序站等。通过处理系统1510所进行的程序步骤其中一或多者可通过处理控制器1520来控制。处理控制器1520可以是包含一或多种软件产品的工作站计算机、桌面计算机、膝上型计算机、平板计算机或任何其它类型的运算装置，该软件产品能够控制程序、接收程序回馈、接收测试结果数据、进行学习周期调整、进行程序调整等。
半导体装置处理系统1510可在诸如硅晶圆的介质上生产集成电路。更特别的是，半导体装置处理系统1510生成具有finFET装置的集成电路，该等finFET装置包含具有信道空洞的鳍片，该等空洞填充有氧化物，并且是按照如上所述的用以降低或实质防止氧化的方式所进行。
装置处理系统1510可基于由集成电路设计单元1540所提供的电路设计来生产集成电路。处理系统1510可在诸如输送器系统的输送机构1550上提供已处理集成电路/装置1515。在一些具体实施例中，此输送器系统可以是能够输送半导体晶圆的尖端无尘室输送系统。在一项具体实施例中，半导体装置处理系统1510可包含多个处理步骤，用以提供WFM厚度、WFM材料、光晕层与栅极切口位置等的调整，如以上所述。
在一些具体实施例中，标示「1515」的组件可代表个别晶圆，而在其它具体实施例中，组件1515可代表半导体群组，例如：一「批」半导体晶圆。集成电路或装置1515可以是晶体管、电容器、电阻器、记忆胞、处理器及/或类似者。
系统1500的集成电路设计单元1540能够提供可通过半导体处理系统1510来制造的电路设计。集成电路设计单元1540可有能力判定要置放在装置封装中的装置(例如：处理器、内存装置等)的数目。集成电路设计单元1540亦可判定鳍片的高度、鳍片通道的尺寸等。这些尺寸可基于与驱动电流/效能度量、装置尺寸、阈值电压等有关的数据。基于该等装置的此类细节，集成电路设计单元1540可判定要制造的finFET的规格。基于这些规格，集成电路设计单元1540可提供用于制造本文中所述半导体装置封装的数据。此规格可包括处理半导体晶圆，使得可调整WFM厚度、WFM材料及/或光晕层以提供预定可接受范围内的阈值电压值。
系统1500可有能力进行涉及各种技术的各种产品的分析及制造。举例而言，系统1500可设计与产生数据以供制造CMOS技术、Flash技术、BiCMOS技术、功率装置、内存装置(例如，DRAM装置)、NAND内存装置及/或各种其它半导体技术的装置。
以上所揭示的特殊具体实施例仅属描述性，正如本发明可用所属领域的技术人员所明显知道的不同但均等方式予以修改并且实践而具有本文的指导效益。举例而言，以上所提出的程序步骤可按照不同顺序来进行。再者，除了如权利要求书中所述除外，未意图限制于本文所示构造或设计的细节。因此，证实可改变或修改以上揭示的特定具体实施例，而且所有此类变例全都视为在本发明的范畴及精神内。因此，本文寻求的保护是如权利要求书中所提。

Claims (10)

1.一种方法，包含：
判定第一晶体管栅极的第一阈值电压，该第一晶体管栅极包含具有第一长度的第一栅极通道；
判定第二晶体管栅极的第二栅极通道的第二长度；
基于该第二长度判定该第二栅极的程序调整，用于提供该第二晶体管栅极的第二阈值电压，其中，该第二阈值电压是在该第一阈值电压的预定范围内，其中，判定该程序调整包含判定该第一晶体管栅极的第一功函数金属(WFM)层的厚度及判定该第二晶体管栅极的第二WFM层的厚度，其中，回应于判定该第一阈值电压为PFET低电压阈值(PLVT)、PFET规则电压阈值(PRVT)、PFET超低电压阈值(PSLVT)、NFET低电压阈值(NLVT)、NFET规则电压阈值(NRVT)或NFET超低电压阈值(NSLVT)其中至少一者，该第二WFM层比该第一WFM层的该厚度更厚；以及
提供与程序调整有关的数据至处理控制器，用于进行该程序调整。
2.如权利要求1所述的方法，其特征为，判定该第一阈值电压包含判定该第一晶体管栅极是否为下列其中一者：PFET低电压阈值(PLVT)、PFET规则电压阈值(PRVT)、PFET超低电压阈值(PSLVT)、NFET低电压阈值(NLVT)、NFET规则电压阈值(NRVT)或NFET超低电压阈值(NSLVT)。
3.如权利要求2所述的方法，其特征为：
该PLVT与该NLVT为约0.20伏特的绝对值；
该PRVT与该NRVT为约0.25伏特的绝对值；以及
该PSLVT与该NSLVT为约0.15伏特的绝对值。
4.如权利要求1所述的方法，其特征为，该第一晶体管栅极的第一WFM呈第二WFM的相反极性。
5.如权利要求1所述的方法，其特征为，判定该程序调整包含判定用于该第一WFM层的第一材料及用于该第二WFM层的第二材料。
6.如权利要求1所述的方法，其特征为，判定该程序调整包含调整对应于该第二晶体管栅极的源极与漏极区所相邻的光晕层，其中，调整该光晕层包含提供更薄的光晕层或消除该光晕层。
7.如权利要求1所述的方法，其特征为，判定第二功函数金属层的厚度判定该第二WFM层要在约40A至50A的范围内。
8.一种系统，包含：
用以制造包含至少一个鳍式场效晶体管(finFET)的半导体装置的半导体装置处理系统；以及
有效耦接至该半导体装置处理系统的处理控制器，该处理控制器经组配以控制该半导体装置处理系统的运作；
其中，该半导体装置处理系统经调适以：
判定第一晶体管栅极的第一阈值电压，该第一晶体管栅极包含具有第一长度的第一栅极通道；
判定第二晶体管栅极的第二栅极通道的第二长度；
基于该第二长度判定该第二栅极的程序调整，用于提供该第二晶体管栅极的第二阈值电压，其中，该第二阈值电压是在该第一阈值电压的预定范围内，其中，判定该第一晶体管栅极的第一功函数金属(WFM)层的厚度及判定该第二晶体管栅极的第二WFM层的厚度，其中，回应于判定该第一阈值电压为PFET低电压阈值(PLVT)、PFET规则电压阈值(PRVT)、PFET超低电压阈值(PSLVT)、NFET低电压阈值(NLVT)、NFET规则电压阈值(NRVT)或NFET超低电压阈值(NSLVT)其中至少一者，该第二WFM层比该第一WFM层的该厚度更厚；以及
提供与程序调整有关的数据至该处理控制器，用于进行该程序调整。
9.如权利要求8所述的系统，进一步包含经组配用以产生第一设计的设计单元，该第一设计包含用于程序掩膜的界定、用于形成该第一晶体管栅极与该第二晶体管栅极的界定，其中，出自该设计单元的数据是由该处理控制器用于控制该半导体装置处理系统的运作。
10.如权利要求8所述的系统，其特征为，该半导体装置处理系统经进一步调适以：
调整对应于该第二晶体管栅极的源极与漏极区所相邻的光晕层，其中，调整该光晕层包含提供更薄的光晕层或消除该光晕层；以及
判定第一栅极-源极-漏极设计的第三阈值电压及第二栅极-漏极-源极设计的第四阈值电压，并且判定该第二栅极-漏极-源极设计的WFM层的厚度，用于造成该第四阈值电压处在该第三阈值电压的预定范围内。
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