TW201903931A - 在ｆｉｎｆｅｔ裝置中用於閾值電壓控制之方法、設備及系統 - Google Patents

在ｆｉｎｆｅｔ裝置中用於閾值電壓控制之方法、設備及系統 Download PDF

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TW201903931A
TW201903931A TW106124112A TW106124112A TW201903931A TW 201903931 A TW201903931 A TW 201903931A TW 106124112 A TW106124112 A TW 106124112A TW 106124112 A TW106124112 A TW 106124112A TW 201903931 A TW201903931 A TW 201903931A
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threshold voltage
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TWI675425B (zh
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東郷光洋
藍 阿斯拉
興 張
帕拉尼爾 巴拉斯拉瑪尼安
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美商格羅方德半導體公司
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Abstract

所揭示的是就複數個電晶體裝置用於控制閾值電壓值之至少一種方法、設備及系統。判定第一電晶體閘極之第一閾值電壓，該第一電晶體閘極包含具有第一長度之第一閘極通道。判定第二電晶體閘極之第二閘極通道之第二長度。基於該第二長度判定該第二閘極之程序調整，用於提供該第二電晶體閘極之第二閾值電壓。該第二閾值電壓是在該第一閾值電壓之預定範圍內。提供與程序調整有關之資料至程序控制器，用於進行該程序調整。

Description

在FINFET裝置中用於閾值電壓控制之方法、設備及系統
本揭露大體上是關於尖端半導體裝置之製造，並且更具體地說，是關於就FinFET裝置用於提供閾值電壓控制之各種方法。
諸如CPU、儲存裝置、ASIC(特定應用積體電路)及諸如此類的先進積體電路在製作時，需要根據指定之電路布局，在給定的晶片面積中，形成大量電路元件，其中所謂的金屬氧化物場效電晶體(MOSFET或FET)代表一種重要的電路元件類型，其實質決定積體電路的效能。FET是一種裝置，其典型包括源極區、汲極區、置於該源極區與該汲極區之間的通道區，以及置於該通道區上面之閘極電極。通過FET之電流流動是藉由控制施加至閘極電極之電壓來控制。若對閘極電極施加比裝置之閾值電壓更小之電壓，則沒有通過該裝置的電流流動(略去非所欲的漏電流，其相對較小)。然而，對閘極電極施加與裝置之閾值電壓相等或比其更大之電壓時，通道區變為具有導電性， 並且允許電流穿過導電通道區在源極區與汲極區之間流動。
為了提升場效電晶體的運作速度，並且增加積體電路裝置上場效電晶體的密度，裝置設計人員多年來已大幅縮減場效電晶體的實體尺寸。更具體地說，FET的通道長度已顯著縮減，已使FET的切換速度獲得提升。然而，縮減FET的通道長度亦縮減源極區與汲極區之間的距離。在一些情況下，縮減源極與汲極之間的間隔會造成難以有效率地使通道的電位免於因汲極的電位而受到負面影響。這有時稱為所謂的短通道效應，其中FET作為主動開關的特性會降低。
與具有平面結構之平面型FET相比，有所謂的3D裝置，諸如說明性FinFET裝置，其是一種3維結構。更具體地說，在FinFET中，形成大體上垂直而置的鰭形主動區，而且閘極電極將鰭形主動區的側邊及上表面兩者都包圍，用以形成三閘結構，為的是要使用具有3維結構而非平面結構之通道。在一些情況下，絕緣覆蓋層(例如：氮化矽)是置於鰭片的頂端，並且FinFET裝置僅具有雙閘結構。
FinFET設計使用可使用選擇性蝕刻程序在半導體晶圓之表面上形成之「鰭片」。鰭片可用於在電晶體之閘極與源極與汲極之間形成隆起通道。接著沉積閘極，使得其環繞鰭片以形成三閘結構。由於通道極薄，閘極對裡面的載子一般會具有更大的控制。然而，當電晶體切換 為接通時，通道之形狀可限制電流之流動。因此，可平行使用多個鰭片以提供更大的電流流動使驅動強度提升。
第1圖繪示目前FinFET裝置的特寫截面圖。第1圖所示的FinFET裝置100包含複數個「鰭片」110。該半導體裝置可朝垂直取向安置，建立一或多個鰭片110。該FinFET之源極與汲極是沿著鰭片水平置放。高k金屬閘極120環繞於鰭片上方，將其三個側邊包覆。閘極120界定FinFET裝置之長度。順著與半導體晶圓之平面平行之方向沿著正交晶面出現電流流動。鰭片之電氣有效高度(標示為H)典型為藉由鰭片顯露步驟中之氧化物凹陷量來測定，因此，所有鰭片110都固定。
鰭片之厚度(標示為Tfi)判定電晶體裝置之短通道行為，並且通常比鰭片110之高度H還小。鰭片之間距(標示為P)是藉由微影限制條件來測定，並且指定要實施所欲裝置寬度之晶圓區。若間距P值小且高度H值大，則能實現每平方面積之較佳裝置堆積，導致設計更稠密，或矽晶圓區使用更有效率。
積體電路有比例縮小的趨勢，以利支援不斷縮減的電子裝置。這已促使設計人員縮減finFET裝置的尺寸。如此，finFET裝置中鰭片的間距得以縮減，使finFET裝置的密度增加。如此，在許多情況下，以緊密靠近的方式形成包含多個finFET電晶體之裝置，這些電晶體有不同的閘極長度或通道長度。在許多裝置中，源極與汲極之間的通道寬度縮減，可能出現所謂的短通道效應。這可能造 成裝置彼此間閾值電壓(VT)出現變異。
隨著閘極通道的長度縮減，VT也可能改變。因此，含有具不同閘極通道長度、不同閾值電壓之電晶體的裝置可適用於不同電晶體。亦即，相較於更短通道裝置之閾值電壓，長通道裝置彼此間可有明顯的閾值電壓差異。這可能例如對於給定電壓造成效能問題，有一些電晶體可變為啟動，而其它則停住，需要在功率消耗與空間消耗方面代價高昂的補償電路。
本揭露可因應及/或至少減少以上指認之其中一或多個問題。
以下介紹本發明之簡化概要，以便對本發明之一些態樣有基本的了解。本概要並非本發明之詳盡概述。用意不在於指認本發明之重要或關鍵要素，或敍述本發明之範疇。目的僅在於以簡化形式介紹一些概念，作為下文更詳細說明的引言。
大體上，本揭露是針對就複數個電晶體裝置用於控制閾值電壓值之各種方法、設備及系統。判定第一電晶體閘極之第一閾值電壓，該第一電晶體閘極包含具有第一長度之第一閘極通道。判定第二電晶體閘極之第二閘極通道之第二長度。基於該第二長度判定該第二閘極之程序調整，用於提供該第二電晶體閘極之第二閾值電壓。該第二閾值電壓是在該第一閾值電壓之預定範圍內。提供與程序調整有關之資料至程序控制器，用於進行該程序調 整。
100‧‧‧FinFET裝置
110、510‧‧‧鰭片
120‧‧‧高k金屬閘極、閘極
500‧‧‧半導體裝置、裝置、電晶體
501、605、605a、605b、705a、705b、805a、805b、905a、 905b、1105a、1105b‧‧‧基材
502‧‧‧基礎層、層
510C‧‧‧中央部分
510E‧‧‧末端部分
511‧‧‧汲極與源極區
512‧‧‧覆蓋層
520‧‧‧閘極電極結構
521‧‧‧側壁間隔物結構、結構
522‧‧‧閘極電極材料、電極材料
600、700、800、900、1100‧‧‧裝置、第一裝置
601、701、801、901、1101‧‧‧裝置、第二裝置
603‧‧‧源極/汲極鰭片、鰭片
622a、622b、722a、722b、822a、822b、922a、922b、1122a、1122b‧‧‧源極區
624a、624b、724a、724b、824a、824b、924a、924b、1124a、1124b‧‧‧汲極區
630a、630b、640、645、730a、730b、830a、830b、930a、930b、1130a、1130b‧‧‧閘極
645a、645b、745a、745b、845a、845b、945b、1145b‧‧‧高k襯墊
650、650a、650b‧‧‧功函數材料、WFM特徵
660‧‧‧切割線路
660a、660b、760a、760b、860a、860b、960a、960b、1160a、1160b‧‧‧閘極填充區
670、770、870、970、1270‧‧‧光暈層
750a、750b、850a、850b、950a、950b、1150a、1150b‧‧‧WFM特徵、WFM
855a、855b、955a、955b‧‧‧襯墊層、內層、層
1300‧‧‧積體電路
1310‧‧‧閘極形成體、閘極
1320‧‧‧源極/汲極(S/D)形成體
1330‧‧‧基材層
1340、1342‧‧‧閘極切口區
1410至1470‧‧‧步驟
1500‧‧‧系統
1510‧‧‧半導體裝置處理系統、處理系統
1515‧‧‧積體電路或裝置
1520‧‧‧處理控制器
1540‧‧‧設計單元
1550‧‧‧輸送機構
H‧‧‧高度
Tfi‧‧‧厚度
P‧‧‧間距
本揭露可搭配所附圖式參照以下說明來了解，其中相似的元件符號表示相似的元件，並且其中：第1圖繪示目前FinFET裝置的特寫圖；第2圖根據本文中之具體實施例，繪示半導體裝置之透視圖的特寫圖；第3圖根據本文中之具體實施例，繪示沿著第2圖之裝置之第一區段取看之截面圖的特寫圖；第4圖根據本文中之具體實施例，繪示第2圖之裝置進一步順著程序之截面圖的特寫圖；第5圖根據本文中之具體實施例，繪示finFET裝置的特寫、簡化俯視圖；第6圖繪示具有PRVT特性及習知功函數金屬層之兩個finFET的特寫截面圖；第7圖根據本文中之一具體實施例，繪示具有PRVT特性及功函數金屬層之兩個finFET的特寫截面圖；第8圖繪示具有NRVT特性及習知功函數金屬層之兩個finFET的特寫截面圖；第9圖根據一項具體實施例，繪示具有NRVT特性及功函數金屬層之finFET的特寫截面圖；第10圖根據另一具體實施例，繪示具有NRVT特性及功函數金屬層之finFET的特寫截面圖； 第11圖根據一項具體實施例，繪示具有PRVT特性及相反極性功函數金屬層之finFET的特寫截面圖；第12圖根據另一具體實施例，繪示具有PRVT特性及相反極性功函數金屬層之finFET的特寫截面圖；第13圖根據本文中之具體實施例，繪示半導體裝置上閘極切口區之俯視圖的特寫圖；第14圖根據本文中之具體實施例，繪示用於對具有不同閘極通道長度之諸裝置調整閾值電壓之程序的流程圖；以及第15圖根據本文中之具體實施例，繪示用於製作半導體裝置之系統的特寫圖，該半導體裝置具有不同閘極通道長度finFET裝置及預定範圍內之閾值電壓。
儘管本文所揭示的申請標的易受各種修改和替代形式所影響，其特定具體實施例已藉由圖式中的實施例予以表示並且在本文中予以詳述。然而，應了解的是，本文中特定具體實施例之說明用意不在於將本發明限制於所揭示之特定形式，相反地，如隨附申請專利範圍所界定，用意在於涵蓋落於本發明之精神及範疇內的所有修改、均等例及替代方案。再者，所提供的圖式未依照比例繪製。
下面說明本發明之各項說明性具體實施例。為了澄清，本說明書中並未說明實際實作態樣的所有 特徵。當然，將會領會的是，在開發任何此實際具體實施例時，必須作出許多實作態樣特定決策才能達到開發者的特定目的，例如符合系統有關及業務有關的限制條件，這些限制條件會隨實作態樣不同而變。此外，將會領會的是，此一開發努力可能複雜且耗時，雖然如此，仍會是受益於本揭露之所屬技術領域中具有通常知識者的例行工作。
本申請標的現將參照附圖來說明。各種結構、系統及裝置在圖式中只是為了闡釋而繪示，為的是不要因所屬技術領域中具有通常知識者眾所周知的細節而混淆本揭露。雖然如此，仍將附圖包括進來以說明並闡釋本揭露之說明性實施例。本文中使用的字組及詞組應了解並詮釋為與所屬技術領域中具有通常知識者了解的字組及詞組具有一致的意義。與所屬技術領域中具有通常知識者了解的通常及慣用意義不同的詞彙或詞組(即定義)之特殊定義，用意不在於藉由本文詞彙或詞組的一致性用法提供暗示。就一詞彙或詞組用意在於具有特殊意義的方面來說，即有別於所屬技術領域中具有通常知識者了解的意義，此一特殊定義將會按照為此詞彙或詞組直接且不含糊地提供此特殊定義的定義方式，在本說明書中明確提出。
本文中的具體實施例是用來形成包含具不同閘極通道長度之finFET的裝置，以及提供預定變異內之各別閾值電壓。舉例而言，本文中之具體實施例是用來形成包含具有不同閘極通道之複數個finFET裝置的裝置，其中該等finFET裝置包含不同對應的功函數特性。各種功函 數特性可補償不同閘極通道長度，使得各個finFET裝置之閾值電壓處在預定範圍內。因此，本文中之具體實施例提供具有類似閾值電壓之不同閘極通道長度之finFET裝置。
在一些具體實施例中，為了提供實質均勻的閾值電壓，在裝置之閘極部分之形成期間，功函數特性經調制為功函數材料之厚度。在其他具體實施例中，為了提供實質均勻的閾值電壓，功函數特性經調制為當作功函數層使用之材料之類型。在又其它具體實施例中，為了提供實質均勻的閾值電壓，可調制或消除相鄰源極與汲極區所形成之光暈層。「實質均勻的閾值電壓」一詞可指稱為處在電壓值預定範圍內之閾值電壓。本文中所述之具體實施例可因應具有不同閘極長度之裝置中與閾值電壓差異相關聯的問題。再者，諸如閘極線與空間間距之閘極設計差異等可造成閾值電壓差異之其它因素亦可使用本文中提供之具體實施例，藉由調整閾值電壓來因應。
第2至4圖根據本文中之具體實施例，繪示與進行形成finFET裝置之初始程序有關的各種特寫圖。第2圖示意性繪示半導體裝置500的透視圖，其可以是包含複數個鰭片之finFET裝置。在所示製造階段中，裝置500可包含基材501，諸如矽基材或任何其它適當的載體材料，其上可形成適當的基礎層502，其在一些說明性具體實施例中可代表絕緣層，諸如二氧化矽層、氮化矽層、氮氧化矽層及類似者。舉例而言，若基材501可由實質結晶半導體材料所構成，基礎層502(若以絕緣材料的形式提供) 及基材501可界定絕緣體上矽(SOI)組態。
此外，複數個鰭片510是在層502上形成，並且包含各別末端部分510E及中央部分510C，其是藉由閘極電極結構520所包覆。再者，至少可在鰭片510之側壁上形成閘極絕緣材料(第2圖未示)，而若考量三閘電晶體架構，可在鰭片510之頂端表面上形成對應閘極絕緣層。在其它例子中，鰭片510可藉由覆蓋層(圖未示)所包覆，其可導致連至鰭片510之電容性耦合不足，以致其頂端表面可能無法有效充當通道區。關於鰭片510之任何材料組成，要領會的是，可使用任何適當的材料，諸如矽、矽/鍺、鍺或任何其它適當的半導體化合物，端視總體裝置要求而定。類似的是，鰭片510之對應尺寸可根據所考量對應技術節點之設計規則來選擇。
第3圖繪示沿著第2圖之區段IIb取看之截面圖的特寫圖。如圖所示，可在鰭片510及閘極電極結構520上形成覆蓋層512，諸如氧化矽層或高K HFO2層及/或類似者。閘極電極結構520可由諸如多晶矽、含金屬材料及類似者等適當的材料所構成，可在覆蓋層512上形成，並且亦可沿著鰭片510之對應側壁(第3圖之區段中未示)向下延展至層502。如第2及3圖所示之半導體裝置500可基於建置良好的程序技巧來形成，舉例來說，亦如以上參照裝置500所闡釋。
第4圖繪示電晶體500在更晚期製造階段時之透視圖的特寫圖。如圖所示，閘極電極結構520可包含 側壁間隔物結構521，其可由諸如氮化矽、二氧化矽及類似者等任何適當的材料所構成。該間隔物結構可基於建置良好的沉積與蝕刻技巧來形成，其中間隔物結構520之寬度可根據鰭片510之各末端部分510E中之所欲摻質分布來選擇。亦即，相鄰於閘極電極結構520之末端部分510E中可建立適度高摻質濃度，有可能使用偏移間隔物元件(圖未示)來建立，之後，可提供結構521之一或多個間隔物元件，並且可在一或多個後續佈植步驟期間將其當作佈植遮罩使用，以在對閘極電極結構520之閘極電極材料522具有側向距離之末端部分510E中提供所欲高摻質濃度。應領會的是，藉由在結構521中適當地形成對應數目之間隔物元件，可建立延展自電極材料522之任何適當的濃度分布。應進一步領會的是，可進行任何其它佈植程序，舉例來說，關於在中央部分510C附近界定反摻雜區，該反摻雜區代表實際通道區。可在相反安置的末端部分510E處形成汲極與源極區511，該等末端部分相對中央部分510C具有所欲摻質濃度與濃度梯度。基於就第2至4圖所示的概念，可形成具有各種閘極通道長度之各個finFET裝置。運用本文中提供之具體實施例所例示的一或多種概念，具有各種閘極通道長度之各個finFET裝置可顯示實質類似的閾值電壓值。
現請參閱第5圖，根據本文中之具體實施例，所繪示的是finFET裝置之特寫、簡化俯視圖。第5圖繪示裝置600，其包含形成於基材605上之複數個源極/汲 極鰭片603，與第4圖所示之實施例類似。再者，第5圖繪示複數個閘極，例如：閘極640及閘極645。閘極640、645可由功函數材料層650所圍繞。第5圖展示切割線路660，其中第6至12圖就切割線路660表示finFET裝置之特寫截面圖。
在一些具體實施例中，可將電晶體裝置之閾值電壓區分成六類：PFET規則電壓閾值(PRVT)；PFET低電壓閾值(PLVT)；PFET超低電壓閾值(PSLVT)；NFET規則電壓閾值(NRVT)；NFET低電壓閾值(NLVT)；NFET超低電壓閾值(NSLVT)。在一些具體實施例中，PRVT與NRVT之絕對值可約為0.25伏特，PLVT與NLVT之絕對值可約為0.20伏特，以及PSLVT與NSLVT之絕對值可約為0.15伏特，其中可施加其它電壓位準，但仍在本揭露之精神內。所屬技術領域中具有通常知識者將輕易理解的是，上列電壓閾值是以絕對值的方式來提供，以及PFET裝置大體上將具有負VT值，而NFET裝置大體上將具有正VT值。本文中之具體實施例是用來提供就複數種閘極通道寬度間之不同閾值電壓類別維持實質一致的閾值電壓。
現請參閱第6圖，所示為具有PRVT特性及習知功函數金屬層之兩個finFET的特寫截面圖。第6圖包含第6圖(a)部分所示之第一裝置600及第6圖(b)部分所示之第二裝置601。裝置600包含基材605a、閘極630a、源極區622a以及汲極區624a。大體上，源極/汲極區622a、622b、624a、624b是由所謂的光暈層670所圍繞，如第6 圖所示。
裝置601包含基材605b、閘極630b、源極區622b以及汲極區624b。各裝置600、601包含位在閘極電極內之金屬，大體上稱為功函數金屬(work-function metal；WFM)。閘極630a包含高k襯墊645a、WFM特徵650a及閘極填充區660a，其可填充有鎢。類似的是，閘極630b包含高k襯墊645b、WFM特徵650b及閘極填充區660b。
如第6圖所示，閘極630a之通道長度比閘極630b之通道長度相對更小。如此，閘極填充區660b比閘極填充區660a更寬。在諸如第6圖所示之裝置600、601等習知裝置中，WMF特徵650a、650b有類似的厚度及材料類型。此習知組態可造成裝置600之閾值電壓與裝置601之閾值電壓明顯不同。
現請參閱第7圖，根據本文中之具體實施例，所示為具有PRVT特性及功函數金屬層之兩個finFET的特寫截面圖。第7圖包含第7圖(a)部分所示之第一裝置700及第7圖(b)部分所示之第二裝置701。裝置700包含基材705a、閘極730a、源極區722a以及汲極區724a。類似的是，裝置701包含基材705b、閘極730b、源極區722b以及汲極區724b。在一些具體實施例中，第6至12圖所示之源極與汲極區可對應於第5圖之鰭片603。
在一項具體實施例中，源極/汲極區722a、722b、724a、724b可由所謂的光暈層770所圍繞，類似於 第6圖之光暈層670。在其他具體實施例中，可省略光暈層770之沉積，其中源極/汲極區722a、722b、724a、724b將不由光暈層所圍繞。
閘極730a包含高k襯墊745a、功函數金屬(WFM)特徵750a及閘極填充區760a，其在一項具體實施例中，可填充有鎢。類似的是，閘極730b包含高k襯墊745b、WFM特徵750b及閘極填充區760b。
如第7圖所示，閘極730a之通道長度比閘極730b之通道長度相對更小。如此，閘極填充區760b比閘極填充區760a更寬。在一項具體實施例中，相較於WFM 750b，WFM 750a具有不同厚度。舉例而言，WFM 750b之厚度可比WFM 750a之厚度大一預定量，以顧及裝置701之閘極通道增加。在一項具體實施例中，相對裝置700之閘極通道長度，WFM 750b之厚度增加(從WFM 750a之基線厚度起增加)可與裝置701之閘極通道長度增加成比例。在一些具體實施例中，可增加WFM 750b之厚度，使得閘極填充區760b與閘極填充區760a實質相同。按照這種方式，裝置701因其閘極通道尺寸增加所致的閾值電壓變化可減少或實質降到最小，以使短通道裝置700與長通道裝置701有實質類似的閾值電壓。
現請參閱第8圖，所示為具有NRVT特性及習知功函數金屬層之兩個finFET的特寫截面圖。第8圖包含第8圖(a)部分所示之第一裝置800及第8圖(b)部分所示之第二裝置801。裝置800包含基材805a、閘極830a、源 極區822a以及汲極區824a。裝置801包含基材805b、閘極830b、源極區822b以及汲極區824b。大體上，源極/汲極區822a、822b、824a、824b是由光暈層870所圍繞，如第8圖所示。
裝置801包含閘極830b、源極區822b以及汲極區824b。各裝置800、801包含位在閘極電極內之金屬，俗稱功函數金屬(WFM)。裝置800之閘極830a包含高k襯墊845a、WFM特徵650a、襯墊層855a(諸如鈦組合層，例如：TiAl或TiAlC)以及閘極填充區860a，其可填充有鎢。類似的是，裝置801之閘極830b包含高k襯墊845b、內層855b、WFM特徵850b以及閘極填充區860b。
如第8圖所示，閘極830a之通道長度比閘極830b之通道長度相對更小。如此，閘極填充區860a比閘極填充區860b更寬。在諸如第8圖所示之裝置800、801等習知裝置中，WMF特徵850a、850b有類似的厚度及材料類型。此習知組態可造成裝置800之閾值電壓與裝置801之閾值電壓明顯不同。
現請參閱第9及10圖，根據本文中之具體實施例，所示為具有NRVT特性及功函數金屬層之finFET的特寫截面圖。第9及10圖各包含第9圖(a)部分所示之第一裝置900及第10圖(b)部分所示之第二裝置901。裝置900包含基材905a、閘極930a、源極區922a以及汲極區924a。裝置901包含基材905b、閘極930b、源極區922b以及汲極區924b。在一項具體實施例中，第9圖之源極/ 汲極區922a、922b、924a、924b可由光暈層970所圍繞，類似於第6圖之光暈層670。在其他具體實施例中，如第10圖所例示，可省略光暈層970之沉積，其中第10圖中源極/汲極區922a、922b、924a、924b將不由光暈層所圍繞。在一些具體實施例中，第9圖之光暈層可僅在一個裝置900或另一裝置901上形成，用於達到預定範圍內之閾值電壓位準。
閘極930b包含高k襯墊945b、功函數金屬(WFM)特徵950b以及內層955b，諸如鈦組合層，例如：TiAl或TiAlC。再者，WFM 950a(請參閱(a)部分)及層955a內形成閘極填充區960a，其在一項具體實施例中，可填充有鎢。類似的是，閘極930b包含高k襯墊945b、WFM特徵950b、鈦組合層955b及閘極填充區960b。
如第9圖所示，閘極930a之通道長度比閘極930b之通道長度相對更小。如此，閘極填充區960b比閘極填充區960a更寬。在一項具體實施例中，相較於WFM 950b，WFM 950a具有不同厚度。舉例而言，WFM 950b之厚度可增加一預定量，以顧及裝置901之閘極通道增加。在一項具體實施例中，相對裝置900、901之閘極通道長度，WFM 950b之厚度增加(從WFM 950a之基線厚度起增加)可與裝置901之閘極通道長度增加成比例。
在一些具體實施例中，可增加WFM 950b之厚度，使得WFM 950b對閘極填充區960b之比例有別於WFM 950b對閘極填充區960b之比例。因此，在一項具體 實施例中，對於NRVT裝置中之小閘極通道長度，可使用較薄的WFM，其中可將更厚的WFM用於更大的閘極通道長度，以使介於那兩個裝置之間的VT保持類似。
按照這種方式，可對閘極通道長度之變化進行補償，使得裝置901之閾值電壓相較於裝置900之VT因其閘極通道尺寸增大所致的變化可以降低或實質降到最小。再者，在一些具體實施例中，對於NSLVT裝置，可調整第9及10圖之類似WFM厚度以提供實質類似的VT值。
現請參閱第11及12圖，根據本文中之具體實施例，所示為具有PRVT特性及相反極性功函數金屬層之finFET的特寫截面圖。大體上，處理finFET裝置時可使用兩種類型之工作力金屬(work force metal；WFM)：用於p通道裝置之第一WFM及用於n通道裝置之第二WFM。大體上，關於影響電壓閾值，對PFET裝置施加大有效功函數(即第一WFM)，其可對NFET裝置指出大阻障高度。相比之下，大體上，關於影響電壓閾值，對NFET裝置施加小有效功函數(即第二WFM)，其可對PFET裝置指出大阻障高度。關於WFM的「極性」一詞大體上是指用於PFET裝置之有效WFM類型與用於NFET裝置之有效WFM類型的相對關係，因為PFET與NFET大體上視為相反極性。因此，在一些具體實施例中，「相反極性之WFM」一詞可指稱為使用位在PFET裝置上之第二WFM以及位在NFET裝置上之第一WFM。諸如摻雜程序、合金化程序、退火程序、離子佈植程序等一或多個程序可影響有效WFM，並從而影 響WFM極性。
第11及12圖各包含第11與12圖(a)部分所示之第一裝置1100及第11與12圖(b)部分所示之第二裝置1101。裝置1100包含基材1105a、閘極1130a、源極區1122a以及汲極區1124a。類似的是，裝置1101包含基材1105b、閘極1130b、源極區1122b以及汲極區1124b。在一項具體實施例中，第12圖之源極/汲極區1122a、1122b、1124a、1124b可由光暈層1270所圍繞，類似於第6圖之光暈層670。在其他具體實施例中，如第11圖所例示，可省略光暈層1270之沉積，其中源極/汲極區1122a、1122b、1124a、1124b將不由光暈層所圍繞。
閘極1130b包含高k襯墊1145b、功函數金屬(WFM)特徵1250b。再者，WFM 1150a(請參閱(a)部分)及層1155a內形成閘極填充區1160a，其在一項具體實施例中，可填充有鎢。類似的是，閘極1130b包含高k襯墊1145b、WFM特徵1150b、鈦組合層1155b及閘極填充區1160b。
如第11圖所示，閘極1130a之通道長度比閘極1130b之通道長度相對更小。如此，閘極填充區1160b比閘極填充區1160a更寬。在一項具體實施例中，相較於WFM 1150b，WFM 1150a具有不同厚度。舉例而言，WFM 1150b之厚度可增加一預定量，以顧及裝置1101之閘極通道差異。在一項具體實施例中，相對裝置1100、1101之閘極通道長度，WFM 1150b之厚度增加(從WFM 1150a之基 線厚度起增加)可與裝置1101之閘極通道長度增加成比例。因此，相對於薄WFM層1150b，裝置1100之WFM 1150a可以是更薄之層。再者，相較於WFM 1150b，WFM 1150a可具有不同極性。在一項具體實施例中，裝置1100、1101其中一者之極性差異結合WFM層1150a、1150b之厚度變化可修改VT，使得裝置1100、1101之閾值電壓可在預定變異範圍內。
在一些具體實施例中，VT之預定變異可約為10%；因此，對於約0.250伏特之VT，預定可接受差異可約為0.025伏特。
在一些具體實施例中，可將WFM 1150b之厚度從「更薄」層級增加至「薄」層級，使得WFM 1150b對閘極填充區1160b之比例有別於WFM 1150b對閘極填充區1160b之比例。在一些具體實施例中，「薄」層級WFM可約為30-40A(例如：TiN)，「更薄」層級可低於30A，而「厚」層級可約為40-50A。因此，在一項具體實施例中，對於PRVT裝置中之小閘極通道長度，可使用較薄的WFM，其中可將薄WFM用於更大的閘極通道長度，以使介於那兩個裝置之間的VT保持類似。按照這種方式，可對閘極通道長度之變化進行補償，使得裝置1101之閾值電壓相較於裝置1100之VT因其閘極通道尺寸增大所致的變化可以降低或實質降到最小。
在一些具體實施例中，類似於藉由使用不同極性之WFM層來控制具有不同通道長度之PFET裝置之 閾值電壓，可藉由使用不同極性之WFM層，使具有不同通道長度之NFET的閾值電壓在預定容差等級內。
現請參閱第13圖，根據本文中之具體實施例，所示為半導體裝置上閘極切口區之俯視圖的特寫圖。形成積體電路1300，其中可在基材層(例如：非晶矽)1330上形成複數個閘極形成體1310。可在閘極形成體1310週圍形成閘極間隔物。再者，形成複數個源極/汲極(S/D)形成體1320。可在S/D鰭片320上形成磊晶(EPI)形成體325(N型及P型)。
第13圖亦展示兩個例示性閘極切口區1340、1342。在一些具體實施例中，閘極切口區1340、1342之定位可影響電路1300之裝置的閾值電壓。可在閘極切口1340、1342之位置處切割閘極1310。就影響待處理裝置之閾值電壓(例如：設計程序期間)而言，閘極切割之位置可在形成閘極前先判定。定位閘極切口1340、1342及源極/汲極設計可影響裝置設計，藉此影響用於形成電路1300之finFET之閾值電壓。閘極切口1340、1342之定位可影響漏電流，其進而可影響裝置之閾值電壓。在一些具體實施例中，可施作上述對WFM層及/或光暈特徵之調整，以使不同閘極-源極-汲極設計之諸裝置之間達到所欲的閾值電壓範圍。
因此，為了補償因閘極通道長度不同所致的閾值電壓變化，可使閘極切口位置之位置所造成之變化帶來具有不同閘極通道長度或不同閘極-源極-汲極設計之 finFET裝置之閾值電壓。
現請參閱第14圖，根據本文中之具體實施例，所示為用於對具有不同閘極通道長度之諸裝置調整閾值電壓之程序的流程圖。本文中所述之程序可在設計階段期間及/或處理階段期間進行。
可判定finFET裝置之裝置類型，亦即P型裝置或N型裝置(於1410)。再者，可判定裝置之閾值電壓，亦即PLVT、PRVT、PSLVT、NLVT、NRVT、NSLVT(於1420)。再者，可判定用於形成標準胞元及/或積體電路之裝置的閘極通道長度(於1430)。再者，可判定對應於各種閘極通道長度之閾值電壓(於1440)。
不同閾值電壓一經判定，便可判定閾值電壓控制程序(於1450)。此程序可包括判定閾值電壓值之範圍，該範圍內應含有具不同閘極通道閾值之裝置的閾值電壓。再者，此程序亦可包括識別要對特定裝置採取的特定程序動作。舉例而言，可選擇具有更大閘極通道之特定裝置，用於修改WFM厚度、WFM材料及/或光暈層之存在性。這些技巧其中之一或多者可用於使各個裝置之VT位準具有不同閘極與源極/汲極設計，該等設計是在可接受、預定的範圍內。
閾值電壓調整參數一經判定，便可進行特定設計及/或程序調整。可進行WFM厚度之調整(於1460)，可進行WFM材料之調整(例如：材料類型、極性等)(於1462)，及/或可進行光暈層程序之調整(於1464)。基於這些 調整，對包含具不同閘極通道長度之裝置的積體電路進行處理(於1470)。按照這種方式，形成包含具不同閘極通道長度之裝置的積體電路，使得該等裝置呈現預定可接受範圍內之閾值電壓。
現請參閱第15圖，根據本文中之具體實施例，所繪示的是用於製作包含積體電路之半導體裝置封裝之系統的特寫圖，該積體電路形成有不同閘極通道長度之複數個裝置，使得該等裝置呈現預定可接受範圍內之閾值電壓。第15圖的系統1500可包含半導體裝置處理系統1510及設計單元1540。半導體裝置處理系統1510可基於設計單元1540所提供之一或多個設計來製造積體電路裝置。
半導體裝置處理系統1510可包含各種處理站，例如：蝕刻程序站、光微影程序站、CMP程序站等。藉由處理系統1510所進行之程序步驟其中一或多者可藉由處理控制器1520來控制。處理控制器1520可以是包含一或多種軟體產品的工作站電腦、桌上型電腦、膝上型電腦、平板電腦或任何其它類型的運算裝置，該軟體產品能夠控制程序、接收程序回饋、接收測試結果資料、進行學習週期調整、進行程序調整等。
半導體裝置處理系統1510可在諸如矽晶圓之介質上生產積體電路。更特別的是，半導體裝置處理系統1510生成具有finFET裝置之積體電路，該等finFET裝置包含具有通道空洞之鰭片，該等空洞填充有氧化物，並且是按照如上所述的用以降低或實質防止氧化之方式所進 行。
裝置處理系統1510可基於由積體電路設計單元1540所提供的電路設計來生產積體電路。處理系統1510可在諸如輸送器系統之輸送機構1550上提供已處理積體電路/裝置1515。在一些具體實施例中，此輸送器系統可以是能夠輸送半導體晶圓的尖端無塵室輸送系統。在一項具體實施例中，半導體裝置處理系統1510可包含複數個處理步驟，用以提供WFM厚度、WFM材料、光暈層及閘極切口位置等的調整，如以上所述。
在一些具體實施例中，標示「1515」的元件可代表個別晶圓，而在其它具體實施例中，元件1515可代表半導體群組，例如：一「批」半導體晶圓。積體電路或裝置1515可以是電晶體、電容器、電阻器、記憶胞、處理器及/或類似者。
系統1500之積體電路設計單元1540能夠提供可藉由半導體處理系統1510來製造的電路設計。積體電路設計單元1540可有能力判定要置放在裝置封裝中之裝置(例如：處理器、記憶體裝置等)的數目。積體電路設計單元1540亦可判定鰭片之高度、鰭片通道之尺寸等。這些尺寸可基於與驅動電流/效能度量、裝置尺寸、閾值電壓等有關的資料。基於該等裝置之此類細節，積體電路設計單元1540可判定要製造之finFET的規格。基於這些規格，積體電路設計單元1540可提供用於製造本文中所述半導體裝置封裝之資料。此規格可包括處理半導體晶圓，使得 可調整WFM厚度、WFM材料及/或光暈層以提供預定可接受範圍內之閾值電壓值。
系統1500可有能力進行涉及各種技術之各種產品的分析及製造。舉例而言，系統1500可設計與產生資料以供製造CMOS技術、Flash技術、BiCMOS技術、功率裝置、記憶體裝置(例如，DRAM裝置)、NAND記憶體裝置及/或各種其它半導體技術之裝置。
以上所揭示的特殊具體實施例僅屬描述性，正如本發明可用所屬領域的技術人員所明顯知道的不同但均等方式予以修改並且實踐而具有本文的指導效益。舉例而言，以上所提出的程序步驟可按照不同順序來進行。再者，除了如下面申請專利範圍中所述除外，未意圖限制於本文所示構造或設計的細節。因此，證實可改變或修改以上揭示之特定具體實施例，而且所有此類變例全都視為在本發明的範疇及精神內。因此，本文尋求的保護是如以下申請專利範圍中所提。

Claims (20)

  1. 一種方法，包含：判定第一電晶體閘極之第一閾值電壓，該第一電晶體閘極包含具有第一長度之第一閘極通道；判定第二電晶體閘極之第二閘極通道之第二長度；基於該第二長度判定該第二閘極之程序調整，用於提供該第二電晶體閘極之第二閾值電壓，其中，該第二閾值電壓是在該第一閾值電壓之預定範圍內；以及提供與程序調整有關之資料至程序控制器，用於進行該程序調整。
  2. 如申請專利範圍第1項所述之方法，其中，判定該第一電壓閾值包含判斷該第一電晶體閘極是否為下列其中一者：PFET低電壓閾值(PLVT)、PFET規則電壓閾值(PRVT)、PFET超低電壓閾值(PSLVT)、NFET低電壓閾值(NLVT)、NFET規則電壓閾值(NRVT)或NFET超低電壓閾值(NSLVT)。
  3. 如申請專利範圍第2項所述之方法，其中：該PLVT與該NLVT為約0.20伏特之絕對值；該PRVT與該NRVT為約0.15伏特之絕對值；以及該PSLVT與該NSLVT為約0.25伏特之絕對值。
  4. 如申請專利範圍第1項所述之方法，其中，判定該程序調整包含判定該第一電晶體閘極之第一工作力金屬(WFM)層之厚度及判定該第二電晶體閘極之第二WFM 之厚度，其中，回應於判定該第一閾值電壓為PLVT、PRVT或PSLVT其中至少一者，該第二WMF層比該第一工作力金屬層之該厚度更厚。
  5. 如申請專利範圍第4項所述之方法，其中，該第一電晶體閘極之第一WFM呈第二WFM之相反極性。
  6. 如申請專利範圍第1項所述之方法，其中，判定該程序調整包含判定該第一電晶體閘極之第一工作力金屬層之厚度及判定該第二電晶體閘極之第二工作力金屬之厚度，其中，回應於判定該第一閾值電壓為NLVT、NRVT或NSLVT其中至少一者，該第二工作力金屬層比該第一工作力金屬層之該厚度更厚。
  7. 如申請專利範圍第1項所述之方法，其中，判定該程序調整包含判定用於該第一WFM之第一材料及用於該第二WFM之第二材料。
  8. 如申請專利範圍第1項所述之方法，其中，判定該程序調整包含調整對應於該第二電晶體閘極之源極與汲極區所相鄰之光暈層，其中，調整該光暈層包含提供更薄之光暈層或消除該光暈層。
  9. 如申請專利範圍第4項所述之方法，其中，判定第二工作力金屬之厚度判定該WFM層要在約40A至50A之範圍內。
  10. 一種半導體裝置，包含：包含具有第一長度之第一閘極通道及第一工作力金屬(WFM)層的第一電晶體閘極，其中，該第一電晶體 閘極基於該第一閘極通道具有第一閾值電壓；以及包含具有第二長度之第二閘極通道及第二WFM層的第二電晶體閘極，其中，該第二電晶體閘極基於該第二閘極通道具有第二閾值電壓；其中，該第二WFM層之至少一個特性為該第一WFM層之對應特性之修改版，其中，該特性之該修改版提供要在該第一閾值電壓之預定範圍內之該第二閾值電壓。
  11. 如申請專利範圍第10項所述之半導體裝置，其中，該特性之該修改版包含下列其中一者：該第二WFM層之厚度、該第二WFM之材料類型或該第二WFM層之極性。
  12. 如申請專利範圍第11項所述之半導體裝置，其中，該第二長度大於該第一長度。
  13. 如申請專利範圍第12項所述之半導體裝置，其中，該第二WFM層之該厚度比用於PFET裝置之該第一WFM層之該厚度更大，以及其中，第二WFM層之該厚度比用於NFET裝置之該第一WFM層之該厚度更小。
  14. 如申請專利範圍第12項所述之半導體裝置，其中，該第二WFM層與該第一WFM層之厚度差正比於該第二長度與該第一長度之間的差值。
  15. 如申請專利範圍第10項所述之半導體裝置，其中，該第一閘極通道是在第一源極鰭片與第一汲極鰭片之間形成，並且該第二閘極通道是在第二源極鰭片與第二汲 極鰭片之間形成。
  16. 如申請專利範圍第15項所述之半導體裝置，更包含實質圍繞該第一源極與汲極或該第二源極與汲極其中一者之光暈襯墊，用於影響該第一閾值電壓或該第二閾值電壓其中至少一者。
  17. 如申請專利範圍第10項所述之半導體裝置，其中，該第一閾值電壓與該第二閾值電壓為下列其中一者：PFET低電壓閾值(PLVT)、PFET規則電壓閾值(PRVT)、PFET超低電壓閾值(PSLVT)、NFET低電壓閾值(NLVT)、NFET規則電壓閾值(NRVT)或NFET超低電壓閾值(NSLVT)。
  18. 一種系統，包含：用以製造包含至少一個鰭式場效電晶體(finFET)之半導體裝置的半導體裝置處理系統；以及有效耦接至該半導體裝置處理系統之處理控制器，該處理控制器經組配以控制該半導體裝置處理系統之運作；其中，該半導體裝置處理系統經調適以：判定第一電晶體閘極之第一閾值電壓，該第一電晶體閘極包含具有第一長度之第一閘極通道；判定第二電晶體閘極之第二閘極通道之第二長度；基於該第二長度判定該第二閘極之程序調整，用於提供該第二電晶體閘極之第二閾值電 壓，其中，該第二閾值電壓是在該第一閾值電壓之預定範圍內；以及提供與程序調整有關之資料至該程序控制器，用於進行該程序調整。
  19. 如申請專利範圍第18項所述之系統，更包含經組配用以產生第一設計之設計單元，該第一設計包含用於程序遮罩之界定、用於形成該第一電晶體閘極與該第二電晶體閘極之界定，其中，出自該設計單元之資料是由該處理控制器用於控制該半導體裝置處理系統之運作。
  20. 如申請專利範圍第18項所述之系統，其中，該半導體裝置處理系統經進一步調適以：判定該第一電晶體閘極之第一工作力金屬(WFM)層之厚度及判定該第二電晶體閘極之第二WFM之厚度，其中，回應於判定該第一閾值電壓為該PLVT、PRVT、PSLVT、NLVT、NRVT或NSLVT其中至少一者，該第二WMF層比該第一工作力金屬層之該厚度更厚；調整對應於該第二電晶體閘極之源極與汲極區所相鄰之光暈層，其中，調整該光暈層包含提供更薄之光暈層或消除該光暈層；以及判定第一閘極-源極-汲極設計之第三閾值電壓及第二閘極-汲極-源極設計之第四閾值電壓，並且判定該第二閘極-汲極-源極設計之WFM層之厚度，用於造成該第四閾值電壓處在該第三閾值電壓的預定範圍內。
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US10325824B2 (en) 2019-06-18
TWI675425B (zh) 2019-10-21
CN109087889B (zh) 2023-08-04

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