JP5071899B2 - Dramセル用の分離領域を有する半導体構造及び製造方法 - Google Patents
Dramセル用の分離領域を有する半導体構造及び製造方法 Download PDFInfo
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Description
トランジスタデバイスは多くの半導体アセンブリで利用される。トランジスタデバイスは、たとえば、ダイナミックランダムアクセスメモリ(DRAM)構造及びスタティックランダムアクセスメモリ(SRAM)構造などの、メモリ回路に利用されることができる。半導体デバイス処理の継続する目標は、集積の規模を増し、処理を簡単にし、コストを低減することである。そのような継続する目標のうちの1つ又は複数に向かって前進する、トランジスタ構造を形成する新しい方法を生み出すことが望まれる。
一態様において、本発明は半導体構造を形成する方法に関する。半導体基板が設けられる。基板は、単結晶半導体材料内に延びる複数のトレンチ分離領域を含む。分離領域は、単結晶半導体材料を含む第1領域によって互いに離間される。単結晶半導体材料は、第1領域内でパターニングされて複数のピラーにされる。後続の処理において、ピラーは、トランジスタデバイス内に組み込まれることができる。そのような用途では、ピラーは、トランジスタデバイスの垂直に延びるチャネル領域を備えることができる。
好ましい実施の形態の詳細な説明
本発明は、垂直に延びるピラーを含む半導体構造、及び、そのような構造を形成する方法に関する。特定の態様では、ピラーは、縦型のサラウンディングゲート電界効果トランジスタに組み込まれることができる。そのようなトランジスタは、たとえば、高密度DRAMアレイ及び/又はSRAMアレイなどの高密度メモリアレイに組み込まれることができる。本発明の例示的な態様は、図1〜図21を参照して述べられる。
メモリデバイス408はメモリモジュールに対応することができる。たとえば、シングルインラインメモリモジュール(SIMM)及びデュアルインラインメモリモジュール(DIMM)は、本発明の教示を利用する実施態様において使用され得る。メモリデバイスは、デバイスのメモリセルから読み出し、メモリセルに書き込む異なる方法を提供する種々のデザインのうちの任意のデザインに組み込まれることができる。1つのそのような方法はページモード動作である。DRMにおけるページモード動作は、メモリセルアレイのある行をアクセスし、アレイの異なる列をランダムにアクセスする方法によって定義される。行と列の交差部に格納されたデータは、その列がアクセスされている間に読み出され、出力される。
Claims (6)
- 半導体構造を形成する方法であって、
半導体基板を設けるステップであって、前記半導体基板は第1半導体材料内に延びるトレンチの行を備え、前記行は前記第1半導体材料を含む第1領域によって互いに離間され、前記トレンチは内部に第1誘電体材料を有し、前記トレンチ内の前記第1誘電体材料は誘電体材料の行を形成する、ステップと、
前記半導体基板上に第2半導体材料を形成するステップであって、前記第2半導体材料は、前記第1誘電体材料の行の上を延び、かつ、前記第1誘電体材料の行間の前記第1領域にわたっても延びる、ステップと、
前記第2半導体材料を貫通し、前記第1誘電体材料まで延びる開口を形成するステップと、
前記開口を第2誘電体材料で充填して、誘電体材料の行の高さを前記第2半導体材料の上面まで延ばすステップと、
前記第1及び第2半導体材料をパターニングして、複数のピラーと、該ピラー間の半導体区域とを形成するステップであって、個々の前記ピラー及び前記半導体区域は、前記第1半導体材料の分割部分上に前記第2半導体材料の分割部分を備え、前記複数のピラーは行に沿って配置される、ステップと、
前記ピラーの行に沿って、かつ、前記ピラーと前記半導体区域との間に、ゲート誘電体材料及びゲート線材料を形成するステップと、
前記ピラーの各々の上方領域に第1ソース/ドレイン領域を形成するステップと、
前記半導体区域の各々の上方領域に、前記第1ソース/ドレイン領域と関連付けられた第2ソース/ドレイン領域を形成するステップであって、前記第1ソース/ドレイン領域が、前記ゲート誘電体材料に隣接するチャネル領域を介して、前記第2ソース/ドレイン領域に接続され、その結果、各々が前記チャネル領域と、前記第1ソース/ドレイン領域と、前記第2ソース/ドレイン領域とを含む複数のトランジスタデバイスが形成される、ステップと、
を含む方法。 - 半導体構造を形成する方法であって、
半導体基板を設けるステップであって、前記半導体基板は第1半導体材料内に延びる複数のトレンチを備え、前記第1半導体材料は最上面を備え、前記トレンチは、前記第1半導体材料を含む第1領域によって互いに離間される、ステップと、
前記トレンチを第1誘電体材料で充填するステップと、
前記トレンチ内の前記第1誘電体材料の高さを下げて、前記トレンチ内に誘電体材料の第1線状構造物を形成するステップであって、前記第1線状構造物は前記第1半導体材料の前記最上面よりも低い最上面を有する、ステップと、
前記第1誘電体材料の高さを下げた後に、前記半導体基板上に第2半導体材料を形成するステップであって、前記第2半導体材料は、前記第1線状構造物の上に延び、かつ、前記第1領域にわたっても延びる、ステップと、
前記第2半導体材料を貫通し且つ前記第1誘電体材料まで延びる開口を形成するステップと、
前記開口を第2誘電体材料で充填するステップと、
前記第1及び第2半導体材料をパターニングして、前記第1領域内に複数のピラーを形成するステップであって、個々の前記ピラーは、前記第1半導体材料の分割部分上に前記第2半導体材料の分割部分を備え、前記ピラーは前記第1半導体材料の前記最上面よりも高い最上面を有する、ステップと、
前記第1及び第2半導体材料をパターニングして前記ピラーを形成するのと同時に、前記第2誘電体材料及び前記第2半導体材料をパターニングして、前記第2誘電体材料及び前記第2半導体材料を含む第2線状構造物を形成するステップであって、該第2線状構造物は前記ピラーの間に延び、該第2線状構造物は、前記第2誘電体材料の領域によって互いに分離された前記第2半導体材料の区域を備える、ステップと、
前記ピラーと前記第2線状構造物との間にゲート線材料を形成するステップと、
前記ピラーの各々の中に第1ソース/ドレイン領域を形成するステップと、
前記第2線状構造物内における前記第2半導体材料の前記区域の各々の中に、前記第1ソース/ドレイン領域に関連付けられた第2ソース/ドレイン領域を形成するステップであって、前記第1ソース/ドレイン領域は前記ゲート線材料を介して前記第2ソース/ドレイン領域にゲート制御可能に接続され、その結果、各々が前記第1ソース/ドレイン領域及び前記第2ソース/ドレイン領域を含む複数のトランジスタデバイスが形成される、ステップと、
を含む方法。 - 半導体構造であって、
単結晶半導体材料を含む半導体基板と、
前記単結晶半導体材料内にあり、前記半導体基板の表面に平行な第1の方向に沿って延びる複数の分離領域であって、前記第1の方向に延びる前記単結晶半導体材料の細長い領域によって互いに離間された複数の分離領域と、
前記半導体基板の表面に平行で且つ前記第1の方向に対して直角な第2の方向に沿って延びる複数の線状構造物であって、前記分離領域上の誘電体領域と、該誘電体領域間の半導体区域とを有する複数の線状構造物と、
前記単結晶半導体材料から上に延びるピラーのアレイであって、該アレイは、前記第1の方向に沿った列と、前記第2の方向に沿った行とを備え、前記アレイの前記列は、前記分離領域の間で、かつ、前記単結晶半導体材料の前記細長い領域に沿って存在し、前記ピラーは、前記細長い領域から上に延びる前記単結晶半導体材料のメサ状領域を備える、アレイと、
前記ピラーの上側領域における第1ソース/ドレイン領域と、
前記線状構造物の前記半導体区域内の第2ソース/ドレイン領域と、
前記第1ソース/ドレイン領域と前記第2ソース/ドレイン領域との間のチャネル領域と、
前記第2の方向に沿って延びる複数のゲート線の行であって、前記ピラーのアレイの行に沿って延びる複数のゲート線の行と、
を備え、
前記ゲート線の行、前記チャネル領域、前記第1ソース/ドレイン領域及び前記第2ソース/ドレイン領域は、複数のトランジスタデバイスを形成し、個々のトランジスタデバイスが、前記第1ソース/ドレイン領域のうちの1つと、それに関連付けられた前記第2ソース/ドレイン領域のうちの1つと、前記第1ソース/ドレイン領域のうちの前記1つから前記第2ソース/ドレイン領域のうちの前記1つまで延びる前記チャネル領域のうちの1つと、前記ゲート線の行内で且つ前記チャネル領域のうちの前記1つに近接するゲートとを備える、半導体構造。 - 前記ピラーは、前記単結晶半導体材料の前記メサ状領域からなる、請求項3に記載の半導体構造。
- 前記単結晶半導体材料は第1半導体材料であり、前記個々のピラーの少なくとも一部は、前記単結晶半導体材料の前記メサ状領域の上に第2半導体材料の分割部分を備える、請求項3に記載の半導体構造。
- トランジスタデバイスの前記第2ソース/ドレイン領域に電気的に接続されたコンデンサと、
前記トランジスタデバイスの前記第1ソース/ドレイン領域に電気的に接続されたビット線と、
をさらに備える、請求項3に記載の半導体構造。
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PCT/US2004/034587 WO2006022765A1 (en) | 2004-08-24 | 2004-10-19 | Semiconductor construction with isolation regions for dram cell and production method |
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