TWI234203B - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- TWI234203B TWI234203B TW092131157A TW92131157A TWI234203B TW I234203 B TWI234203 B TW I234203B TW 092131157 A TW092131157 A TW 092131157A TW 92131157 A TW92131157 A TW 92131157A TW I234203 B TWI234203 B TW I234203B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 238000005108 dry cleaning Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 16
- 239000001257 hydrogen Substances 0.000 claims description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 238000009832 plasma treatment Methods 0.000 claims description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 abstract description 4
- 239000002184 metal Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 19
- 239000000126 substance Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 210000000496 pancreas Anatomy 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000002203 pretreatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 241000238631 Hexapoda Species 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000003446 ligand Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
1234203
【本發明所屬之技術領域】 本發明是有關一種製造半 可防止由於自然氧化膜所引起 resistance )之增加的半導體 【先前技術】 導體元件的方法,特別是有關 接觸電阻(contact 元件的製造方法。 产 如眾所周知,除了半導體技術的進展以外,高速操作與 高積體化半導體元件的發展也在積極的進行中。因此,精細 與高積體化的電路圖樣(pattern )即為必需,依照此一傾 向,多種製程技術也已開發並使用來獲得優良的元件特性。
特別是,為了增進半導體元件的操作效率,新的接觸工 程技術業已開發。在此接觸工程技術中,當一介於上、下部 圖樣(p a 11; e r η )之間的接觸係不穩定,或是接觸電卩且增加 時,雖然圖樣(pattern )大小的微細化可以達成,但是半 導體元件的可靠度卻缺乏,且難以執行高速動作。 以下,簡單說明一種從來的接觸工程。 第1 A圖至第1 C圖係工程斷面圖,說明一傳統的製造,半 導體元件的方法。 請參看第1A圖,首先製備一矽基板1,在其上,所形成 的一預定的下部構造物有一接合區2。其次,一層間絕緣膜 3乃沈積於整個碎基板1的表面上’以覆蓋下部構造物。接 著,一蝕刻罩,例如,一感光膜圖樣4利用已知的製耩形成 於層間"電膜3 ’該感光膜圖樣4定義了 一接觸形成隱。 請參第1 B圖,層間絕緣膜3係藉由使用光阻圖樣4來# 刻。因此,形成了 一露出接合區2的接觸孔5,然後,伏用
1234203 、發明說明(2) 作為蝕刻罩之感光膜圖樣4乃被去除 明蒼第1 C圖,一導電膜,例如,一金屬膜乃被沈積於層 間絕緣膜3上,以埋入接觸孔5,金屬膜係被形成圖案以形成 一與砍基板1的接合區2相接觸的金屬配線6。 當形成金屬配線6時,一中間插入物質(intermediate plUg materiaU ,亦即,多晶石夕膜7可被插入於金屬配線6 與接合區2之間情形如第2圖所示。而在第2圖中,參考 號瑪8代表一氧化膜8。 另一方面,從來製造丰墓雕― A ^ ^ L 牛V肢凡件時,接觸蝕刻期間所生 成的I虫刻殘留物及表面的自铁氦 曰A虱化胰必需予以去除。為了回 復#刻所造成之傷害,在接觸 ^ /n /A ^ A 丧觸孔形成以後,使用nf3/o2、 SF6/〇2、CF4/〇2、或入1"/02的電將私 / I: 分、隹一二么 ;/ J兒水乾式洗淨與濕式洗淨製程乃 依序進仃,然後,沈積一金屬膜。 然而,在形成接觸導電膜時:由於 (sputtering )裝置沈積金屬 ^ 積多晶箱在洗淨後的=面匕=蒸=装置沈 是,金屬配線6與基板接合Ϊ2觸表面形成自然氧化膜10。於 ⑶以…就無法達成。因二之广的完全歐姆接觸(―ic 體元件品質的不良。口此增加了接觸電阻,並導致半導 為了解決上述的問題,傳 Αι*電漿進行物理性濺鍍,而作 前處理。而且,為了使利用多 化膜最小化,一基板乃裝入於 統上係於沈積金屬膜以前,以 為流程場合中(i n — s i t u )的 晶矽膜沈積設備的形成自然氧 ~基板裝入部,在基板裝入部
1234203
五、發明說明(3) 分開地被關 於1 0 0 p p m的 的門乃開啟 然而, 提供一清楚 增加了接觸 <發明要解 本發明 此,本發明 其防止了由 而且, 供了清潔的 高,此為本 【本發明之 為了達 造方法乃包 了一具有接 述半導體基 成暴露出接 半導體基板 之氣圍下對 上的自然氧 區的表面, 償且在接合 閉,且氧的濃度由於高純度氮的流動而降 狀態時,一設於基板裝入部與一高溫沈積放& 乂 ,而基板則裝入於高溫沈積管之中。 s之間 此步驟只可使自然氧化膜的影響最小化, 〜 的接觸面。結果’因為界面的不良,益 b ^ ^ …、力避免地 決的問題> 即疋為要解決發生於習見技術之上述問題者 之一目的乃在提供一種製造半導體元件的方因 於自然氧化膜所導致接觸電阻的增加。 〆 依本發明的製造方法所製成的半導體 1千’ jMl 接觸面,因此元件特性與製程的良率妗 發明的另一目的。 勺可大為提 内容】 从丄a < a的,不赞明尸;τ徒供的半導體元件 括下列步驟:(1 )製備一半導體基板, 、 合區的下部構造物;(2 )形成一層間絕緣膜於用 板的整個表面上;(3)藉著蝕刻層間絕绦腊;^ 合區的接觸孔;(4)順序地乾式洗淨並濕式 > 由於接觸孔所露出的表面;(5)在一還^ 1氣^ 已清洗的接觸表面作前處理以去除形成在接觸 化膜;(6)於製程場合中追加摻雜不純物至接合 ^此在前處理期間所造成不純物的損失乃獲得" 區表面的不純物濃度乃增加;以及,(7)在*製于程
第8頁 1234203 五、發明說明(4) _ “中沈和‘電膜於上述接觸孔及層間絕 較佳地,還原氣體為氫氣、胰上。 驟(5)係利用一低溫電聚 ' z W ,更佳的是,步 ! :〇τ滎處理係氫氣以1〜ι〇00--的ii:動: 1〜3 0 0 丁 〇 r r的壓力曰杳、、w 0 Λ Λ。 J狀况流動,於 溫熱處理則係氫氣i ^ C的溫度下進行之。所述高 的壓力,且m〜:狀況流動,而於1_ 、1UUUC的溫度下進行之。 受損之5蚰Z述步驟(6 )追加推雜不純物係利用供庫勹八 又損之不純物的氣體分子 刃用供應包含一 處理或高溫熱處理。 °又f中而進仃,且進行低溫電漿 依照本發明,& 供了氫氣或其他的還 1L洗淨後,接觸導電膜形成設備提 自然氧化膜。而且氧體,以去除在接觸表面所形成的 製程場合(i n s · t在接合區表面的不純物的濃度係由於在 一去除了自然氧化膜的、、主::广的接觸表面,因此,提供了 於自然氧化膜& π ^办接觸表面。於是,有效防止了由 本:化膜所引起之接觸電阻的增加。 1明之其他目的盥^ 具體實施例的$ _ > /、特徵,麥妝下列依附圖所作之較佳 【本發明之實施方即可得到明確的了解。 第“圖' :::本發明之較佳具體實施例。 施例製程縱截面圖Υ 5兄明本發明之製造半導體元件的方法實 +導體基板41,其上形成了一具有接
f 9頁 請參看第4Α圖,一束 1234203 五、發明說明(5) 半導體 物的深 合之下部構造物乃被製備完成。在接合區42中, 的¥私率係依照不純物的種類,不純物的濃度與不 度而調整。 、明蓼看第4B圖,一層間絕緣膜43係沈積於整個矽基板41 $表面’以覆蓋具有接合區4 2的下部構造物,層間絕緣膜4 3 係使用—已知的製程來蝕刻以形成一將接合區露出的接觸孔 為了回復飯刻殘留物與石夕晶核(1 a M i c e )缺陷對於接 觸表面所造成之蝕刻損傷,一使用NF^/O2、SFe/〇2、(^/〇2或 2之篆漿乾式洗淨乃被進行’然後,以二氧化石夕膜钱刻 液之濕式洗淨再被進行。 在石夕接觸(s i 1 i con contact )的場合,一電漿乾式洗 淨去除了乾式蝕刻所導致的物理性的損傷。在碳系之钱刻殘 留物被氧化並被去除之後,殘留的氧化膜乃藉著使用氣系化 學溶液的濕式洗淨來去除。結果,可得到清潔的接觸表面。 請參看第4C圖,所述基板結果物係設有時間的遲延地裝 入濺鍍設備或化學蒸氣沈積設備中,而此濺鍍設備沈積一 ^ 觸導電膜,亦即,金屬膜。化學蒸氣沈積設備則沈積^晶石夕 膜’此時,在所述基板結果物裝入設備的過程中,_自然氧 化膜乃產生在接觸表面上。在本發明的此實施例中,為了去 除產生在接觸表面上的自然氧化膜,在基板結果物裝入裝備 内以後’接觸表面係首先在還原性氣體的氣圍中進行前處 理,此還原性氣體較佳的包括氫氣或氨氣。 所述前處理包括一低溫電漿處理,其係藉由將氣氣以
第10頁 1234203 五、發明說明(6) 1〜1 0 0 0 s c c m的狀況洁無从,
Rnn aa ^ ^ 兄机動,於1〜3 0 0Torr的壓力,且常溫〜 b 0 0 C的溫度下進杆夕。i iη 之所述前處理也包括一高溫熱處理,
Hi 5Slm的狀況流動,於1〜3〇Wrr的壓力,且 強 C的溫度下進行。在氫氣的處理時,由於氫氣加 ^ ί Γ 基板的表面,亦即接合區42的不純物,乃與 :虱::而形成一氫化物,❿此氫化物並以氣體的形態被釋 、主初沾ί,形成於接觸表面的自然氧化膜乃被去除以獲得一 :靖巧表面。但是,在一鱗(ρ)掺雜接合區的場合于, 斤1 2種還原反應,在接觸表面不只形成自然氧化膜,而氫 氣也會,磷(Ρ)結合並以ΡΗ3氣之形態釋放出來。 氧 另方面’备此接合區4 2的不純物與氫氣結合,且此翁 化口物被釋放出來時,所述接合區4 2的導電率乃變差,且拉 =阻=增加。因此,在本發明中,在進行上述的氫氣前處 ^ ’ 一包含一相對不純物的物質乃供應至在製程場合 j ln Sltu )中的設備,而低溫電漿處理或高溫熱處理乃進 行仏在接合區4 2的不純物的損傷。例如,磷(p )摻雜 ,合區的場合,PH3氣體係以10至10 OOsccm的狀況流動,電 漿在壓力為1〜30 0T〇rr,溫度為常溫〜6〇〇它的狀況下被形 成而且’P^3氣體在1〜5slm的狀況下流動時,熱分解於壓 力為1〜300T〇rr,溫度為700〜1 0 0 0 °C的情形下產生,使得 石森(P )追加摻雜在接觸表面上。 睛參看第4D圖,在進行接觸表面的前處理後,一金屬膜 乃於製程場合中沈積於基板結果物上,以將接觸孔45覆蓋。 然後’所述金屬膜乃被形成圖樣(pattern )以形成一與接
第11頁 1234203 五、發明說明(7) 合區接觸的金屬配線46。 一以後,依序進行公知的後續製程以獲得本發明之半導體 件。 $屬配線46與接合區42之間的接觸可藉由插入一層間插 物貝例如多晶矽膜於金屬配線4 6與接合區4 2之間來達 =。f,種場合下,插入物質係通過—沈積後再#刻(dd 或化學機械拋光(CMp,Chemicai 开;二Λ又來形成、。其*,通過沈積與蝕刻氧化膜而 線46。ή ° ’’、、、後’形成一與層間插入物質相接觸的金屬配 體’例如氫氣之前處 摻雜,以及一接觸導電 %合(in-situ)中連 的歐姆接觸表面 所製造的半導體元件, ’可維持低的接觸電 依…、本發明,由於使用一還原氣 理,一用以補償損傷的不純物的追加 月,的沈積乃利用相同的設備,在製程 續地進行,金屬配線即形成有一理想 (ohmic contact surf ace )的狀態, 因此,在利用依照本發明的方法 自然氧化膜可從接觸表面完全 阻。 叉方丨示 <發明之效果> 依…、本發明,在接觸孔被洗淨以 士 =置可供應例如氫氣的還原氣體至 i在接觸表面的自然氧化膜,而此裝 ;觸導電膜至接觸表面中,如此,即 軋化膜的清潔接觸表面。於是,其 後,濺鍍或化學蒸氣 一接觸表面,以去除 置在製程場合中沈積 可提供一已去除所述 有效地防止了由於
1234203 五、發明說明(8) 氧化膜所引起之接觸電阻的增加。更由於本發明在於製程場 合中的前處理期間補償損傷的不純物後,沈積接觸導電膜, 其即可防止半導體元件的特性變差。 因此,由於本發明形成一理想的歐姆接觸,其乃增進了 元件的特性與製造的良率。 需陳明者,以上所述者乃是本發明較佳具體實施例,若 依本發明之構想所作之改變,其產生之功能作用,仍未超出 說明書與圖示所涵蓋之精神時,均應在本發明之範圍内,合 予陳明。
第13頁 1234203 圖式簡單說明 第1A圖至第1C圖為截面圖,解釋一種傳統製造半導體元 件的方法。 第2圖係截面圖,解釋另一種傳統製造半導體元件的方 法 發 所 法 方 的 件 元 體 導 半 造 製 統 傳 釋 解 圖 面 截 係 圖 3 第 法 方 的 件 元 體 導 半 造 製 之 明 發 本 明 說。 圖圖 4D面 第截 至縱 。圖程 題4A製 問第例 的 施 生 實 【圖式中元件名稱與符號對照】 1 : $夕基板 2 接 合 區 3 : 層間絕緣膜 4 感 光 膜 圖 樣 5 : 接觸孔 6 金 屬 配 線 7 : 多晶$夕膜 8 琴— 氧 化 膜 10 :自然氧化膜 41 半 導 體 基 板 42 :接合區 43 層 間 絕 緣 膜 45 :接觸孔 46 金 屬 配 線
第14頁
Claims (1)
1234203 六、申請專利範圍 1 · 一種製造半導體元件的方法 製備一半導體基板,其上带成包括下列步驟: 部構造物; $成了一具有接合區的下 (2 )形成一層間絕緣膜於上述丰 (3) 藉著蝕刻層間絕緣膜而形^ =基板的整個表面上 (4) 順序地乾式洗淨並濕式洗J :=出接合區的接觸孔 所露出的表面; ‘體基板由於接觸孔 (5 )在一還原性氣體之氣圍下 處理以去除形成在接觸孔上的—/肖洗的接觸表面作前 ⑷於製程場合中追㈣雜不= 此在前處理期間所造成不純物的損关至接s合區的表面,如 表面的不純物濃度乃增加;以及,、乃獲得補償且在接合區 (7 )在製程場合中沈積一带 緣膜上。 、 私、;上述接觸孔及層間絕 2·如申請專利範圍第丨項之製造半 中還原氣體為氫氣或氨氣。 ¥體凡件的方法,其 3·如申請專利範圍第丨項之製造 中步驟⑸係利用-低溫電漿處理或一高!::的方法,其 4. 如申請專利範圍第3項之製造半熱;理來進行。 中低溫電漿處理係氫氣 -兀件的方法,其 町的壓力且常^ :广’咖的狀況流動,於卜 刀且吊,皿〜600 〇C的溫度下進行之。 5. =中請專利範圍第3項之製造半導體元件豆 中所述咼溫熱處理則係氫氣以i〜Ssl 而厂 3辦町的壓力,且700〜1〇〇(Kc的溫度下進兄行^動。,而於1〜
第15頁 1234203 六、申請專利範圍 6.如申請專利範圍第1項之製造半導體元件的方法,其 中所述步驟(6)追加摻雜不純物係利用供應包含一受損之不 純物的氣體分子至設備中而進行,且進行低溫電漿處理或高 溫熱處理。
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